Abstract: In a semiconductor device including a plurality of insulated gate switching cells each of which has a gate electrode, an emitter electrode that is commonly provided to cover the plurality of insulated gate switching cells, and a bonding wire connected to the emitter electrode, a gate driving voltage being applied to the gate electrode of each insulated gate switching cell so that emitter current flows through the emitter electrode, mutual conductance of each insulated gate switching cell is varied in accordance with the distance from the connection portion corresponding to the bonding position of the bonding wire so that the emitter current flowing through the emitter electrode is substantially equal among the plurality of insulated gate switching cells.

Abstract: The present teachings provide a semiconductor device comprising: an IGBT element region, a diode element region and a boundary region provided between the IGBT element region and the diode element region are formed in one semiconductor substrate. The boundary region comprises a second conductivity type first diffusion region, a first conductivity type second diffusion region, and a second conductivity type third diffusion region. A first drift region of the IGBT element region contiguously contacts the first diffusion region of the boundary region, and a second drift region of the diode element region contiguously contacts the first diffusion region of the boundary region. A first body region of the IGBT element region contiguously contacts the second diffusion region of the boundary region, and a second body region of the diode element region contiguously contacts the second diffusion region of the boundary region.

Abstract: Various structures and methods for improving the performance of trench-shielded power semiconductor devices and the like are described. An exemplary device comprises a semiconductor region having a surface, a first area of the semiconductor region, a well region of a first conductivity type disposed in the semiconductor region and around the first area, and a plurality of trenches extending in a semiconductor region. Each trench haves a first end disposed in a first portion of the well region, a second end disposed in a second portion of the well region, and a middle portion between the first and second ends and disposed in the first area. Each trench further having opposing sidewalls lined with a dielectric layer, and a conductive electrode disposed on at least a portion of the dielectric layer.

Abstract: Fashioning a quasi-vertical gated NPN-PNP (QVGNP) electrostatic discharge (ESD) protection device is disclosed. The QVGNP ESD protection device has a well having one conductivity type formed adjacent to a deep well having another conductivity type. The device has a desired holding voltage and a substantially homogenous current flow, and is thus highly robust. The device can be fashioned in a cost effective manner by being formed during a BiCMOS or Smart Power fabrication process.

Abstract: According to one embodiment, a semiconductor device includes a first major electrode, a first semiconductor layer, a first conductivity type base layer, a second conductivity type base layer, a first conductivity type second semiconductor layer, a gate insulating film, a gate electrode, and a second major electrode. The gate insulating film is provided on a side wall of a trench penetrating the second conductivity type base layer to reach the first conductivity type base layer. The gate electrode is provided inside the gate insulating film in the trench. The second major electrode is provided on the second semiconductor layer and electrically connected with the second semiconductor layer. A maximum impurity concentration in the second semiconductor layer is within ten times a maximum impurity concentration in the second conductivity type base layer.

Abstract: According to an embodiment, a semiconductor device includes a first trench being provided in an N+ substrate. An N layer, an N? layer, a P layer, and an N+ layer are formed in a stacked manner to cover the first trench. The semiconductor device includes second and third trenches. The P+ layer is formed to cover the second trench. The trench gates are formed to cover the third trenches.

Abstract: Each of first base regions of sequentially layered first IGBT and second IGBT has a peripheral section in the vicinity of the side face of the semiconductor substrate. Each of the IGBTs includes a P-type peripheral base region that is adjacent to the peripheral section of the first base region of the N-type to form a diode and a diode electrode that is formed on an upper face of the peripheral section of the first base region, thereby electrically connecting the diode electrode and a collector electrode of each of the IGBTs. When the semiconductor device is ON, current flows at the center side of the semiconductor substrate separated from the side face. When current in a reverse direction is generated when the semiconductor device is OFF, current in a reverse direction flows in the vicinity of the side face of the semiconductor substrate.

Abstract: According to an embodiment, a semiconductor device includes a first trench being provided in an N+ substrate. An N layer, an N? layer, a P layer, and an N+ layer are formed in a stacked manner to cover the first trench. The semiconductor device includes second and third trenches. The P+ layer is formed to cover the second trench. The trench gates are formed to cover the third trenches.

Abstract: A semiconductor package that includes a conductive can, a power semiconductor device electrically and mechanically attached to the inside surface of the can, and an IC semiconductor device copackaged with the power semiconductor device inside the can.

Abstract: A N-channel lateral insulated-gate bipolar transistor includes a semiconductor substrate, a drift layer, a collector region, a channel layer, an emitter region, a gate insulation film, a gate electrode, a collector electrode, an emitter electrode. The collector region includes a high impurity concentration region having a high impurity concentration and a low impurity concentration region having a lower impurity concentration than the high impurity concentration region. The collector electrode is in ohmic contact with the high impurity concentration region and in schottky contact with the low impurity concentration region.

Abstract: An IGBT, which is a vertical type IGBT allowing for reduced on-resistance while restraining defects from being produced, includes: a silicon carbide substrate, a drift layer, a well region, an n+ region, an emitter contact electrode, a gate oxide film, a gate electrode, and a collector electrode. The silicon carbide substrate includes: a base layer made of silicon carbide and having p type conductivity; and a SiC layer made of single-crystal silicon carbide and disposed on the base layer. The base layer has a p type impurity concentration exceeding 1×1018 cm?3.

Abstract: An electrostatic discharge protection device is coupled between a first power line and a second power line and comprises a P-type well, a first N-type doped region, a first P-type doped region, a second P-type doped region and a second N-type doped region. The first N-type doped region is formed in the P-type well. The first P-type doped region is formed in the first N-type doped region. The second P-type doped region comprises a first portion and a second portion. The first portion of the second P-type doped region is formed in the first N-type doped region. The second portion of the second P-type doped region is formed outside of the first N-type doped region. The second N-type doped region is formed in the first portion of the second P-type doped region. The first P-type doped region, the first N-type doped region, the second P-type doped region and the second N-type doped region constitute an insulated gate bipolar transistor (IGBT).

Abstract: A semiconductor device includes a vertical IGBT and a vertical free-wheeling diode in a semiconductor substrate. A plurality of base regions is disposed at a first-surface side portion of the semiconductor substrate, and a plurality of collector regions and a plurality of cathode regions are alternately disposed in a second-surface side portion of the semiconductor substrate. The base regions include a plurality of regions where channels are provided when the vertical IGBT is in an operating state. The first-side portion of the semiconductor substrate include a plurality of IGBT regions each located between adjacent two of the channels, including one of the base regions electrically coupled with an emitter electrode, and being opposed to one of the cathode regions. The IGBT regions include a plurality of narrow regions and a plurality of wide regions.

Abstract: A semiconductor device includes a baseplate and a first and a second insulated gate bipolar transistor (IGBT) substrate coupled to the baseplate. The semiconductor device includes a first and a second diode substrate coupled to the baseplate and a first, a second, and a third control substrate coupled to the baseplate. Bond wires couple the first and second IGBT substrates to the first control substrate. Bond wires couple the first and second IGBT substrates to the second control substrate via the first and second diode substrates, and bond wires couple the first and second IGBT substrates to the third control substrate via the second diode substrate.

Abstract: On a main surface of a semiconductor substrate, an N? semiconductor layer is formed with a dielectric portion including relatively thin and thick portions interposed therebetween. In a predetermined region of the N? semiconductor layer, an N-type impurity region and a P-type impurity region are formed. A gate electrode is formed on a surface of a portion of the P-type impurity region located between the N-type impurity region and the N? semiconductor layer. In a predetermined region of the N? semiconductor layer located at a distance from the P-type impurity region, another P-type impurity region is formed. As a depletion layer block portion, another N-type impurity region higher in impurity concentration than the N? semiconductor layer is formed from the surface of the N? semiconductor layer to the dielectric portion.

Abstract: An embodiment of an integrated electronic device formed in a body of semiconductor material, which includes: a substrate of a first semiconductor material, the first semiconductor material having a first bandgap; a first epitaxial region of a second semiconductor material and having a first type of conductivity, which overlies the substrate and defines a first surface, the second semiconductor material having a second bandgap wider than the first bandgap; and a second epitaxial region of the first semiconductor material, which overlies, and is in direct contact with, the first epitaxial region. The first epitaxial region includes a first buffer layer, which overlies the substrate, and a drift layer, which overlies the first buffer layer and defines the first surface, the first buffer layer and the drift layer having different doping levels.

Abstract: In a semiconductor device, an IGBT cell includes a trench passing through a base layer of a semiconductor substrate to a drift layer of the semiconductor substrate, a gate insulating film on an inner surface of the trench, a gate electrode on the gate insulating film, a first conductivity-type emitter region in a surface portion of the base layer, and a second conductivity-type first contact region in the surface portion of the base layer. The IGBT cell further includes a first conductivity-type floating layer disposed within the base layer to separate the base layer into a first portion including the emitter region and the first contact region and a second portion adjacent to the drift layer, and an interlayer insulating film disposed to cover an end of the gate electrode. A diode cell includes a second conductivity-type second contact region in the surface portion of the base layer.

Abstract: There is known a semiconductor device in which an IGBT structure is provided in an IGBT area and a diode structure is provided in a diode area, the IGBT area and the diode area are both located within a same substrate, and the IGBT area is adjacent to the diode area. In this type of semiconductor device, a phenomenon that carriers accumulated within the IGBT area flow into the diode area when the IGBT structure is turned off. In order to prevent this phenomenon, a region of shortening lifetime of carriers is provided at least in a sub-area that is within said IGBT area and adjacent to said diode area. In the sub-area, emitter of IGBT structure is omitted.

Abstract: The semiconductor device includes a P-type semiconductor region and an MOS transistor. MOS transistor includes a gate electrode, a collector electrode, a drain electrode, an N-type impurity region and a P-type impurity region. N-type impurity region is electrically connected to the drain electrode. P-type impurity region is electrically connected to the collector electrode. P-type impurity region is electrically connected to the drain electrode. The semiconductor device further includes an N-type impurity region and an electrode. N-type impurity region is electrically connected to the gate electrode. The electrode is formed on the P-type semiconductor region with an insulating film therebetween, and is electrically connected to gate electrode. Thereby, an element footprint can be reduced while maintaining characteristics.

Abstract: A sinker layer is in contact with a first conductivity-type well, and is separated from a first conductivity-type collector layer and a second conductivity-type drift layer. A second conductivity-type diffusion layer (second second-conductivity-type high-concentration diffusion layer) is formed in the surface layer of the sinker layer. The second conductivity-type diffusion layer has a higher impurity concentration than that of the sinker layer. The second conductivity-type diffusion layer and the first conductivity-type collector layer are isolated from each other with an element isolation insulating film interposed therebetween.

Abstract: A method of forming a semiconductor device having an asymmetrical source and drain. In one embodiment, the method includes forming a gate structure on a first portion of the substrate having a well of a first conductivity. A source region of a second conductivity and drain region of the second conductivity is formed within the well of the first conductivity in a portion of the substrate that is adjacent to the first portion of the substrate on which the gate structure is present. A doped region of a second conductivity is formed within the drain region to provide an integrated bipolar transistor on a drain side of the semiconductor device, in which a collector is provided by the well of the first conductivity, the base is provided by the drain region of the second conductivity and the emitter is provided by the doped region of the second conductivity that is present in the drain region. A semiconductor device formed by the above-described method is also provided.

Abstract: A semiconductor device includes a switching element having: a drift layer; a base region; an element-side first impurity region in the base region; an element-side gate electrode sandwiched between the first impurity region and the drift layer; a second impurity region contacting the drift layer; an element-side first electrode coupled with the element-side first impurity region and the base region; and an element-side second electrode coupled with the second impurity region, and a FWD having: a first conductive layer; a second conductive layer; a diode-side first electrode coupled to the second conductive layer; a diode-side second electrode coupled to the first conductive layer; a diode-side first impurity region in the second conductive layer; and a diode-side gate electrode in the second conductive layer sandwiched between first impurity region and the first conductive layer and having a first gate electrode as an excess carrier injection suppression gate.

Abstract: This invention discloses an insulated gate bipolar transistor (IGBT) formed in a semiconductor substrate. The IGBT comprises a buffer layer of a first conductivity type formed below an epitaxial layer of the first conductivity having body and source regions therein. The IGBT further includes a lowly doped substrate layer below the buffer layer and a dopant layer of a second conductivity type disposed below the lowly doped substrate layer and above a drain electrode of said IGBT attached to a bottom surface of said semiconductor substrate wherein the dopant layer of the second conductivity type has a higher dopant concentration than the lowly doped substrate layer.

Abstract: An object of the present invention is to provide a MOS type semiconductor device allowing production at a low cost without lowering a breakdown voltage and avoiding increase of an ON resistance.

Abstract: A first annular isolation trench is formed in a periphery of an element region, and a second annular isolation trench is formed around the first annular isolation trench with a predetermined distance provided from the first annular isolation trench, and a semiconductor layer between the first annular isolation trench and the second annular isolation trench is separated into a plurality of portions by a plurality of linear isolation trenches formed in the semiconductor layer between the first annular isolation trench and the second annular isolation trench, and the semiconductor layer (source-side isolation region) which opposes a p-type channel layer end portion and is located between the first annular isolation trench and the second annular isolation trench is separated from other semiconductor layers (drain-side isolation regions) by the linear isolation trenches.

Abstract: Aspects of the invention are directed to a three-level power converter that has, as one phase, a bidirectional switching element connected to the series connection point of a series circuit of a first insulated gate bi-polar transistor (“IGBT”) and second IGBT and an intermediate electrode of a direct current power supply. Also included is a fuse connected between the bidirectional switching element and the intermediate electrode of the direct current power supply, and an overcurrent shutdown unit provided in each gate drive circuit of the first and second IGBTs, are provided as protection from a power supply short circuit phenomenon occurring in the event of a short circuit failure of any of the IGBTs or diodes.

Abstract: A semiconductor device having an IGBT includes: a substrate; a drift layer and a base layer on the substrate; trenches penetrating the base layer to divide the base layer into base parts; an emitter region in one base part; a gate element in the trenches; an emitter electrode; and a collector electrode. The one base part provides a channel layer, and another base part provides a float layer having no emitter region. The gate element includes a gate electrode next to the channel layer and a dummy gate electrode next to the float layer. The float layer includes a first float layer adjacent to the channel layer and a second float layer apart from the channel layer. The dummy gate electrode and the first float layer are coupled with a first float wiring on the base layer. The dummy gate electrode is isolated from the second float layer.

Abstract: A silicon carbide semiconductor device includes: a semiconductor substrate having a silicon carbide substrate, a first semiconductor layer, a second semiconductor layer, and a third semiconductor layer; a trench penetrating the second and the third semiconductor layers to reach the first semiconductor layer; a channel layer on a sidewall and a bottom of the trench; an oxide film on the channel layer; a gate electrode on the oxide film; a first electrode connecting to the third semiconductor layer; and a second electrode connecting to the silicon carbide substrate. A position of a boundary between the first semiconductor layer and the second semiconductor layer is disposed lower than an utmost lowest position of the oxide film.

Abstract: A voltage mitigating element mitigating a voltage applied across a gate insulating film in an off state of an insulated gate bipolar transistor (IGBT) is arranged to a gate electrode node of a P-channel MOS transistor provided for suppressing flow-in of holes at the time of turn-off of the IGBT. Withstanding voltage characteristics are improved and an occupation area thereof is reduced while maintaining switching characteristics and a low on-resistance of an insulated gate bipolar transistor.

Abstract: Insulated gate bipolar transistor (IGBT) electrostatic discharge (ESD) protection devices are presented. An IGBT-ESD device includes a semiconductor substrate and patterned insulation regions disposed on the semiconductor substrate defining a first active region and a second active region. A high-V N-well is formed in the first active region of the semiconductor substrate. A P-body doped region is formed in the second active region of the semiconductor substrate, wherein the high-V N-well and the P-body doped region are separated with a predetermined distance exposing the semiconductor substrate. A P+ doped drain region is disposed in the high-V N-well. A P+ diffused region and an N+ doped source region are disposed in the P-body doped region. A gate structure is disposed on the semiconductor substrate with one end adjacent to the N+ doped source region and the other end extending over the insulation region.

Abstract: An IGBT transistor includes a drift region, at least one body region housed in the drift region and having a first type of conductivity, and a conduction region, which crosses the body region in a direction perpendicular to a surface of the drift region and has the first type of conductivity and a lower resistance than the body region. The conduction region includes a plurality of implant regions, arranged at respective depths from the surface of the drift region.

Abstract: A power semiconductor module includes a plurality of sets of semiconductor switching elements, a molded resin casing containing the semiconductor switching elements, screw holders for receiving mounting screws formed at bottom regions of four corners of the molded resin casing, first terminal blocks having main circuit terminals, and arranged on a central region of a top surface of the molded resin casing, and second terminal blocks having control terminals arranged at a side edge of the molded resin casing apart. Insulating separation walls having a configuration of a rib erect from a surface of the second terminal blocks, and are interposed between groups of the control terminals corresponding to the sets of semiconductor switching elements, and between the screw holder including the mounting screw therein on the molded resin casing and the control terminal at a high voltage side adjacent to the screw holder.

Abstract: A manufacturing method of a semiconductor device 10 includes forming a plurality of second conductive second semiconductor regions at specific intervals on one main surface of a first conductive first semiconductor region, the plurality of second conductive second semiconductor regions being opposite to the first conductive first semiconductor region, forming a plurality of the first conductive third semiconductor regions on a main surface of the second semiconductor region, the plurality of the first conductive third regions being separated from each other, forming a plurality of holes at specific intervals on an another main surface which faces the one main surface of the first semiconductor region, the plurality of holes being separated from each other, forming a pair of adjacent second conductive fourth semiconductor regions which are alternately connected at a bottom part of the hole within the first semiconductor region, and burying an electrode within the hole.

Abstract: A semiconductor device provided with: an island and an island which are separated from each other; leads which approach the islands at one end; a control element which is attached to the island and is connected to a lead through a thin metal wire; and a switching element which is attached to the island and is connected to the lead through a metal wire. Further, the thin metal wire and the thin metal wire are arranged so as to the intersect.

Abstract: A cooling member for withdrawing heat from a heat containing device is disclosed. The cooling member can have a housing with a fluid inlet, a fluid outlet and a plurality of irregular-shaped fins located at least partially therewithin. In addition, a plurality of irregular-shaped and hierarchical branched fluid pathways can be located between the plurality of fins and the housing and/or the plurality of fins can be in physical contact with the heat containing device.

Abstract: A semiconductor device having a lateral semiconductor element includes a semiconductor substrate, a first electrode on the substrate, a second electrode on the substrate, and an isolation structure located in the substrate to divide the substrate into a first island and a second island electrically insulated from the first island. The lateral semiconductor element includes a main cell located in the first island and a sense cell located in the second island. The main cell causes a first current to flow between the first electrode and the second electrode so that the first current flows in a lateral direction along the surface of the substrate. The first current is detected by detecting a second current flowing though the sense cell.

Abstract: A lateral insulated gate bipolar transistor includes a semiconductor substrate including a drift layer, a collector region, a channel layer, an emitter region, a gate insulating layer, a gate electrode, a collector electrode, an emitter electrode, and a barrier layer. The barrier layer is disposed along either side of the collector region and is located to a depth deeper than a bottom of the channel layer. The barrier layer has an impurity concentration that is higher than an impurity concentration of the drift layer. The barrier layer has a first end close to the collector region and a second end far from the collector region. The first end is located between the channel layer and the collector region, and the second end is located on the bottom of the channel layer.

Abstract: A semiconductor device includes: a first semiconductor region; a second semiconductor region provided on a first major surface of the first semiconductor region; a first major electrode; a third semiconductor region provided in a part of a third major surface of the second semiconductor region; a fourth semiconductor region provided in a part of a fourth major surface of the third semiconductor region; a second major electrode; a control electrode; a fifth semiconductor region; and a sixth semiconductor. The fifth semiconductor region is provided passing through the fourth semiconductor region along a direction perpendicular to the fourth major surface of the third semiconductor region. The sixth semiconductor region is provided in contact with a bottom part of the fourth semiconductor region, and has a higher impurity concentration than the third semiconductor region.

Abstract: A semiconductor device includes: an insulating substrate; a first electrode pattern and a second electrode pattern provided apart from each other on a major surface of the insulating substrate; a semiconductor element connected to the first electrode pattern; an electrode terminal connected to the second electrode pattern; and a connection wiring. The connection wiring electrically connects the first electrode pattern and the second electrode pattern with each other and has a thermal resistance larger than that of the first electrode pattern.

Abstract: A semiconductor unit of certain aspects of the invention includes electrically conductive plates in the shape of the letter L, each consisting of a horizontally disposed leg portion and a vertically disposed flat body portion that is perpendicular to a cooling plate adhered to the bottom of the semiconductor unit. A pair of the vertically disposed flat body portions sandwiches a semiconductor chip. Owing to this construction, the heat generated in the semiconductor chip can be conducted away through the both surfaces of the chip, thus improving cooling performance. Since the heat is conducted away through the leg portions of the L-shaped electrically conductive plates a projected planar area occupied by the cooling plate required for cooling the semiconductor unit is reduced. Therefore, the size of the semiconductor unit can be reduced.

Abstract: A trench insulation gate bipolar transistor (IGBT) power device with a monolithic deep body clamp diode comprising a plurality of trench gates surrounded by emitter regions of a first conductivity type near a top surface of a semiconductor substrate of the first conductivity type encompassed in base regions of a second conductivity type. A collector region of the second conductivity type is disposed on a rear side opposite from the top surface of the semiconductor substrate corresponding to and underneath the trench gates surrounded by the emitter regions encompassed in the base regions constituting a plurality of insulation gate bipolar transistors (IGBTs). A deep dopant region of the second conductivity type having P-N junction depth deeper than the base region is disposed between and extending below the trench gates in the base region of the first conductivity type.

Abstract: A semiconductor component includes a semiconductor body having a first surface and a second surface, and having an inner region and an edge region. The semiconductor component further includes a pn-junction between a first semiconductor region of a first conductivity type and a second semiconductor region of a second conductivity type, the pn-junction extending in a lateral direction of the semiconductor body in the inner region. A first trench extends from the first side in the edge region into the semiconductor body. The trench has sidewalls that are arranged opposite to another and that are beveled relative to a horizontal direction of the semiconductor body.

Abstract: An insulated gate semiconductor device includes a semiconductor substrate, a drift layer on the substrate, a base layer on the drift layer, a ring-shaped gate trench dividing the base layer into a channel layer and a floating layer, an emitter region located in the channel layer to be in contact with a side surface of the gate trench, a well region located on the periphery of a cell area of the base layer and having a depth greater than a depth of the base layer, and a ring-shaped buffer trench located adjacent to and spaced from the gate trench in a length direction of the gate trench. An edge of the well region is located in an area enclosed by the buffer trench in the length direction of the gate trench.

Abstract: A semiconductor device manufacturing apparatus is provided with a drawing pattern printing part having a print head which injects a conductive solvent, an insulative solvent and an interface treatment solution. The print head is formed in such a way that desired circuit drawing pattern can be printed on a wafer based on information on the drawing pattern from a wafer testing part, information on the wafer from a storage part and coordinate information from a chip coordinate recognition part. In a semiconductor device manufacturing method according to the present invention, a semiconductor device is manufactured by using the semiconductor device manufacturing apparatus in such a manner that desired circuits are formed through printing process. In the semiconductor device, pad electrodes and so on are formed in such a way that trimming process can be conducted by printing circuit drawing patterns.

Abstract: A semiconductor device which can make the generation of gate parasitic oscillations more difficult than a semiconductor device of the related art is provided.

Abstract: A semiconductor power module includes at least two sub modules. The sub modules include at least one respective transistor having a collector, an emitter, and a gate. The module includes a connection arrangement having a collector terminal unit for connecting the collectors of the at least two sub modules collectively to external circuit components, at least two emitter terminal units for connecting the respective emitters of the at least two sub modules individually to external circuit components, and at least two gate terminal units for connecting the respective gates of the at least two sub modules individually to external circuit components.

Abstract: A semiconductor device having the present high withstand voltage power device IGBT has at a back surface a p collector layer with boron injected in an amount of approximately 3×1013/cm2 with an energy of approximately 50 KeV to a depth of approximately 0.5 ?m, and an n+ buffer layer with phosphorus injected in an amount of approximately 3×1012/cm2 with an energy of 120 KeV to a depth of approximately 20 ?m. To control lifetime, a semiconductor substrate is exposed to protons at the back surface. Optimally, it is exposed to protons at a dose of approximately 1×1011/cm2 to a depth of approximately 32 ?m as measured from the back surface. Thus snapback phenomenon can be eliminated and an improved low saturation voltage (Vice (sat))-offset voltage (Eoff) tradeoff can be achieved.

Abstract: A semiconductor device having the present high withstand voltage power device IGBT has at a back surface a p collector layer with boron injected in an amount of approximately 3×1013/cm2 with an energy of approximately 50 KeV to a depth of approximately 0.5 ?m, and an n+ buffer layer with phosphorus injected in an amount of approximately 3×1012/cm2 with an energy of 120 KeV to a depth of approximately 20 ?m. To control lifetime, a semiconductor substrate is exposed to protons at the back surface. Optimally, it is exposed to protons at a dose of approximately 1×1011/cm2 to a depth of approximately 32 ?m as measured from the back surface. Thus snapback phenomenon can be eliminated and an improved low saturation voltage (Vce (sat))-offset voltage (Eoff) tradeoff can be achieved.

Abstract: Disclosed is a method for controlling the recombination rate in the base region of a bipolar semiconductor component, and a bipolar semiconductor component.

Abstract: An n+-emitter layer arranged under an emitter electrode is formed of convex portions arranged at predetermined intervals and a main body coupled to the convex portions. A convex portion region is in contact with the emitter electrode, and a p+-layer doped more heavily than a p-base layer is arranged at least below the emitter layer. In a power transistor of a lateral structure, a latch-up immunity of a parasitic thyristor can be improved, and a turn-off time can be reduced.