Abstract: A signal compensation circuit of a bus is disclosed in the present invention, wherein the amplitude of a surge is obtained by inputting a test pattern into the bus and comparing a reference voltage and a peak-value signal filtered out from the bus. For continual correction of the damping resistance, the test pattern can be inputted into the bus repeatedly to optimize the effect of the compensation. Then, a proper damping resistor is selected and connected to the bus in series to absorb the energy of the surge. The signal compensation circuit is embedded in the chip, such as in the south bridge.

Abstract: Disclosed is an input/output circuit having a terminating circuit that contributes to a smaller chip area. The input/output includes an output buffer having a first series circuit, which comprises a first transistor and a resistor and a second series circuit, which comprises a second transistor and a resistor, connected in parallel between a high-potential power supply and an input/output pin, as well as a third series circuit, which comprises a third transistor and a resistor and a fourth series circuit, which comprises a fourth transistor and a resistor, connected in parallel between the input/output pin and a low-potential power supply.

Abstract: A memory device includes an equalization voltage generator. The equalization voltage generator includes an oscillator and a charge pump to produce a first voltage, which may be used as an equalization voltage for pairs of complementary digit lines. The oscillator is controlled by an oscillator control signal, which is produced by a feedback and control loop of the equalization voltage generator. The feedback and control loop includes a reference generator circuit to produce a stable, internal reference signal that is clamped at a maximum reference voltage. A comparator of the feedback and control loop compares the internal reference signal with a second voltage, which is proportional to the first voltage. The comparator causes the oscillator to turn on when the second voltage is lower than the reference voltage, and causes the oscillator to turn off when the second voltage is higher than the reference voltage.

Abstract: A high-speed signal level detector employs the high gain and high bandwidth of an inverter to perform a comparison. The high-speed signal level detector is capable of achieving the desired high-speed level detection without demanding the substantial power consumption required when using either the averaging technique or a high bandwidth op-amp type comparator.

Abstract: A voltage detecting circuit that has a stable output even when a battery voltage is low includes first and second terminals connected across poles of a battery, a reference voltage generating circuit, and a comparator for comparing values of the reference voltage and voltage across the terminals. A first output circuit is connected between the first and second terminals to output a first output signal on the basis of the comparison result, a second output circuit outputs a second output signal that changes in value based on a voltage of the battery and on the basis of signals at the first and second terminals, and an output terminal outputs the first and second output signals.

Abstract: A system and method for providing a clock-independent reset signal based on supply voltage threshold levels is described. The trip points or predefined voltage levels where the power-on-reset circuit behavior reverses (which controls the reset signal) is determined by the dimensions of the transistors selected for the voltage dividers. The system and method described allows for a clock-independent stable power-up phase wile consuming a very small area of a circuit board and, in particular, on integrated circuits.

Abstract: A system of the present invention uses small swing differential source synchronous voltage and timing reference (SSVTR and /SSVTR) signals to compare single-ended signals of the same slew rate generated at the same time from the same integrated circuit for high frequency signaling. The SSVTR and /SSVTR signals toggle every time the valid signals are driven by the transmitting integrated circuit. Each signal receiver includes two comparators, one for comparing the signal against SSVTR and the other for comparing the signal against /SSVTR. A present signal binary value determines which comparator is coupled to the receiver output, optionally by using exclusive-OR logic with SSVTR and /SSVTR. The coupled comparator in the receiver detects whether change in signal binary value occurred or not until SSVTR and /SSVTR have changed their binary value. The same comparator is coupled if the signal transitions. The comparator is de-coupled if no transition occurs.

Abstract: A voltage monitoring arrangement including a number of comparison devices, which corresponds to a prescribed number of voltage ranges, compares the value of an input voltage with a reference voltage and outputs a prescribed signal if the input voltage is within one of the prescribed voltage ranges. The voltage monitoring arrangement has a latch circuit which, when a latch signal is applied, establishes which voltage range the input voltage is currently in when the latch signal is applied, resulting in the arrangement having automatic voltage range reduction. The voltage monitoring arrangement has a monitoring unit which outputs a predetermined signal if the input voltage is outside the voltage range which exists when the latch signal is applied.

Abstract: A fan regulation circuit configuration includes an input receiving an input voltage (proportional to fan current and forms a first comparison voltage), a low-pass filter (filters input voltage and a filter output voltage is tapped off as second comparison voltage), a first comparison device for commutation identification (outputs signal indicating a commutation if value of one of the comparison voltages multiplied by first factor is greater than the other comparison voltage), and a regulator (outputs a control voltage dependent upon identified commutation pulses). The circuit has self-adjusting sensitivity adaptation and a second comparison device outputting a signal if the value of one of the comparison voltages multiplied by a second factor is greater than the other comparison voltage, the second factor being less than the first factor.

Abstract: Disclosed are methods and circuits for providing a bandgap reference in an electronic circuit having a supply voltage and ground. The methods include steps for generating a bandgap reference current, mirroring the bandgap reference current, summing the mirrored currents, and modulating and outputting a bandgap reference voltage from the sum. Representative preferred embodiments are disclosed in which the methods of the invention are used in providing under-voltage protection and in providing a regulated output voltage. Circuits are disclosed for a bandgap reference voltage generator useful for providing a bandgap reference voltage in a circuit. A first current mirror for provides current from a supply voltage. A bandgap reference current circuit between the first current mirror and ground is configured for deriving a bandgap current proportional to absolute temperature. A second current mirror and control circuit are provided for summing the mirrored currents and modulating a bandgap reference voltage output.

Abstract: An input receiver with hysteresis including a differential sense amplifier, a reference circuit having a reference node providing a reference signal at a nominal threshold voltage level, and a switching stack device. The amplifier has a first input which receives an input signal, a second input coupled to the reference node, and an output which provides an output signal having first and second states indicative of the input signal. The switching stack device operates to adjust the reference signal based on the output signal between upper and lower threshold levels in an opposite direction of the input signal. The reference circuit may be a voltage divider that divides a power voltage signal to develop the reference signal. The switching stack device may include a P-channel device and an N-channel device coupled to the voltage divider to adjust the threshold voltage level of the reference signal.

Abstract: A stable voltage that is independent of supply voltage is applied to a pair of current sources. A first current source generates a first current that passes through a first resistor, setting a compare-input voltage. A source-input voltage is applied to the first current source to vary the first current and the compare-input voltage. A second current source generates a stable current that passes through a second resistor, setting a reference voltage. The compare-input voltage and the reference voltage are applied to inputs of a comparator that generates an output voltage that indicates when the source-input voltage causes the compare-input voltage to rise past the reference voltage. The first and second currents track each other over temperature and process variations and are independent of supply voltage. A more accurate comparison of the source-input voltage is thus made.

Abstract: An apparatus and method of a programmable hysteresis comparator capable of producing a digital signal in response to differential input signals is disclosed. In one embodiment, the programmable hysteresis comparator includes a hysteresis offset programmable circuit that is operable to selectively provide a hysteresis offset in response to a programmable hysteresis offset control signal. The programmable hysteresis comparator further includes a comparator circuit, which is capable of receiving differential input signals. The hysteresis comparator is operable to output a digital signal in response to differential input signals and the hysteresis offset.

Abstract: Comparator circuits, including rail-to-rail comparator circuits, can implement inverter structures such as current-starved inverters to provide hysteresis to the comparator's output. For example, a current-starved inverter can have its input driven by the comparator output and add current to the currents produced by the comparator's input stage. The inverter current can be derived from bias sources used to bias the input stage of the comparator so that the inverter current can track the input stage bias currents.

Abstract: An internal power supply voltage generation circuit includes a main amplifier that supplies a current from an external power supply node to an internal power supply line in accordance with the difference between a reference voltage from a reference voltage generation circuit and an internal power supply voltage on the internal power supply line. The current supply amount by the main amplifier is adjusted by a level adjust circuit, according to the difference between the external power supply voltage and the reference voltage. The internal power supply voltage generation circuit can suppress reduction in the internal power supply voltage in the vicinity of the lower limit area of the differential power supply voltage.

Abstract: System and method for detecting a reference signal. A preferred embodiment comprises a latch (such as the latch 320) and a filter (such as the filter 325). The latch tracks a reference signal at its input and reflects the reference signal at its output. The filter can be coupled to the output of the latch and may inject a delay to help eliminate the effects of glitches and noise. When the reference signal reaches a specified value, a control signal from the filter causes the latch to store the reference signal. A delay imparted by the filter ensures that the latch does not store the reference signal until a finite amount of time after the reference signal reaches the specified value.

Abstract: A technique for reducing input currents associated with a comparator circuit during certain events includes minimizing bias currents associated with the comparator circuit when a magnitude of an input signal at a signal input of the comparator circuit is a predetermined value from a magnitude of a reference signal applied to a reference input of the comparator circuit. The bias currents are increased when the magnitude of the input signal is within the predetermined value of the magnitude of the reference signal.

Abstract: A BiCMOS auxiliary output driver is provided to maintain output logic signal levels when integrated circuit chip power supply voltage is outside its nominal range. When the power supply voltage level is within design tolerance for a MOSFET output driver stage, the auxiliary output driver is off; when below design tolerance, the auxiliary output driver is turned on. Driver stage output pad signal level is maintained at a desired state level by the auxiliary output driver whenever the power supply slips below its design tolerance range.

Abstract: A low voltage pull-down circuit for maintaining a node at a logic LOW voltage is provided. When a logic LOW is desired, the circuit provides a low-impedance path from the node to ground. The node may be easily pulled-up to a logic HIGH voltage, for example, by simply removing the low-impedance path and allowing a voltage source to reach the node through a resistor or transistor.

Abstract: The disclosure relates to detectors of the level of supply voltage in an integrated circuit. The disclosed detector is designed to detect the crossing of low levels of supply voltage. It comprises a first arm to define a first reference voltage and a second arm to define a second reference voltage, these two reference voltages varying differently as a function of the supply voltage and their curves of variation intersecting for a value of the supply voltage located close to a desired threshold. A comparator receives the two reference voltages. The first arm has a resistive divider bridge, an intermediate connector of which constitutes the first reference voltage. The second arm comprises a resistor series-connected with a native P type MOS transistor, the point of junction of this resistor and this transistor constituting the second reference voltage. A non-linear element may be parallel-connected to the resistor which constitutes the first reference voltage.

Abstract: A stable voltage that is independent of supply voltage is applied to a pair of current sources. A first current source generates a first current that passes through a first resistor, setting a compare-in-put voltage. A source-input voltage is applied to the first current source to vary the first current and the compare-input voltage. A second current source generates a stable current that passes through a second resistor, setting a reference voltage. The compare-input voltage and the reference voltage are applied to inputs of a comparator that generates an output voltage that indicates when the source-input voltage causes the compare-input voltage to rise past the reference voltage. The first and second currents track each other over temperature and process variations and are independent of supply voltage. A more accurate comparison of the source-input voltage is thus made.

Abstract: A supply noise compensation circuit. The supply noise compensation circuit senses the onset of dI/dt noise events on a supply line and selectively gates off/forces on a chip clock to chip circuits.

Abstract: Level shifting and amplified level shifting circuit topologies are provided that include two or more level shifting or amplified level shifting circuits. The level shifting circuits receive a variable and fixed input and generate a variable and fixed output that are level shifted with respect to the input signals. The amplified level shifting circuits receive a variable and fixed input and generate a variable and fixed output that are level shifted and amplified with respect to the input signals. These circuits may be utilized to form a detection circuit that detects a difference in the output signals.

Abstract: Level shifting and amplified level shifting circuit topologies are provided that include two or more level shifting or amplified level shifting circuits. The level shifting circuits receive a variable and fixed input and generate a variable and fixed output that are level shifted with respect to the input signals. The amplified level shifting circuits receive a variable and fixed input and generate a variable and fixed output that are level shifted and amplified with respect to the input signals. These circuits may be utilized to form a detection circuit that detects a difference in the output signals.

Abstract: A method and apparatus for generating a reference voltage potential, also known as an input switching reference, using differential clock signals or other differential signals that ideally have a 180 degree phase shift is provided. The differential signals are generated by a transmitting circuit. The reference voltage potential is dependent on the differential signals. The voltage potentials of the differential signals are averaged and low-pass filtered. Comparators in a receiving circuit compare an input signal's voltage potential to the reference voltage potential to determine if the transmitted input signal is a binary one or binary zero.

Abstract: A hysteresis comparing device with constant hysteresis width and the method thereof, which can respectively receive a first signal and a second signal and can output a digital signal. The hysteresis comparing device includes a threshold voltage generator, a multiplexer, and a next stage comparator. The threshold voltage generator is used to receive the first signal and output an upper threshold voltage and a lower threshold voltage. The multiplexer is used to receive the upper threshold voltage and the lower threshold voltage, and output a multiplexing signal according to the digital signal. The multiplexing signal is either the upper threshold voltage or the lower threshold voltage. The next stage comparator has one terminal used to receive the multiplexing signal, and another terminal used to receive the second signal. The next stage comparator outputs the digital signal. The hysteresis comparing device with constant hysteresis width can suppress the effect from the glitch.

Abstract: An area-efficient fully integrated BiCMOS analog time delay circuit with low-power supply requirements provides delays as long as two milliseconds. An ultralow PTAT current source comprises medium-value resistors to discharge an on-chip capacitor from a fixed zero-temperature coefficient voltage. The comparator monitors the capacitor voltage and changes stage from low to high when the capacitor is discharged below a reference voltage having a defined negative temperature coefficient. The temperature coefficient of the reference voltage generator and the PTAT current source are such that the timeout period is independent of temperature in the first-order. The generated timeout delay is independent of the supply voltage and can be used with a supply voltage as low as two volts.

Abstract: A rectified analog input signal is compared with a threshold voltage by a voltage comparator, and counting direction of an up/down counter is switched based on the comparison result, and a latch circuit retains an output of the up/down counter, and then an analog-digital converting circuit converts an output of the latch signal into a direct-current voltage. In addition, two input terminals, to which a clock for up-count operation and a clock for down-count operation are independently provided, is provided in the up/down counter, and a timing pulse generating circuit for determining reset timing of the up/down counting circuit and latch timing of the latch circuit is provided.

Abstract: A method for receiving data by an integrated circuitry chip includes receiving data signals and a first clock signal sent by a sending chip. The data signals are received by data receivers and the clock signal is received by at least one clock receiver of the receiving chip. A reference voltage is derived by reference voltage circuitry for the receiving chip responsive to the first clock signal. Logical states of the received data signals are detected. The detecting includes the data receivers comparing voltage levels of the received data signals to the derived reference voltage.

Abstract: A differential input receiver with hysteresis on both sides of the reference voltage may include a two-input, one-output differential amplifier including two input transistors having a common terminal connected together. The control terminal of each transistor may be connected to one of the inputs of the differential amplifier. The output of the differential amplifier may be connected to a set of cascaded digital inverters/buffers, and an output of each digital buffer may be connected to the control terminal of a feedback transistor. The feedback transistor may be connected in parallel across each of the input transistors so that when one input voltage increases above or decreases below the input voltage at the second input by a predetermined threshold value, the feedback transistors operate to provide positive feedback to facilitate a rapid switching action at the output.

Abstract: In accordance with one embodiment of the present invention, a signal detect circuit may analyze an input signal before passing it on to a receiver. The analysis may be done outside of the data path to avoid affecting the data path speed or adding distortion or jitter. The positive and negative thresholds of the data may be checked to see if the numbers of positive and negative crossings are comparable. Random and bursty noise can be detected since such noise normally does not have comparable positive and negative crossings.

Abstract: A floating gate circuit in a read mode that includes at least one floating gate and an analog feedback circuit is disclosed. The feedback circuit causes the floating gate circuit to reach a steady state condition in the read mode such that a reference voltage is generated that is a predetermined function of an input set voltage used to set the at least one floating gate. In a preferred embodiment, the reference voltage generated is approximately equal to the input set voltage.

Abstract: A method and apparatus for setting a floating gate in a floating gate circuit using dual conduction of Fowler-Nordheim tunnel devices is disclosed. In one embodiment, the present invention comprises a floating gate circuit having a single floating gate. During a set mode, the charge level on the floating gate is modified until it is set to a predetermined charge level that is a function of an input set voltage. In another embodiment, the floating gate circuit comprises two floating gates. During a set mode the charge level on each of the floating gates is modified until the difference in charge level between the two floating gates is a predetermined function of an input set voltage that is capacitively coupled to one of the floating gates during the set mode.

Abstract: A receiving circuit including an amplifier for generating a receiving voltage signal, a comparator for generating a binary signal from the receiving voltage signal, and a logic maintaining circuit for receiving the binary signal and maintaining the binary signal at a shifted level for a predetermined period after the level of the binary signal is shifted. The logic maintaining circuit prevents noise pulses from appearing in a receiving signal.

Abstract: A low-current input buffer is disclosed. The buffer uses self-biased N and P channel differential pairs with their outputs tied together. The self-biasing assists in reducing current consumption. The combination of N and P-channel differential pairs results in symmetry across a wide range of reference and supply voltages.

Abstract: A chopper comparator has inverters in input and output stages including NMOS transistors to control connection and disconnection of an inverter circuit of each inverter. During a non-operation period of the chopper comparator, parts of the inverters are disconnected form the ground based on a signal supplied to gates of the NMOS transistors.

Abstract: There is described an integrating circuit (20) for use with a photodetector (10) and an optical sensor (1) including such an integrating circuit. The integrating circuit comprises an operational amplifier (30) having a non-inverting input (32) connected to a non-zero bias voltage (VPD-BIAS), an inverting input (31) coupled to the photodetector (10), and at least one output (33). This integrating circuit further includes an integrating voltage storage device (25) having a first terminal coupled to the operational amplifier output and a second terminal coupled to the operational amplifier inverting input, and switching circuitry for controlling timing of the integrating circuit and switching the integrating circuit between a reset phase and an integration phase.

Abstract: A voltage detector is disclosed, which has a resistor pair, a reference resistor, at least one transistor pair and a comparator. One resistor of the resistor pair is coupled between an input voltage and one of the transistor pair, and the other resistor is coupled between the input voltage and the reference resistor. The other transistor is coupled between the reference resistor and a ground voltage. Thus, a reference detection voltage and a voltage to be detected are generated. The comparator compares the reference detection voltage and the voltage to be detected to obtain a resulting output, wherein temperature effect can be eliminated by adjusting an area ratio of the transistors and an area ratio of the reference resistor to the resistor pair.

Abstract: The Floating Diffusion charge detection system has incorporated a signal feedback directly into the charge-detection node. The feedback is coupled to the node from the output of the standard buffer amplifier A1 through a feedback amplifier A3, switching transistors S2 and S3, and capacitors Cf and Ch. The feedback significantly reduces kTC noise, has good linearity, and improves DR.

Abstract: A semiconductor device is constructed by at least one reference voltage generating circuit for generating a reference voltage, a plurality of input voltage pads for receiving input voltages, a control signal pad for receiving a control signal, and a plurality of input buffers. Each of the input buffers amplifies a difference between one of the input voltages and the reference voltage to generate an output voltage, and includes a switch connected between the reference voltage generating circuit and one of the input voltage pads and controlled by the control signal.

Abstract: A method for sensing the voltage on a floating gate in a floating gate circuit during a set mode is disclosed.

Abstract: A system of the present invention uses small swing differential source synchronous voltage and timing reference (SSVTR and/SSVTR) signals to compare single-ended signals of the same slew rate generated at the same time from the same integrated circuit for high frequency signaling. The SSVTR and/SSVTR signals toggle every time the valid signals are driven by the transmitting integrated circuit. Each signal receiver includes two comparators, one for comparing the signal against SSVTR and the other for comparing the signal against/SSVTR. A present signal binary value determines which comparator is coupled to the receiver output, optionally by using exclusive-OR logic with SSVTR and/SSVTR. The coupled comparator in the receiver detects whether change in signal binary value occurred or not until SSVTR and/SSVTR have changed their binary value. The same comparator is coupled if the signal transitions. The comparator is de-coupled if no transition occurs.

Abstract: A current sense apparatus and method comprises a common drain DMOSFET and a MOSFET connected in series between a high voltage and a low voltage to serve as an output stage. The DMOSFET produces a phase output current, a mirror current mirrored from the phase output current, and a sense voltage. A servo amplifier is connected with the mirror current and sense voltage to produce a current sense signal. Due to the mirror current from the DMOSFET proportional to the phase output current, the current sense apparatus senses the phase output current in a temperature independent manner.

Abstract: A fan regulation circuit configuration includes an input receiving an input voltage (proportional to fan current and forms a first comparison voltage), a low-pass filter (filters input voltage and a filter output voltage is tapped off as second comparison voltage), a first comparison device for commutation identification (outputs signal indicating a commutation if value of one of the comparison voltages multiplied by first factor is greater than the other comparison voltage), and a regulator (outputs a control voltage dependent upon identified commutation pulses). The circuit has self-adjusting sensitivity adaptation and a second comparison device outputting a signal if the value of one of the comparison voltages multiplied by a second factor is greater than the other comparison voltage, the second factor being less than the first factor.

Abstract: An input circuit includes a gate circuit receiving an output power supply voltage that determines the logic level of an input signal or a comparison circuit receiving an input signal and a reference voltage depending on the output power supply voltage supplied from a pad different from a power supply pad for an output circuit.

Abstract: A buffer has an amplifier that receives an external signal, a reference voltage, and outputs an amplified signal. The amplified signal is responsive to the difference between the external signal and the reference voltage. An inverter receives the amplified signal and generates an inverted signal. A voltage supply circuit is configured to provide an adjusted power supply voltage to the inverter responsive to the reference voltage. A ground voltage supply circuit is configured to provide an adjusted ground voltage to the inverter responsive to the reference voltage.

Abstract: A comparator is provided with a pair of transistors which are continuously in ON state, in which a switch unit constructed of a diode pair, for switching a current path in response to a high/low relationship between a voltage level of an input signal and a voltage level of a reference voltage, and a unit for converting a current into a voltage level are provided between emitter terminals of the transistor pair.

Abstract: The present invention relates to a method and a device for monitoring at least one output stage (1) which is actuated by a microcontroller (&mgr;C) using an input signal (2) having any pulse duty factor. The output signal (3) from the output stage (1) is averaged by an electrical circuit (4) and compared to a setpoint value (5) which is calculated from the input signal (2) of the output stage. An error in the output stage (1) is diagnosed when the averaged value (6) deviates from the calculated setpoint value (5).

Abstract: An input buffer circuit simultaneously supports a low voltage interface and a general low voltage transistor-transistor logic (LVTTL) interface and operates at high speed. In the input buffer circuit, a self bias voltage generated by a self biased differential amplification circuit is used not only for tracking a common mode input voltage in the differential amplification circuit but also for controlling the current of a current source and/or sink that controls the current used in the differential amplification circuit. Accordingly, the self bias voltage remains at a substantially uniform level. Therefore, the entire transconductance gain gm of the differential amplification circuit is substantially uniform regardless of the change in a reference voltage input to the differential amplification circuit. As a result, a low voltage interface characteristic is improved.

Abstract: The differential amplifier of a comparator circuit includes first and second n-type MOSFETs for receiving an input signal, first and second p-type MOSFETs of a current mirror circuit, and a third n-type MOSFET of a current source circuit. The output stage includes a third p-type MOSFET for transmitting a signal, and a fourth n-type MOSFET of the current source circuit. The differential amplifier further includes fifth and sixth n-type MOSFETs respectively series-connected to the first and second n-type MOSFETs. The output stage further includes a seventh n-type MOSFET series-connected to the fourth n-type MOSFET. The gates of the fifth, sixth, and seventh n-type MOSFETs are connected to voltage bias circuits. The fifth, sixth, and seventh n-type MOSFETs suppress variations in voltage at an output node caused by poor saturation characteristics of the first, second, and fourth main n-type MOSFETs.