Abstract: A low voltage pull-down circuit for maintaining a node at a logic LOW voltage is provided. When a logic LOW is desired, the circuit provides a low-impedance path from the node to ground. The node may be pulled-up to a logic HIGH voltage, for example, by removing the low-impedance path and allowing a voltage source to reach the node through a resistor or transistor. A low voltage pull-down circuit may be provided in a power supervision circuit for systems that operate with, for example, low power conditions. The open-drain node is utilized as a power-on-reset node that provides a LOW logic signal to a system when the power being supplied to the system is below a predetermined voltage threshold.

Abstract: A circuit and a method are provided to produce a novel comparator with Schmitt trigger hysteresis character. The circuit includes a current source which controls the magnitude of current flow through this comparator circuit. It has a first logic device which is turned ON by a reference voltage, and a second logic device is turned ON by a comparator input voltage. A first feedback device is turned ON by a negative comparator output. A first parallel resistor is connected in parallel to the first feedback device. A second feedback device is turned ON by a positive comparator output. A second parallel resistor is connected in parallel to the second feedback device. The first and second parallel resistors are used to provide the differential comparator with switching voltage offsets which result in the Schmitt trigger hysteresis character.

Abstract: A power-off detection device is formed without use of a photo coupler, which is expensive and occupies a relatively large area. The power-off detection device rectifies AC power, provided as external input power from a power supply device, into DC power, detects the power-off of the external input power from the power supply device as provided to an electronic appliance, provides a power-off detection signal to central control means of the electronic appliance, and enables the central control means to prepare for the power-off, thereby reducing manufacturing cost of the power supply device, and achieving miniaturization thereof.

Abstract: A supply voltage sensing circuit comprises an internal power supply circuit, which provides a constant output voltage regardless of the supply voltage. A delay circuit generates a delayed signal by delaying a variation in the output voltage. A divider circuit generates a divided voltage by dividing the supply voltage at a certain division ratio. A p-type MOS transistor has a source given the delayed signal and a gate given the divided voltage and turns on when the supply voltage lowers below a certain value. An output circuit provides an output voltage based on a drain voltage on the p-type MOS transistor.

Abstract: An improved comparator circuit and associated methods are disclosed. In one embodiment, the comparator circuit comprises two voltage-to-time converter circuits, one for each input voltage to be compared, and an arbiter circuit for receiving the time-converted output of each converter. Each converter assesses the magnitude of its input voltage, and outputs a signal that is asserted at a time in inverse proportion to the magnitude of the input voltage. In one embodiment, producing the output signal at the asserted time comprises using the input voltage to gate a transistor whose discharge rate dictates the timing of the output signal. The two output signals arrive at an arbiter circuit whose function is to determine which output arrived at the arbiter first, as is indicative of the higher magnitude input voltage, and to set the output of the comparator accordingly.

Abstract: An input/output buffer that protects a circuit from voltage signals provided from an external device. The input/output buffer includes a reference power generation circuit connected to a high voltage power supply and a low voltage power supply to convert the voltage of an external voltage signal and generate reference power. The reference power generation circuit has a protection circuit including a plurality of MOS transistors for decreasing the voltage of the external voltage signal to a predetermined voltage when the input/output buffer is not supplied with the voltage of the high voltage power supply. Each of the MOS transistors has a back gate connected to a predetermined node at which the voltage is less than the voltage of the high voltage power supply and greater than the voltage of the low voltage power supply.

Abstract: A circuit for providing an output current is provided. The circuit includes a differential amplifier, a transistor having a gate that is coupled to the output of the differential amplifier, a comparator, and a sense resistor that is coupled between the drain of the transistor and the input pin. One input of the differential amplifier is connected to the input pin and the other input is connected to a reference voltage. The inputs of the comparator are coupled across the sense resistor. If an external resistor is coupled to the input pin, the comparator trips. If the comparator is tripped, the current from the external resistor is mirrored to provide the output current. If the comparator is not tripped, the output current is provided from an on-chip current source.

Abstract: A bulk voltage (VBB) level sensor for a semiconductor memory apparatus is disclosed. The VBB level detector includes a reference voltage generator for generating a first reference voltage of which level varies with temperature, a reference voltage comparator for receiving a second reference voltage and the first reference voltage to generate a third reference voltage, a bias generator for receiving the third reference voltage to generate a specific bias level, and a VBB sensor for receiving the bias level to detect VBB level.

Abstract: A voltage (UE1, UE2), other than a supply voltage (UV1, UV2), is monitored and controlled to avoid damage to circuit components by maintaining a required voltage level. Dissipation power losses are reduced by switching off a monitoring circuit when monitoring is not required. For this purpose a stepped down voltage is derived from the voltage to be monitored at a tap (N1) of a voltage divider connected between ground potential and the voltage to be monitored. The derived voltage is then evaluated, for example by comparing with a reference voltage. A controllable switch is connected in series with two voltage divider elements. The switch is controlled to open for switching off the voltage divider when monitoring is not needed. The switch is closed to activate the voltage divider when monitoring is needed.

Abstract: A current mode comparator for a semiconductor device is disclosed. The current mode comparator may include a logic circuit coupled to a voltage sensing node, a first cascode coupled to the voltage sensing node and a first power node, and a second cascode coupled to the voltage sensing node and a second power node. The logic circuit may convert a voltage of the voltage sensing node to an output signal.

Abstract: A high-speed, low-power input buffer for an integrated circuit device in which the input voltage (VIN) is coupled to both a pull-up and a pull-down transistor. In accordance with a specific embodiment, the input buffer utilizes a reference voltage input (VREF) during a calibration phase of operation but not when in an active operational mode. A maximum level of through current is supplied when VIN=VREF with lower levels of through current at all other VIN voltages. In an integrated circuit device incorporating an input buffer as disclosed, two (or more) input buffers may be utilized per device input pin.

Abstract: A low voltage detect and supply circuit (200) can include a detect circuit (202), a bias circuit (204) and a power supply transistor structure (P1). In operation, when a device power supply (Vext) remains above a predetermined limit, a detect circuit (202) can provide low impedance, thus maintaining transistor structure P1 in a high impedance state. When a device power supply (Vext) falls below a predetermined limit, a detect circuit can provide a high impedance. Embodiments of the circuit (200) do not include a differential voltage type comparator, and can be biased to draw relatively small amounts of current.

Abstract: An analog filter circuit in which filter characteristic deviation can be adjusted with simple circuitry and its adjustment method can be provided. The analog filter circuit includes a low pass filter and a high pass filter and output signals of both filters are input to a comparison and adjustment section from which an adjustment signal is fed back to the low pass and high pass filters and also input to a predetermined-band pass filter having predetermined correlation to the low pass and high pass filters. The low pass and high pass filters are tuned so that the frequency-gain characteristic line in an attenuation band of the low pass filter linearly falls, while that line of the high pass filter linearly rises, both the lines crossing at a reference frequency.

Abstract: An integrated circuit die includes a microprocessor and a control circuit to control elements of a voltage regulator to supply power to the microprocessor.

Abstract: A device for detecting an interface voltage of a Universal Serial Bus (USB) interface. The device includes first and second voltage level indicators, and first and second control circuits. The first control circuit receives the interface voltage to generate a first control signal and drive the first voltage level indicator when the interface voltage level is less than a first voltage level. The second control circuit receives the interface voltage to generate a second control signal and drive the second voltage level indicator when the interface voltage level exceeds a second voltage level.

Abstract: Integration and terminal arrangement of serially-connected parallel monitor circuits, capable of monitoring the terminal voltages of serially-connected capacitors, are disclosed. A semiconductor device has a predetermined number of parallel monitor circuits, corresponding to a number of capacitors existing in the system. The semiconductor device includes a number of capacitor terminals and transistor terminals distributed on a capacitor side surface or a capacitor side, and a number of connector terminals distributed on the side surface opposite to the capacitor side surface or the side opposite to the capacitor side.

Abstract: A voltage detection circuit, comprises a constant-current circuit, a current mirror circuit operated by the constant-current circuit, at least one diode-connected first transistor disposed between an output of the current mirror circuit and a detected voltage, and an output circuit outputting one logic voltage in response to a turn-on of the first transistor when the detected voltage is a predetermined voltage or higher, and outputting the other logic voltage in response to a turn-off of the first transistor when the detected voltage is lower than the predetermined voltage.

Abstract: Disclosed is a Boundary-Scan test receiver for capturing signals during board interconnect testing. The test receiver has a comparator with a first input to receive signals during board interconnect testing, and a second input to receive a reference voltage. A programmable hysteresis circuit is coupled to at least one of the comparator's inputs. The programmable hysteresis circuit may be configured to program a hysteresis voltage and/or a hysteresis delay, both of which help prevent the comparator from integrating signal noise.

Abstract: A comparator includes a sampling capacitor, a first switching unit which is connected to an input end of the sampling capacitor and which applies an input signal to the input end of the sampling capacitor, a second switching unit which is connected to the input end of the sampling capacitor and which applies a reference signal to the input end of the sampling capacitor, an output transistor connected to an output end of the sampling capacitor in a source follower connection manner or an emitter follower connection manner, and a third switching unit which is connected to an output end of the sampling capacitor and which maintains maintaining a voltage at the output end of the sampling capacitor to be constant. The input signal is compared with the reference signal.

Abstract: Aspects of a method and system for a linear regulator with high bandwidth, PSRR, and a wide range of output current are provided. A method for isolating voltages in a circuit may comprise applying a reference voltage to an isolation resistor based on a supply voltage. An internal voltage at a reference point may be determined based on the applied reference voltage, and a maximum and/or minimum voltage may be determined based on the internal voltage. A plurality of output transistor devices may be controlled based on either the maximum voltage or minimum voltage. The reference voltage may be modified based on controlling the plurality of output transistor devices. By turning ON and OFF the output transistor devices, a much wider operating range is facilitated.

Abstract: A circuit and method are provided for performing built-in test of output signal magnitudes of integrated differential signal generator circuitry. In accordance with one embodiment, first upper and lower reference voltages and second upper and lower reference voltages are received via a plurality of reference electrodes, wherein: a difference between the first and upper and lower reference voltages comprises a first difference magnitude; a difference between the second upper and lower reference voltages comprises a second difference magnitude; and the first difference magnitude is greater than the second difference magnitude. Test signal generator circuitry provides a plurality of binary signals with respective successions of opposing signal states.

Abstract: Some embodiments of the invention include an input buffer having multiple differential amplifiers for receiving input signals to generate an output signal. The input buffer operates in a relatively low supply voltage and a relatively wide range of signal levels of the input signals while improving the symmetry between rising and falling signal transitions of the output signal. Other embodiments are described and claimed.

Abstract: A comparator uses two resonant tunneling diodes (RTDs) in series with resistors of the latch element of the comparator. By inserting two RTD diodes in series with resistors, the negative resistance of the first and the second RTD diodes reduces the effective RC time constants of the resistors and latch, leading to a faster regeneration during a latching mode of the comparator than achieved with alternative designs.

Abstract: A rectifier circuit is provided, which does not need a feedback function and prevents deterioration of a frequency characteristic, even if the rectifier circuit is configured with thin film transistors (TFTs). For example, the rectifier circuit is configured with an amplifier circuit, which compares an input signal with a voltage of a power source; a waveform shaping circuit for shaping a waveform of an output signal of the amplifier circuit; a resistor, which is connected to both an input terminal and output terminal; and a switching circuit, which is connected to both the output terminal and the power source, and is controlled by an output signal of the waveform shaping circuit. Then, either the input signal or the voltage of the power source is outputted in accordance with an operation of the switching circuit, so that the input signal is ideally rectified.

Abstract: A DC level wandering cancellation circuit is provided. The DC level wandering cancellation circuit comprises a low pass filter, for receiving an input voltage; a high pass filter coupled to the low pass filter; an amplifier coupled to the high pass filter for receiving a reference voltage and an output signal of the high pass filter; a comparator coupled to the amplifier for receiving an output signal of the amplifier to compare the reference voltage with the output signal of the amplifier; a resistor coupled between outputs of the high pass filter and the amplifier; a control logic coupled to the comparator for receiving a compared result from the comparator; and a switching means coupled between the high pass filter and the output of the amplifier. The switching means is turned on for a predetermined interval by the control logic according to the compared result.

Abstract: A word recognizer for providing a channel-to-channel compare for an input digital signal divides channels of the input digital signal into equal-width input signal channel paths. One input signal channel path serves as a reference value for comparison with the other input signal channel path to produce the channel-to-channel compare.

Abstract: A system of the present invention uses small swing differential source synchronous voltage and timing reference (SSVTR and /SSVTR) signals to compare single-ended signals of the same slew rate generated at the same time from the same integrated circuit for high frequency signaling. The SSVTR and /SSVTR signals toggle every time the valid signals are driven by the transmitting integrated circuit. Each signal receiver includes two comparators, one for comparing the signal against SSVTR and the other for comparing the signal against /SSVTR. A present signal binary value determines which comparator is coupled to the receiver output, optionally by using exclusive-OR logic with SSVTR and /SSVTR. The coupled comparator in the receiver detects whether change in signal binary value occurred or not until SSVTR and /SSVTR have changed their binary value. The same comparator is coupled if the signal transitions. The comparator is de-coupled if no transition occurs.

Abstract: Provided is an amplifier circuit having a constant output swing range and a stable delay time, where the amplifier circuit includes a first bias unit, a second bias unit, a comparison unit, and an amplifier unit, and the first bias unit responds to an internal reference signal with a predetermined voltage level and maintains constant the amount of a first current, and the second bias unit receives an external reference signal, responds to a control voltage, and controls the amount of a second current to be the same as the amount of the first current, and the comparison unit compares a voltage level of a first node with a voltage level of a second node, and controls a voltage level of the control voltage according to the comparison result, and the amplifier unit compares a voltage level of an external input signal with a voltage level of the external reference signal, amplifies and outputs a voltage difference between the two compared signals, responds to the control voltage, and controls the amount of a third

Abstract: A control output signal is supplied to a gate electrode of an insulated gate transistor from a control signal output terminal of a control device, however, with regard to the insulated gate transistor, a control output signal is also influenced when that transistor is short-circuited, and a signal waveform different from that in a normal operating state occurs. The short-circuit is detected by monitoring the control output signal of the insulated gate transistor, and in case of the short-circuit, the short-circuit protection of the insulated gate transistor is performed by forcing the control device to stop that control output signal.

Abstract: An output signal of an error amplifier 5, which has a reference terminal to which a voltage having no temperature characteristics fluctuation is applied and which has a detection terminal to which a voltage detecting terminal VO2 is connected, is transmitted to the control terminal of a switching element 6. Voltage fluctuation at the voltage detecting terminal VO2 is output as a current signal by a V-1 conversion circuit constituted by a current mirror circuit having a constant current source 4, the switching element 6, and switching elements 7 and 8 to a detected signal output terminal PC via the error amplifier 5. The signal is transmitted to the outside by a optical coupler 14 to control a voltage at an output voltage terminal VOUT.

Abstract: The conventional chopper comparator circuit has had high power consumption because the gain thereof used to be set high, so that there has been the need for cutting down on power consumption.

Abstract: The present invention is related to a device comprising a capacitive feedback transimpedance operational amplifier, that comprises a main operational amplifier (with a first input, a second input and an output) and an integrating capacitor, connected between the second input and the output, and a first switch connected in parallel to the integrating capacitor. The device further comprises an auto-zero operational amplifier having a third input and a fourth input, whereby to the third input and the first input signals at virtual ground potential are applied. The fourth input is connected to the output by a circuit comprising two offset error capacitors, a second switch and a third switch.

Abstract: A voltage detection circuit of the invention is composed of the minimum needed number of circuit elements and that permits the temperature characteristic of the reference level for voltage detection to be set arbitrarily. The voltage detection circuit has a first transistor and a second transistor that have the emitters thereof connected together to form a differential pair, a voltage division circuit that divides the input voltage into a first division voltage and a second division voltage, that is connected directly to the base of the first transistor to apply the first division voltage thereto, and that is connected directly to the base of the second transistor to apply the second division voltage thereto, and a resistor that has one end thereof connected to the base of the second transistor and that has the other end thereof connected to the emitter of the second transistor. Whether the input voltage is equal to a predetermined level or not is checked based on the output from the differential pair.

Abstract: A programmable, equalizing buffer is provided having feedback transistors used to vary the transfer function of the equalizing buffer, such that a low pass response of a transmission channel is substantially equalized. A zero in the buffer's transfer function is established by a conductive state of transistors caused by signal feedback. Multiple transistors establish increased flexibility for establishing the location of the zero, while a cascade of buffer stages provides a second order transfer function effective to cancel second order channel effects.

Abstract: Current through a wire is sensed with a shunt resistor and a sense resistor in a current divider circuit. The values of the shunt resistor and sense resistor are related to provide a specified gain ratio to increase a dynamic range of current measurement. The sense resistor is a trimmable resistor, the configuration of which can be discerned from a look-up table based on a level of precision needed for current measurement. The two resistors can also be related by thermal coefficients to improve linearity of current measurements.

Abstract: A system of the present invention uses small swing differential source synchronous voltage and timing reference (SSVTR and /SSVTR) signals to compare single-ended signals of the same slew rate generated at the same time from the same integrated circuit for high frequency signaling. The SSVTR and /SSVTR signals toggle every time the valid signals are driven by the transmitting integrated circuit. Each signal receiver includes two comparators, one for comparing the signal against SSVTR and the other for comparing the signal against /SSVTR. A present signal binary value determines which comparator is coupled to the receiver output, optionally by using exclusive-OR logic with SSVTR and /SSVTR. The coupled comparator in the receiver detects whether change in signal binary value occurred or not until SSVTR and /SSVTR have changed their binary value. The same comparator is coupled if the signal transitions. The comparator is de-coupled if no transition occurs.

Abstract: A multi-channel integrated circuit is provided in which each channel has an analog section and a digital section. Each channel of the readout chip employs low noise charge sensitive amplifier at its input followed by other circuitry such as shaper, pole-zero, peak hold, different comparators, buffers and digital control and readout. Each channel produces a self-trigger and a fast timing output. Channel-to-channel time differences are also recorded. Integrated circuit also provides a large dynamic range to facilitate large range of applications. The trigger threshold can be adjusted to provide energy discrimination. The chip has different, externally selectable, operational modes including a sparse readout mode in which only the channels which have received signals greater than a preselected threshold value are read out. The sparse readout mode results in increased data throughput, thus providing fast data acquisition capabilities.

Abstract: A voltage comparator with comparing means that are energized upon the occurrence of a clock-edge and that are de-energized when the comparison operation is completed. The comparing means are preceded by a voltage divider (D) for dividing the voltage to be compared and a switch (S8) in series with the voltage divider for preventing current flow through the voltage divider when the comparing means are de-energized.

Abstract: A capacitor circuit having improved reliability includes at least first and second capacitors, a first terminal of the first capacitor connecting to a first source providing a first voltage, a first terminal of the second capacitor connecting to a second source providing a second voltage, the first voltage being greater than the second voltage. The capacitor further includes a voltage comparator having a first input for receiving a voltage representative of the first voltage, a second input for receiving a third voltage provided by a third source, and an output for generating a control signal. The control signal is a function of a difference between the voltage representative of the first voltage and the third voltage. A switch is connected to second terminals of the first and second capacitors.

Abstract: A reference voltage and an input signal voltage are applied to gates of FETs each equipped with a LOCOS-drain structure, respectively, and currents according to the voltages are made to flow from a power supply voltage Vbat to drain sides through resistors and sources, respectively. The currents are made to flow in FETs to be converted to voltages. Then, both voltages are compared in a comparator. When a potential of a reference voltage input terminal in the comparator that operates with power provided by a power supply Vcc tends to rise above a predetermined level, a FET is turned on and clamps the voltage so as to suppress its potential rise.

Abstract: A comparator circuit includes a reference generator connecting to a first source providing a first voltage. The reference generator is operative to generate a reference signal and includes a control circuit selectively operable in at least a first mode or a second mode in response to a first control signal, wherein in the first mode the reference signal is not generated, and in the second mode the reference generator is operative to generate the reference signal. The comparator circuit further includes a comparator connecting to a second source providing a second voltage, the second voltage being less than the first voltage. The comparator is operative to receive the reference signal and an input signal, and to generate an output signal which is a function of a comparison between the input signal and the reference signal.

Abstract: A DC level wandering cancellation circuit is provided. The DC level wandering cancellation circuit comprises a low pass filter, for receiving an input voltage; a high pass filter coupled to the low pass filter; an amplifier coupled to the high pass filter for receiving a reference voltage and an output signal of the high pass filter; a comparator coupled to the amplifier for receiving an output signal of the amplifier to compare the reference voltage with the output signal of the amplifier; a resistor coupled between outputs of the high pass filter and the amplifier; a control logic coupled to the comparator for receiving a compared result from the comparator; and a switching means coupled between the high pass filter and the output of the amplifier. The switching means is turned on for a predetermined interval by the control logic according to the compared result.

Abstract: The present invention provides one hysteresis circuit device. The hysteresis circuit device includes an input voltage level generator, a switch, and a comparator. The input voltage level generator is used to receive an input signal and output a high input voltage and a low threshold voltage. The switch is used to receive the high input voltage and the low threshold voltage, and output a switch output signal according to a digital signal. The comparator has one terminal used to receive the switch output signal, and another terminal used to receive a reference signal. Then, the comparator outputs the digital signal. The hysteresis circuit device can change their voltage levels by an external circuit; therefore, the noise resulting from the input signal can be avoided and the problem of false detection of the comparator can be solved.

Abstract: A voltage detection circuit for accurately detecting a voltage while suppressing the voltage fluctuation due to the off-leak current of a transistor. The voltage detection circuit includes first and second capacitors, first and second transistors, a comparator, and a control circuit. The capacitors are connected in series to generate a division voltage corresponding to a high voltage by the capacitors. The potential at a node between the first capacitor and the second capacitor is reset to ground potential when the transistors are activated. When the potential at the node reaches a predetermined potential, the first transistor is inactivated, and then the second transistor is inactivated.

Abstract: A driving circuit includes: a first amplifier circuit having a first operating range, for charging and driving an output terminal and a second amplifier circuit having a second operating range, for discharging and driving the output terminal, and an input control circuit for supplying one of a voltage at an upper limit side (V1) of a range common to the first and second operating ranges, a voltage at a lower limit side (V2) of the range, and a target voltage to an input terminal of the first or second amplifier circuit. A driving period for driving the output terminal to the target voltage includes a first period during which the input control circuit supplies the voltage (V1) or the voltage (V2) to the input terminals and a second period (T2) for supplying the target voltage to the input terminals.

Abstract: A method for determining an operating voltage of floating point error detection is implemented by a central processing unit (CPU) and a south bridge chipset. The CPU has a first output port connected to a test port of the south bridge. The test port is used to determine an operating voltage of the CPU. If the operating voltage of the CPU is greater than a predetermined value, the first output port is floating. If the operating voltage of the CPU is smaller than the predetermined value, the first output port is grounded. The method includes using a power supply and a resistor to provide a bias voltage and for measuring a voltage of the test port to determine the operating voltage of the CPU.

Abstract: A method and circuit for synchronizing an input clock signal with a plurality of internal clock signals in a multiple phase Pulse Width Modulation (PWM) switching power supply without using a Phase Locked Loop (PLL). A period of the input clock signal is measured by using a frequency to voltage converter. A reference capacitor charged by a constant current source is arranged to generate a reference voltage with a slope based on the period of the input clock signal. A change in the reference voltage across the reference capacitor is substantially inversely proportional to a frequency of the input clock. By providing the reference voltage to a sample-and-hold circuit and using an output of the sample-and-hold circuit to feed a comparator, synchronization may be accomplished. Each internal clock signal is generated by different reference capacitor and current source circuit.

Abstract: A buffer circuit includes a differential amplifier, a buffering inverter, and a reference voltage monitoring circuit. The differential amplifier has a reference voltage and a current source as inputs. The buffering inverter has an output of the differential amplifier as an input. The reference voltage monitoring circuit includes two transistors and a second current source. An output of the reference voltage monitoring circuit is connected to the buffering inverter so as to minimize an effect of a variation in the value of the reference voltage on signal propagation delay times. The buffer circuit can further include a driver circuit with a comparator. A method of managing signal propagation delays includes providing a differential amplifier, providing at least one buffering inverter, and providing a reference voltage monitoring circuit. The reference voltage monitoring circuit can maintain signal propagation delays as a reference voltage varies.

Abstract: Disclosed is method of controlling an asymmetric waveform generator including the steps of providing a reference timer signal, and generating an asymmetric waveform as a combination of a first sinusoidal wave having a first frequency and a second sinusoidal wave having a second frequency approximately twice the first frequency. The generated asymmetric waveform is sampled to obtain a set of data points, which set of data points is indicative of the generated asymmetric waveform. The method includes analyzing the set of data points in terms of at least a first function relating to an ideal sinusoidal wave of the first frequency, to determine a first set of resultant values relating to the first sinusoidal wave, and analyzing the set of data points in terms of at least a second function relating to an ideal sinusoidal wave of the second frequency, to determine a second set of resultant values relating to the second sinusoidal wave.

Abstract: An arrangement and a method in an integrated circuit for tuning and setting a value comprising a comparator circuit having a reference voltage input and a variable voltage input is provided to produce a digital value on an output depending on a comparison between the reference voltage and the variable voltage. A first clocked counter circuit is connected to the comparator to increase or decrease the value of the first clocked counter depending on the digital value supplied from the comparator. The arrangement further comprises a second clocked counter circuit connected to the comparator to increase the value of the second clocked counter for each change of value of the comparator, and a locking circuit connected to the second clocked counter circuit to lock the value stored in the first clocked counter circuit from further changes when the second clocked counter reaches a first threshold value.