Abstract: Supply voltage level detectors are disclosed. The supply voltage level detector comprises a voltage source divider dividing a voltage source to generate a detection voltage, a bandgap reference voltage generator, a comparator comparing the detection voltage with a bandgap reference voltage generated by the bandgap reference voltage generator to determine if the voltage source is ready, a control circuit, and a forcing circuit. To ensure reliability of the comparison result, the control circuit disables the comparing device until the bandgap reference voltage is available. The forcing circuit is coupled to the output terminal of the comparing device and is controlled by the control circuit. When the comparing device is disabled, the forcing circuit forces the voltage level of the output terminal of the comparing device to a specific value indicating the voltage source is unready.

Abstract: Known phase detectors have feedbackloops and do not function properly under severe conditions. By providing said phase detectors with difference establishers (1) for establishing differences between input signals and with selectors (2) for selecting one of said differences to be used as an output signal for phase locking purposes, the phase detectors operate better under more severe conditions, with any dead-zone having disappeared. Said selector (2) is a feedbackless selector, then a loop delay no longer exists, the linear range will not get any smaller for higher frequencies, the output jitter will not increase, for sampled input signals. Said selector (2) comprises latches (21,22) and a multiplexer (23). A converter (3) converts input signals into compensated input signals, via a buffer circuit (31,33) coupled to a replica circuit (32,34) per input signal, to provide input signals having substantially equal amplitudes and being compensated with process errors and temperature variations.

Abstract: A signal detection circuit includes a first signal multiplier operably coupled to square an input signal, a second signal multiplier operably coupled to square a reference signal, and a filter module operably coupled to produce a digital output representative of the input signal based on a squared input signal and a squared reference signal.

Abstract: A device for detecting an interface voltage of a Universal Serial Bus (USB) interface. The device includes first and second voltage level indicators, and first and second control circuits. The first control circuit receives the interface voltage to generate a first control signal and drive the first voltage level indicator when the interface voltage level is less than a first voltage level. The second control circuit receives the interface voltage to generate a second control signal and drive the second voltage level indicator when the interface voltage level exceeds a second voltage level.

Abstract: A constant-current driving circuit includes a first current source, a reference voltage generating circuit and an output signal generating circuit. A terminal of the first current source is coupled to a terminal of a first LED string, wherein the terminal of the first current source has a first voltage. The reference voltage generating circuit is used for generating a reference voltage and comparing the first voltage with a first predetermined voltage to generate a first comparing signal to thereby adjust the reference voltage. The output signal generating circuit is used for outputting an output signal to another terminal of the first LED string and receiving the input signal, wherein the output signal generating circuit decides whether or not to output the input signal serving as the output signal according to the comparison result of the reference voltage with the second voltage.

Abstract: A low-voltage detection reset circuit that suppresses a current consumption in a stand-by mode and is reduced in a size is offered. The low-voltage detection reset circuit is provided with a power-on reset circuit that operates only at power-on and outputs a reset pulse and is configured to set a detection level of a detection level setting circuit at a default value using the reset pulse and to activate a programmable low-voltage detection circuit. After the programmable low-voltage detection circuit is activated, a detection level of the programmable low-voltage detection circuit can be modified from the default value by a register.

Abstract: A method is provided for fabricating an electron emission source which can attain improved electron emission efficiency and has simplified manufacturing processes. Also provided are an electron emission display device and an electron emission display device fabricated using the method of fabricating an electron emission source. The method includes forming an electrode, forming a carbide compound thin film on the electrode and forming a carbide-induced carbon thin film layer from the carbide compound thin film using an etching gas. The electron emission device and the electron emission display device each include a first electrode, a second electrode disposed to face the first electrode, and a carbide-induced carbon thin film layer formed to be electrically connected to f the first electrode or the second electrode.

Abstract: A comparator includes: a CMOS inverter constituted by a combination of a first p-channel MOS transistor and a first n-channel MOS transistor; a second p-channel MOS transistor connected in parallel to the first p-channel MOS transistor in an analog input period, and disconnected from the first p-channel MOS transistor in a comparison period; and a second n-channel MOS transistor connected in parallel to the first n-channel MOS transistor in the analog input period, and disconnected from the first n-channel MOS transistor in the comparison period.

Abstract: A signal transfer system. A first device operates with a first voltage and outputs a first signal and a second signal. A protection circuit receives the first and second signals and outputs the first and second signals when the first voltage is greater than or equal to a predetermined voltage, and provides a third signal and a fourth signal when the first voltage is smaller than the predetermined voltage. A delay circuit delays the second and fourth signals to generate a first delay signal and a second delay signal, respectively. A second device operates with the first signal and the first delay signal when the first voltage is greater than or equal to the predetermined voltage, and operates with the third signal and the second delay signal when the first voltage is smaller than the predetermined voltage.

Abstract: Provided is a high voltage power supply which includes a controller to provide a PWM signal and a power signal, an input unit to receive the PWM signal provided from the controller, a comparison unit to control output of the power signal supplied from the controller by comparing a signal filtered to a DC voltage by the input unit to a voltage reference signal, a transformation unit to transform the power signal output from the comparison unit, and a rectification unit to rectify the signal output by the transformation unit, wherein the high voltage power supply further includes a power input delay unit to delay the supply of the power signal to the comparison unit by a predetermined time from when the power supplied from the controller for input into the comparison unit.

Abstract: A comparator for comparing a reference signal with a data signal includes a voltage boosting circuit, a first logic inverting circuit and a second logic inverting circuit. The voltage boosting circuit receives the reference signal to hold a voltage difference during a first time, and receives the data signal to generate a comparing signal according to the data signal and the voltage difference during a second time. The first logic inverting circuit is electrically connected to the voltage boosting circuit, outputs an initial signal to the voltage boosting circuit to hold the voltage difference during the first time, and inverts the comparing signal to output a first voltage signal during the second time. The second logic inverting circuit is electrically connected to the first logic inverting circuit during the second time, and inverts the first voltage signal to output a second voltage signal fed back to hold the comparing signal.

Abstract: A motor speed control circuit which controls a rotational speed of a motor by controlling an amount of current flowing through a drive coil of the motor. The control circuit comprises a reference voltage circuit that generates a reference voltage corresponding to a speed-specifying signal inputted to specify the rotational speed of the motor; a clamp circuit that limits a level of the reference voltage generated by the reference voltage circuit; a comparator that has a speed voltage corresponding to an actual rotational speed of the motor and the reference voltage limited in level by the clamp circuit applied thereto and compares the two; and a control signal generator that generates and outputs a control signal for controlling the amount of current flowing through the drive coil based on the comparing result of the comparator.

Abstract: A voltage comparator having hysteresis includes a comparing section that compares an input voltage with a reference voltage so as to output a high-level or low-level signal; and a reference voltage changing section that changes the reference voltage when a low-level signal is output from the comparing section.

Abstract: An IC includes an internal circuit that switches between on-state and off-state in response to an external signal and also includes an oscillator circuit that is externally synchronized. The IC further includes a state holding circuit that, when pulses for synchronizing the oscillator circuit are inputted to a standby pulse input terminal, applies, to the internal and the oscillator circuits, as an operation signal, a voltage obtained by rectifying pulses outputted from a comparator, and, when a constant voltage for non-operation is applied to the standby pulse input terminal for a given time period, applies, to the internal and oscillator circuits, as a non-operation signal, a constant voltage outputted from the comparator.

Abstract: A receiver for receiving a switched signal on a communication line (1), such as a LIN bus, the signal varying between first and second voltage levels (sup, ground). The receiver comprises a comparator (31, 54) responsive to the relative values of the received signal voltage level (Vlin) and an input reference voltage level (Vsup). The comparator (31, 54) comprises a current generator (40, 41) selectively operatble when the recieved signal is asserted to produce an input current (Iin) which is a function of the received signal voltage level (Vlin) and a reference current (Isup) which is a function of the input reference voltage level (Vsup), and output means (28, 32, 31; 55, 56) responsive to the relative values of the input current (Iin) and the reference current (Isup). The output means (28, 32, 31; 56) is supplied with power at a voltage (VDD) substantially lower than the difference between the first and second voltage levels (Vsup, ground).

Abstract: An electronic circuit includes an output terminal and at least a first measuring FET. The second drain-source terminals of a plurality of FETS to be tested are interconnected with the first drain-source terminal of the first measuring FET and the output terminal. The second drain-source terminal of the first measuring FET is interconnected with a first biasing terminal. The first drain-source terminals of the FETS to be tested are interconnected with a second biasing terminal. A state machine is coupled to the gates of the FETS to be tested and the gate of the first measuring FET. The state machine is configured to energize the gate of the first measuring FET and to sequentially energize the gates of the FETS to be tested, so that an output voltage appears on the output terminal. Circuitry to compare the output voltage to a reference value is also provided.

Abstract: Determining voltage level validity for a power-on reset condition is described. A supply voltage is applied to an integrated circuit. An oscillating signal is generated responsive to the supply voltage applied. A counting occurs responsive to oscillations of the oscillating signal. A triggering occurs responsive to reaching a first voltage level of the supply voltage for the power-on reset condition. A first count of the counting occurs responsive to the triggering. A second count is selected responsive to the first count. A second level is accepted as having at least met a threshold for the supply voltage responsive to the counting reaching the second count for the power-on reset condition.

Abstract: Apparatus to compare an input signal to a threshold level are disclosed. An example circuit described herein includes a Widlar bandgap circuit to receive the input signal, an intermediate stage coupled with the output of the Widlar bandgap circuit, and a final stage coupled with the output of the intermediate stage, the final stage to provide an output based on the input signal and the threshold level.

Abstract: The invention relates to a sense amplifier comprising the following element: a first current mirror unit coupled to a high voltage source, outputting a first current and a second current according to a first reference current, wherein the second current is twice the first current; a second current mirror unit coupled to a high voltage source, outputting a third current according to a second reference current; a first impedor coupled to the second current and a low voltage source; a second impedor coupled to the third current and a low voltage source; a third current mirror coupled to the first, second and third currents, and the first current is regarded as the reference current of the third current mirror unit, thus, the current which flows through the first impedor is the first current, and the current which flows through the second impedor is a fourth current.

Abstract: A comparator has: an offset setting portion adapted to set an offset voltage; an offset subtracting portion adapted to subtract the offset voltage from a non-inverting input voltage; and a comparing portion adapted to shift the output logic level thereof according to which of the output voltage of the offset subtracting portion and an inverting input voltage is higher.

Abstract: Embodiments of methods and apparatus for receiving data are disclosed. More particularly, methods of receiving a current mode signal, which can improve a signal to noise ratio (SNR) according to a change in a power supply voltage, and current mode comparators and semiconductor devices that use the methods are provided. A method of receiving a current mode signal includes receiving a reference current signal and a data current signal through a channel and generating a sensing voltage based on a difference between the reference current signal and the data current signal, varying a transconductance to reduce an input resistance of the current mode comparator in inverse proportion to an increase in a power supply voltage supplied to the current mode comparator, and converting the sensing voltage into a CMOS level output signal using the current mode comparator.

Abstract: An on-chip mode-setting circuit and method are provided for a chip having an output driver with an output terminal connected to a pin of the chip. The pin may be defined between two states from exterior of the chip. The on-chip mode-setting circuit includes an electronic element connected to a bias input of the output driver for producing a voltage when the pin is defined at one of the two states, and a voltage detector for monitoring the voltage to determine which one of the two states the pin is at, and producing a mode-setting signal accordingly.

Abstract: An electronic device for determining a type of a memory includes a comparator and a reset controller. The comparator for generating a discrimination signal according to a reference voltage and a first voltage of the memory, includes a first input end for receiving the first voltage, a second input end for receiving the reference voltage, a logic circuit coupled to the first input end and the second input end, for comparing the first voltage and the reference voltage so as to generate the discrimination signal, and an output end coupled to the logic circuit, for outputting the discrimination signal. The reset controller is used for determining the type of the memory according to the discrimination signal.

Abstract: A comparator with a fixed reference voltage (self bias) for an oscillator is disclosed. The comparator includes: a depletion MOS network to form a source current, wherein the gate and the source has a connection; and an enhanced MOS transistor, wherein the drain or the source connects with the depletion MOS transistor in series. The gate of the enhanced MOS transistor receives an input voltage when the input voltage is lower than the reference voltage, and the comparator outputs a high level voltage, or the enhanced MOS transistor outputs a low level voltage if the input voltage is higher then the reference voltage. Moreover, the oscillator's comparator has a reference voltage that is independent from temperature and supply voltage source.

Abstract: An input buffer having differential amplifiers for receiving input signals to generate an output signal. The input buffer operates with a relatively low supply voltage and a relatively wide range of input signal levels while improving the symmetry between rising and falling signal transitions of the output signal.

Abstract: The input buffer is driven by a data input/output supply voltage. The input buffer generates an output signal from an input signal that swings between the data input/output supply voltage and a data input/output ground voltage.

Abstract: A power supply monitoring circuit is provided that utilises an adaptive internal control of the refresh rates of capacitors to reduce the power requirements of the circuit. The circuit provides at an output a signal indicative of the level of the supply voltage relative to a predetermined reference voltage.

Abstract: A circuit exhibits a signal input, means for determining a reference level on the basis of properties of a signal received at the signal input. In addition, the circuit further exhibits means for evaluating the signal on the basis of the reference level.

Abstract: According to one exemplary embodiment, an amplitude compensation circuit includes a first composite programmable buffer for receiving a first input signal with a first input amplitude. The amplitude compensation circuit further includes a second composite programmable buffer for receiving a second input signal with a second input amplitude. The amplitude compensation circuit also includes a feedback circuit coupled to respective outputs of the first and second composite programmable buffers. According to this embodiment, the feedback circuit compares a first output amplitude of the first composite programmable buffer with a reference voltage and a second output amplitude of the second composite programmable buffer with the reference voltage and provides first and second control signals for adjusting the respective gains of the first and second composite programmable buffers so as to reduce respective differences between the first and second output amplitudes and the reference voltage.

Abstract: A voltage detection circuit for accurately detecting a voltage while suppressing the voltage fluctuation due to the off-leak current of a transistor. The voltage detection circuit includes first and second capacitors, first and second transistors, a comparator, and a control circuit. The capacitors are connected in series to generate a division voltage corresponding to a high voltage by the capacitors. The potential at a node between the first capacitor and the second capacitor is reset to ground potential when the transistors are activated. When the potential at the node reaches a predetermined potential, the first transistor is inactivated, and then the second transistor is inactivated.

Abstract: A negative voltage detector includes a first n-channel transistor having a coupled gate node and drain node, a second n-channel transistor having a gate coupled to the gate of the first n-channel transistor, a first current source coupled to a drain of the first n-channel transistor, a second current source coupled to a drain of the second n-channel transistor, an output terminal coupled to the drain of the second n-channel transistor, and an input terminal coupled to a source of the first n-channel transistor. The gate voltage of the first n-channel transistor, i.e., the gate voltage of the second n-channel transistor, depends on its source voltage (the voltage of the input terminal), and the switching operation of the second n-channel transistor can be performed by controlling the voltage of the input terminal to change the output voltage of the output terminal.

Abstract: A three-level detector circuit may comprise an input node and a pair of diode-connected transistors having respective drain terminals coupled to the input node. The pair of diode-connected transistors may be configured to set a voltage if the input voltage at the input node corresponds to an open input. The three-level detector circuit may further comprise a pair of inverting stages coupled to the input node, the pair of inverting stages configured to distinguish between low, high, and/or open inputs. The three-level detector circuit may also comprise a pair of latches, e.g. D-flip-flops, each of the pair of latches having a respective input coupled to a respective output of a respective one of the pair of inverting stages, and each of the pair of latches configured to latch a present state of the input in detection mode. In one set of embodiments, the three-level detector circuit is operable to cease conducting current after the present state of the input has been latched.

Abstract: An electric circuit for providing a selection signal being used to select a control value of a control variable which oscillates, at steady state, about a reference value about a first control value and a second control value with a first period duration comprises a first differential circuit which provides a first current being dependent on a difference between the first control value and the reference value. The electric circuit further comprises a second differential circuit which provides a second current being dependent on a difference between the reference value and the second value and a first node at which a differential current between the first current and the second current is formed. The differential current forms the selection signal indicating if the first control value or the second value is to be selected in order to minimize a difference between the reference signal and control variable.

Abstract: A low voltage detect circuit is provided herein for detecting when an external voltage (Vext) drops below a predetermined minimum voltage. In general, the low voltage detect circuit described herein may be configured to detect a low voltage condition based on a threshold voltage difference between a non-zero threshold transistor having a substantially non-zero threshold voltage, and a zero threshold transistor having a threshold voltage relatively close to zero. According to a particularly advantageous aspect of the invention, the low voltage detect circuit described herein comprises substantially no resistors or reference voltage generation circuits, and therefore, provides significant savings in both current and die area consumption without sacrificing accuracy. The low voltage detect circuit of the present invention is particularly useful in power regulators, such as those used in memory systems or devices.

Abstract: A signal detector includes, in part, first and second peak detectors, a comparator and an amplifier. The first peak detector generates a first signal in response to receiving an incoming signal. The second peak detector generates a second signal in response to receiving a threshold signal. The comparator generates an output signal representing the detected signal in response to the first and second signals. The amplifier amplifies the difference between the second signal and a reference voltage and, in response, generates a control signal that controls the gain of the first and second peak detectors. Each of the first and second peak detectors optionally include a differential amplifier and a pair of common-gate amplifiers each coupled to one of the output terminals of its associated differential amplifier. An RC network may be coupled to a common terminal of the first and second common gate amplifiers of each peak detector.

Abstract: An integrated circuit core power supply event monitor is disclosed. The integrated circuit core power supply event monitor includes a plurality of sub-circuit power supply event monitors. Each sub-circuit power supply event monitor includes a first input for receiving a first voltage, a second input for receiving a second voltage, a comparator for comparing the first voltage to the second voltage in order to detect an occurrence of a voltage deviation of the first voltage from a predetermined magnitude and an output for outputting an indicator of the occurrence of a voltage deviation of the first voltage from a predetermined magnitude if a voltage deviation of the first voltage from a predetermined magnitude occurs. A register for receiving the indicator of the occurrence of the voltage deviation of the first voltage from a predetermined magnitude and for registering the indicator of the occurrence of the voltage deviation from a predetermined magnitude.

Abstract: A signal amplitude threshold detector includes a comparator having first and second inputs. An input signal is coupled to the first input of the comparator. The second input of the comparator receives a reference voltage from a reference voltage generator. The signal amplitude threshold detector also includes a parallel combination of a capacitor and a resistor coupled between the first input of the comparator and ground. The comparator generates a first logic level when the amplitude of the input signal is less than the amplitude of the reference voltage, and it generates a second logic level when the amplitude of the input signal is greater than the amplitude of the reference voltage. The input signal may be supplied by a peak voltage detector, which supplies current to the capacitor when the peak amplitude of a signal is greater than the voltage on the capacitor.

Abstract: A system for detecting a direct current (DC) component of a pulse-width modulated (PWM) signal includes a modulator configured to provide at least one PWM signal to an input of an amplifier. A DC detector is configured to detect a DC component of a selected one of the at least one PWM signal as a function of a switching frequency of the selected PWM signal. The DC detector provides at least one report signal that indicates a level of the DC component of the selected PWM signal relative to a predetermined threshold.

Abstract: A digitally programmable hysteresis comparator a includes digitally programmable variable resistor. One or more control bits are operable to modify the resistance of the variable resistor, and such modification is operable to modify the hysteresis width of the comparator.

Abstract: An abnormality detection circuit monitors a power supply voltage and, when the power supply voltage drops, outputs an abnormality detection signal of a predetermined level. The source of a detection transistor as a P-channel MOSFET is connected to a power supply line to which a power supply voltage to be monitored is applied. A detection resistor as an impedance element is provided between the drain of the detection transistor and a ground terminal. A capacitor is provided between the gate of the detection transistor and the ground terminal. A charging path is provided between the gate of the detection transistor and the power supply line. The abnormality detection circuit outputs a drain voltage of the detection transistor as an abnormality detection signal.

Abstract: This invention provides a comparator circuit which outputs a stable waveform without oscillation even if a gradient of a change of a comparison input signal is small and determines a magnitude of the comparison input signal within a predetermined threshold value regardless of the increase/decrease direction of the comparison input signal.

Abstract: A comparator system for comparing a level of an input signal with a level of a reference signal comprises a first comparator configured to input the input signal to one of input terminals thereof and the reference signal to the other of input terminals thereof, a second comparator configured to input the reference signal to one of input terminals thereof and the input signal to the other of input terminals thereof, and a control circuit configured to input an output of the first comparator and an output of the second comparator. The control circuit selects one of the outputs of the first and second comparators quicker in level change timing, and controls an output signal of the control circuit at the level change timing of the selected output.

Abstract: A single end to differential signal converter comprising a low-frequency transmission step, which mixes the direct current and low-frequency components of single-ended signals with in-phase voltage signals to generate low-frequency signals, and a high-frequency transmission step, which mixes the high-frequency component of these single-ended signals and these low-frequency transmission signals to generate differential signals.

Abstract: A device for comparing the peak value of a periodic voltage signal or a linear combination of periodic voltage signals with a reference voltage includes a reference transconductor element for converting the reference voltage into a reference current, respective transconductor elements for converting each of the periodic voltage signals into respective periodic current signals, a current-comparison node for comparing the respective periodic current signals with the reference current, generating a comparison current as a difference between the sum of the aforesaid periodic current signals and the reference current, a current rectifier supplied with the comparison current, a hold capacitor charged with the output current of the current rectifier, and a discharge-current generator in parallel to the hold capacitor.

Abstract: An integrated semiconductor circuit has a potential detector for detecting a potential boosted by a high voltage generator. One terminal of a first capacitor is connected to a potential detection terminal via a first switching device, the other terminal thereof being connected to a reference potential terminal. A terminal of a second capacitor is connected, via a second switching device, to a first node at which the first switching device and the first capacitor are connected, the other terminal thereof being connected to the reference potential terminal. A third switch is connected between a second node at which the second switching device and the second capacitor are connected and the reference potential terminal. A clock generator generates clock signals to simultaneously and periodically turn on the first and the third switching devices whereas turn on the second switch periodically in an opposite timing for the first and the third switching devices.

Abstract: An apparatus for controlling an I/O interface of a chip operated in multi-power conditions includes an enable signal generator for generating an enable signal based on a chip power down signal; a reference voltage generator for generating a predetermined reference voltage in response to the enable signal; a comparator for determining a voltage required for operating the chip by comparing an external power voltage with the reference voltage in response to the enable signal; and an input/output means for performing an I/O interface function based on the voltage determined according to the comparison result of the comparator.

Abstract: A comparator circuit with reduced current consumption, and other circuits utilizing the same, are provided. The comparator circuit may achieve reduced current consumption by preventing current flow via a switching transistors responsive to the voltage level of the input signal.

Abstract: A power down reset circuit for asserting a signal when a first VDD voltage falls below a voltage threshold. The circuit has at least one diode coupled to the first VDD voltage. The at least one diode is configured to produce a second voltage. At least one capacitor is coupled to the at least one diode to maintain the second voltage. A voltage detector asserts a signal when the first VDD voltage drops below a threshold level. The voltage detector is powered by the second voltage and is coupled to the at least one diode.

Abstract: An output signal cutting-off circuit includes a first switching element, a driving circuit and a voltage-drop-signal generating circuit. When a voltage to be monitored becomes lower than a threshold voltage, a voltage-drop-signal is generated and supplied to the driving circuit. The driving circuit turns on the first switching element based on the voltage-drop-signal to thereby cut off an output signal voltage by bringing it to a ground potential. When the voltage-drop-signal disappears, the first switching element is turned off to bring the output signal to a normal state. Preferably, a second switching element for charging a capacitor and a third switching element for discharging the capacitor are used in the driving circuit. In this case, the first switching element is turned on or off based on a voltage of the capacitor.

Abstract: A direct current sum bandgap voltage comparator for detecting voltage changes in a power supply. The direct current sum bandgap voltage comparator includes a summing node, current sources connected to the summing node and the power supply, and an indicator circuit connected to the summing node. Each current source supplies a current to the summing node wherein the summing node voltage level is responsive to the currents supplied. The indicator circuit is responsive to changes in the summing node voltage level and generates at an output a logical signal at one state when the summing node voltage level is greater than a predetermined value and generates the logical signal at the output at another state when the summing node voltage level is less than the predetermined value, the predetermined value corresponding to a preselected power supply voltage.