Abstract: An active termination circuit is used to set the input impedance of a plurality of input terminals. Each of the input terminals is coupled to a supply voltage through at least one PMOS transistor and to ground through at least one NMOS transistor. The impedances of the transistors are controlled by a control circuit that generates a first control signal to set the impedance of another PMOS transistor to be equal to a first predetermined resistance, and generates a second control signal to set the impedance of another NMOS transistor to be equal to a second predetermined resistance. The first control signal is used to control all of the PMOS transistors and the second control signal is used to control all of the NMOS transistors. As a result the PMOS and NMOS transistors coupled to each input terminal have impedances corresponding to the first and second resistances, respectively.

Abstract: The present invention relates to a buffer circuit of a semiconductor memory device, and includes a common bias supply unit and a plurality of interface units having a differential amplifying structure. Each interface unit receives an input signal and differentially amplifies the input signal and a common bias. The common bias supply unit is driven by a reference voltage to provide the common bias signal to each of the interface units. The buffer circuit makes it possible to reduce the area occupied by the buffer circuit in a semiconductor memory device.

Abstract: A pulse width modulation (PWM) wave output circuit that efficiently and accurately outputs dual PWM waves includes two comparators, an OR circuit, and an AND circuit. A voltage generator supplies the comparators with ramp voltages having the same wave height and shifted phases. The comparator compares the ramp voltages with the reference voltage and provides the comparison results to the OR circuit and the AND circuit. The OR circuit outputs a first modulation wave, and the AND circuit generates a second modulation wave. Accordingly, modulation waves having different duties are output based on ramp voltage having different phases.

Abstract: Embodiments of methods and apparatus for receiving data are disclosed. More particularly, methods of receiving a current mode signal, which can improve a signal to noise ratio (SNR) according to a change in a power supply voltage, and current mode comparators and semiconductor devices that use the methods are provided. A method of receiving a current mode signal includes receiving a reference current signal and a data current signal through a channel and generating a sensing voltage based on a difference between the reference current signal and the data current signal, varying a transconductance to reduce an input resistance of the current mode comparator in inverse proportion to an increase in a power supply voltage supplied to the current mode comparator, and converting the sensing voltage into a CMOS level output signal using the current mode comparator.

Abstract: A circuit is for generating a signal that indicates whether or not an input current exceeds a pre-established threshold current and, in the affirmative case, that is representative of the difference between the input current and the threshold current. The circuit includes a diode-connected transistor biased with a first constant current in a saturation functioning condition, a sense transistor mirrored to the diode-connected transistor and biased in a linear (triode) functioning condition, a load transistor connected in series to the sense transistor, biased with a second constant current and the control terminal of which is connected in common with the respective terminals of the diode-connected transistor and of the sense transistor. The input current to be compared is injected to a common current node of the load transistor and of the sense transistor, and the output voltage is available on the other current node of the load transistor.

Abstract: The voltage of a detection resistor connected to the drain of a low-side switching device is normally a negative voltage, but a positive voltage appears when a countercurrent occurs in an abnormal state. A current comparator monitors the voltage of the detection resistor, transmits high output to an AND circuit whole the voltage of the detection resistor is a negative voltage to maintain the output voltage of the current comparator in a low state when an output signal of a driver can be transmitted to the low-side switching device, and allows the output voltage of the current comparator in a low state when the voltage of the detection resistor becomes a positive voltage, thereby forcibly turning off the low-side switching device.

Abstract: An integrated circuit die includes a microprocessor and a control circuit to control elements of a voltage regulator to supply power to the microprocessor.

Abstract: The present invention discloses a sense amplifier control circuit which controls the sense amplifier. A sense amplifier control circuit comprises a voltage comparing unit outputting delay control signals having a value corresponding to each of divided voltages obtained by dividing a potential of a power supply voltage and a pull-up control signal generating unit outputting an overdrive control signal and a pull-up control signal by an active signal and changing an enable pulse width of the overdrive control signal in response to the delay control signals, whereby it is possible to reduce current consumption caused by unnecessary overdrive operation and prevent a potential drop of the power supply voltage and thus provide operational stability of the semiconductor memory device by providing the overdrive control signal of which the enable pulse width is controlled in response to the potential of the power supply voltage.

Abstract: Power-on-reset circuitry is provided for integrated circuits such as programmable logic device integrated circuits. The power-on-reset circuitry may use comparator-based trip point voltage detectors to monitor power supply voltages. The trip point detectors may use circuitry to produce trip point voltages from a bandgap reference voltage. Controller logic may process signals from the trip point detectors to produce a corresponding power-on-reset signal. The power-on-reset circuitry may contain a noise filter that suppresses noise from power supply voltage spikes. Normal operation of the power-on-reset circuitry may be blocked during testing. The power-on-reset circuitry may be disabled when the bandgap reference voltage has not reached a desired level. The power-on-reset circuitry may be sensitive or insensitive to the power-up sequence used by the power supply signals.

Abstract: The invention relates to a detector circuit for detecting a change in voltage at a terminal or node with respect to a reference potential. The detector circuit comprises an electronic switch with a control terminal, which has a predetermined switching potential at which the switch operates, and with a detection signal output for outputting a detection signal, and a voltage matching circuit, which provides a control potential at the control terminal of the switch which corresponds to a potential of the terminal which has changed by a predetermined, fixed potential absolute value. The predetermined fixed potential absolute value is selected in such a way that the control potential corresponds to the switching potential or approximately to the switching potential when the reference voltage is applied to the terminal in such a way that the change in voltage to be detected causes the switching potential of the electronic switch to be exceeded or undershot.

Abstract: Provided are an IC and a method for automatically tuning process and temperature variations. The IC includes: a test circuit unit including test circuit elements having identical element values and variations to a tuning-targeted circuit element and at least one reference circuit element having a smaller variation than the tuning-targeted circuit element; a comparator that obtains a difference between intensities of first and second signals detected from the test circuit unit; and a tuning unit that tunes the variation of the tuning-targeted circuit element according to the difference between the intensities of the first and second signals. Thus, process and temperature variations of a circuit element can be detected and accurately tuned with respect to the circuit element itself. Also, the process and temperature variations can be tuned inside an IC. Thus, the time required for tuning the process and temperature variations can be reduced.

Abstract: In one embodiment, a method for a control interface includes: receiving a signal conveying bits of information over a single line; and for each bit of information, comparing the proportion of time that the signal on the single line is low versus the proportion of time that the signal on the single line is high for a respective bit period defined from one operative edge of the signal to the next operative edge of the signal in order to determine a logic value for that bit of information.

Abstract: The input buffer circuit of a semiconductor apparatus includes a first buffering unit that that is activated by a voltage level difference between a first voltage terminal and a second voltage terminal, and generates a first compare signal and a second compare signal by comparing the voltage levels of reference voltage and an input signal; a control unit that controls the amount of current flowing between the second voltage terminal and a ground terminal by comparing the voltage levels of the reference voltage and the second compare signal; and a second buffering unit that generates an output signal by comparing the voltage levels of the input signal and the first compare signal.

Abstract: A semiconductor IC device includes at least one IO port, a core logic, and at least one fail-safe IO circuit, the fail-safe IO circuit being coupled between the core logic and the IO port, wherein the fail-safe IO circuit is configured to receive a predetermined control signal and to maintain the IO port at a predetermined impedance with respect to the predetermined control signal.

Abstract: Power-on-reset circuitry is provided for integrated circuits such as programmable logic device integrated circuits. The power-on-reset circuitry may use comparator-based trip point voltage detectors to monitor power supply voltages. The trip point detectors may use circuitry to produce trip point voltages from a bandgap reference voltage. Controller logic may process signals from the trip point detectors to produce a corresponding power-on-reset signal. The power-on-reset circuitry may contain a noise filter that suppresses noise from power supply voltage spikes. Normal operation of the power-on-reset circuitry may be blocked during testing. The power-on-reset circuitry may be disabled when the bandgap reference voltage has not reached a desired level. The power-on-reset circuitry may be sensitive or insensitive to the power-up sequence used by the power supply signals.

Abstract: A semiconductor device includes a reference voltage generating unit configured to produce a reference voltage by dividing a voltage difference between a positive clock terminal and a negative clock terminal, and a logic determination unit configured to determine a logic level of an external signal based on the reference voltage.

Abstract: A voltage detection circuit for accurately detecting a voltage that is unaffected by fluctuation due to variations in transistor characteristics and threshold voltage. The voltage detection circuit includes a reference current generating section and a detecting section. The reference current generating section includes a voltage-controlled current source that includes a control terminal, a reference terminal and an output terminal. The reference current generating section generates an output current that serves as a reference current and output to a current mirroring circuit. The detecting section includes a number of voltage-controlled current sources each with the same configuration as the voltage-controlled current sources in the current generating section. A potential to be detected is input into the detecting section. A target potential is calculated as the set potential multiplied by the number of voltage-controlled current sources in the detecting section.

Abstract: An exemplary programming circuit (40) includes an input terminal (42) configured for receiving an external high voltage signal, a driving circuit (20), a switch circuit (43) connected between the input terminal and the driving circuit, and a feedback circuit (45). When the external high voltage signal is larger than a normal value thereof, the feedback circuit outputs a first control signal to turn off the switch circuit. When the external high voltage signal is less than the normal value thereof, the feedback circuit also outputs the first control signal to turn off the switch circuit. When the external high voltage signal is equal to the normal value thereof, the feedback circuit outputs a second control signal to turn on the switch circuit.

Abstract: A comparator circuit (300) has a first field effect transistor (FET) (307) with a supply voltage (301) connection and a diode connected FET (303) connected in series to form the first circuit leg of the comparator (300). A second diode connected FET (309) and a second FET (305) in series form the second circuit leg. The first FET (307) and said second FET (305) are approximately equal sized FETs. Another embodiment is an integrated circuit (401) with two n-channel FETs. A first diode connected FET (303) is connected to the first n-channel FET (307) in series to form the first circuit leg of a comparator (300) and a second diode connected FET (309) is connected to a second n-channel FET (305) in series to form the second circuit leg of the comparator. The two n-channel FETs that form the differential pair are approximately equal in size. The trip point is high with respect to the supply voltage.

Abstract: A brown-out-reset circuit having programmable power and response time characteristics. These characteristics may be programmed over an n-bit wide bus for 2n different characteristics ranging from very low power consumption and slower response time to very fast response time and higher power consumption. A serial one wire bus may be used instead of the n-bit wide bus.

Abstract: Example embodiments are directed to an over-voltage protection circuit and method thereof. The over-voltage protection circuit may include a voltage converter, a voltage comparator, a delay unit, and/or a switching unit. The voltage converter may be configured to generate first voltage and second voltages from a supply voltage. The voltage comparator may be configured to compare the first voltage with the second voltage and to generate a control signal according to the comparison result. The switching unit may be configured to determine whether to apply the supply voltage to a chip in response to the control signal. The delay unit may be configured to delay transmission of the control signal to the switching unit by a delay time.

Abstract: According to one exemplary embodiment, an amplitude compensation circuit includes a first composite programmable buffer for receiving a first input signal with a first input amplitude. The amplitude compensation circuit further includes a second composite programmable buffer for receiving a second input signal with a second input amplitude. The amplitude compensation circuit also includes a feedback circuit coupled to respective outputs of the first and second composite programmable buffers. According to this embodiment, the feedback circuit compares a first output amplitude of the first composite programmable buffer with a reference voltage and a second output amplitude of the second composite programmable buffer with the reference voltage and provides first and second control signals for adjusting the respective gains of the first and second composite programmable buffers so as to reduce respective differences between the first and second output amplitudes and the reference voltage.

Abstract: A current comparator includes an input node for receiving an input current, an output node, a first wide swing current mirror having an input coupled to the input node of the current comparator, a power node for receiving a first power supply voltage such as ground, and an output coupled to the output node of the current comparator, and a second wide swing current mirror having an input coupled to the input node of the current comparator, a power node for receiving a second power supply voltage such as VDD, and an output coupled to the output node of the current comparator. The output node can provide either a voltage or current output signal.

Abstract: A high-speed, low-power input buffer for an integrated circuit device in which the input voltage (VIN) is coupled to both a pull-up and a pull-down transistor. In accordance with a specific embodiment, the input buffer utilizes a reference voltage input (VREF) during a calibration phase of operation but not when in an active operational mode. A maximum level of through current is supplied when VIN=VREF with lower levels of through current at all other VIN voltages. In an integrated circuit device incorporating an input buffer as disclosed, two (or more) input buffers may be utilized per device input pin.

Abstract: A sleep mode control circuit and method are provided to pull high the error signal of a DC/DC switching power supply system to a target level when the switching power supply system is in a sleep mode, such that the switching power supply system can be more rapidly waked up from the sleep mode to its normal mode once the loading of the switching power supply system increases. A threshold is given for the output signal of the comparator that is used to determine the duty for the switching power supply system, and the error signal in the sleep mode is thus maintained slightly lower than the minimum voltage for the error signal in the normal mode.

Abstract: A semiconductor memory device includes a n-channel type MOSFET in which a drain and a gate are connected to an external power supply and a source and a back gate are connected each other. A node is connected to the source and the back gate of the n-channel type MOSFET, and a detector for detecting an input of the external power supply based on a potential of the node.

Abstract: A semiconductor integrated circuit includes a first external terminal for receiving a voltage converted by a resistance portion from a current varying in response to an extrinsic factor, a second external terminal for externally outputting the voltage received at the first external terminal as a detection signal, a control circuit outputting a control signal for changing a resistance value of the resistance portion based on the voltage received at the first external terminal, and a third external terminal for outputting the control signal to the resistance portion.

Abstract: A high-speed receiver suitable for applications that desire a common-mode voltage range from approximately 0.7V to approximately 0.9V is arranged by coupling first and second differential pair circuit architectures based on first and second current-steering schemes into the same path to generate an output signal. The high-speed receiver includes first and second differential pair circuits. The first differential pair circuit is coupled to a first current-steering path via a first port and a second current-steering path via a second port. The second differential pair circuit is coupled to the first current-steering path via a third port and the second current-steering path via a fourth port. A bridge circuit is interposed between the first and second differential pair circuits. The bridge circuit integrates the first and second current-steering paths in a single-stage of the high-speed receiver assembly.

Abstract: An apparatus, method, and discriminator circuit are provided for filtering false signals. A discriminator circuit receives a low-state signal via an input and, responsive to receiving the low-state signal, the discriminator circuit compares the low-state signal to a static signal. Responsive to the low-state signal being greater than the static signal, the discriminator circuit outputs a high-voltage signal. The high-voltage signal output by the discriminator circuit indicates that the low-state signal is a false low signal. Responsive to the low-state signal being less than or equal to the static signal, the discriminator circuit outputs a low-voltage signal. The low-voltage signal output by the discriminator circuit indicates that the low-state signal is a valid low signal.

Abstract: An electronic device supplied by multiple supply voltages includes a bias current generating stage and maximum current selection stage. The bias current generating stage comprises a crude bias current generator for generating an crude bias current during a power up phase in which at least one of the multiple supply voltages has not yet reached its target supply voltage level, a reference current stage for providing a reference current having a target current value greater than the target value of the crude bias current when the multiple supply voltages have reached their target supply voltage levels. The maximum current selection stage is adapted to continuously output a bias current which is the maximum current of the crude bias current and the reference current.

Abstract: A self-biasing slicer includes a self-biased differential transistor pair. As a result of the self-biasing, the slicer may receive input signals without the use of AC coupling. That is, a differential input signal may be fed directly to the inputs of the differential transistor pair. The differential pair circuit may incorporate a self-biased load and a self-biased current source. The slicer also may include a matched output stage with inverters that provide a rail-to-rail output. Here, the inverters may incorporate components that are matched with components of the differential pair.

Abstract: A sense amplifier according to the present invention for detecting a potential difference of signals input to a first input terminal and a second input terminal, includes a first means for applying voltages corresponding to threshold voltages of first and second transistors to gate-source voltages of the first and second transistors, and a second means for transferring signals input to the first and second input terminals to gates of the first and second transistors. In this case, a threshold variation of the first and second transistors is corrected.

Abstract: A level detector within a back-bias voltage generator includes a toggling unit and a temperature detector. The toggling unit causes an enable signal to be activated when an absolute value of a back-bias voltage is less than an absolute value of a monitoring level. The temperature detector controls the toggling unit for increasing the absolute value of the monitoring level with an increase in temperature with high temperature sensitivity.

Abstract: A comparator-based driver has a configurable inverter that inverts one of the comparator output signals for application to the gate of a driver transistor used to generate the driver output signal. The configurable inverter can be selectively configured to provide any one of at least two different inverter logic threshold levels. In one possible operational scenario, the configurable inverter is configured such that the inverter logic threshold level is equivalent to the comparator's differential common-mode voltage to provide relatively high driver symmetry. The configurable inverter is then configured to provide a different inverter logic threshold level that is greater than the comparator's differential common-mode voltage to inhibit chattering in the driver output signal.

Abstract: A data trigger reset device for an electronic device is provided in order to avoid system errors due to out-of-sequence reset on electronic devices of an electronic system. The data trigger reset device includes a voltage converter and a voltage comparator. The voltage converter receives an input signal and then converts the input signal to generate a data voltage signal. The voltage comparator is coupled to the voltage converter and is used for comparing the data voltage signal with a reference voltage to generate a reset signal for resetting the electronic device.

Abstract: A circuit including a comparing unit for comparing a target voltage with a stepwise-varying tracking voltage, a counting unit for counting a code according to the comparison result of the comparing unit and a control signal generating unit for generating a signal for controlling a counting operation of the counting unit.

Abstract: A current mode comparator for a semiconductor device is disclosed. The current mode comparator may include a logic circuit coupled to a voltage sensing node, a first cascode coupled to the voltage sensing node and a first power node, and a second cascode coupled to the voltage sensing node and a second power node. The logic circuit may convert a voltage of the voltage sensing node to an output signal.

Abstract: A comparator is provided that outputs a comparison result obtained by comparing two signals.

Abstract: A comparator has P-channel field effect transistors that are supplied at respective gates with input voltages Vin and Vref, which are objects of comparison, and that act as a differential transistor pair; and N-channel field effect transistors that serve as current channels for respective drain currents of these two P-channel field effect transistors and that act as a current mirror circuit. The comparator outputs a drain voltage Vx of an N-channel field effect transistor as a signal showing a result of comparison between the two input voltages. An N-channel field effect transistor diode-connected to the comparator is interposed between drains of the N-channel field effect transistors.

Abstract: A time constant calibration device includes: a first voltage generating circuit utilizing a first current passing through a capacitive component to generate a first voltage; a second voltage generating circuit utilizing a second current passing through a resistive component to generate a second voltage; and a comparing circuit for comparing the first voltage with the second voltage to generate a comparing signal, wherein the first voltage generating circuit comprises an analog adjusting component for adjusting the first voltage according to the comparing signal until the first voltage is equal to the second voltage whereby an RC time constant defined by an equivalent capacitance corresponding to the first current passing through the capacitive component and an equivalent impedance corresponding to the second current passing through the resistive component reaches a predetermined value.

Abstract: A semi-dual reference voltage data receiving apparatus includes a first input buffer, a second input buffer, and a phase detector wherein the first input buffer includes a first input receiving unit, a first sense amplifier, and a first current offset controlling unit. The first sense amplifier senses and amplifies the voltage difference between the voltage of a first terminal of a first input transistor and the voltage of a first terminal of a second input transistor. The first current offset controlling unit controls the offset of the current that flows through the second terminal of the second input transistor.

Abstract: An upper end voltage and a lower end voltage of a current detection resistor Rs are supplied, via first and second switches S1 and S2, to one end of a main capacitor Ci. A reference voltage VREF is supplied, via a third switch S3, to the other end of the main capacitor Ci. The operational amplifier OP has a negative input terminal to which a voltage of the other end of the main capacitor Ci is supplied and a positive input terminal to which the reference voltage VREF is supplied. The circuit performs an operation for charging the main capacitor Ci with a voltage corresponding to a difference between the lower end voltage and the reference voltage in a state where the first and third switches S1 and S3 are turned on and the second switch S2 is turned off.

Abstract: A data input buffer in a semiconductor is capable of avoiding operation speed deterioration of the data input buffer due to the temperature condition or process characteristic. The data input buffer in a semiconductor device includes an input detecting unit for detecting logic level of input data by comparing the voltage level of the input data with a reference voltage, a current driving capability adjusting unit for adjusting current driving capability of the input detecting unit based on at least one of temperature condition and process characteristic, and a buffering unit for buffering the output signal from the input detecting unit.

Abstract: A semiconductor device can output a reference voltage for an arbitrary potential and can detect the voltage of each cell in a battery including multiple cells very precisely. The device includes a depletion-type MOSFET 21 and an enhancement type MOSFET 22, and has a floating structure that isolates depletion-type MOSFET 21 and enhancement type MOSFET 22 from a ground terminal. The depletion-type MOSFET 21 and enhancement type MOSFET 22 are connected in series to each other, wherein the depletion-type MOSFET 21 is connected to high-potential-side terminal and the enhancement type MOSFET 22 is connected to low-potential-side terminal. The semiconductor device having the configuration described above is disposed in a voltage detecting circuit section in a control IC for a battery including multiple cells.

Abstract: A voltage comparator circuit includes a voltage input terminal, a first resistor, a second resistor, a first transistor, a second transistor, and a voltage output terminal connected to the collector of the second transistor. The voltage input terminal is connected to ground via the first and second resistors in turn. A node between the first and second resistors is connected to the base of the first transistor. The emitter of the first transistor is grounded. The collector of the first transistor is connected to a direct current (DC) power supply and the base of the second transistor. The emitter of the second transistor is connected to the DC power supply.

Abstract: A comparator circuit of the present invention includes a comparator section and a current buffer circuit. In a normal mode, a standby current outputted from the comparator section is amplified by a predetermined times at the current buffer circuit. On the other hand, the standby current is not amplified in a standby mode.

Abstract: A current control circuit is coupled in parallel with the current paths of a differential comparator circuit to ensure that a substantially constant current is drawn from a current source during all operating phases of a comparator. The current control circuit is biased by a reference voltage, which is also used to bias a V? input terminal of the differential comparator circuit. The reference voltage is stored by a sample capacitor, which is charged by applying the reference voltage to a V+ input terminal of the differential comparator circuit while coupling an output terminal of the differential comparator circuit to the sample capacitor in a unity feedback configuration.

Abstract: A three-level detector circuit may comprise an input node and a pair of diode-connected transistors having respective drain terminals coupled to the input node. The pair of diode-connected transistors may be configured to set a voltage if the input voltage at the input node corresponds to an open input. The three-level detector circuit may further comprise a pair of inverting stages coupled to the input node, the pair of inverting stages configured to distinguish between low, high, and/or open inputs. The three-level detector circuit may also comprise a pair of latches, e.g. D-flip-flops, each of the pair of latches having a respective input coupled to a respective output of a respective one of the pair of inverting stages, and each of the pair of latches configured to latch a present state of the input in detection mode. In one set of embodiments, the three-level detector circuit is operable to cease conducting current after the present state of the input has been latched.

Abstract: Circuit arrangement for detecting a power down situation of a second voltage comprising a first conductor, adapted the be connected to a first voltage, a second conductor, adapted the be connected to a reference voltage, an input node, adapted the be connected to the second voltage, and two output nodes, a first output node and a second output node. The output nodes are interconnected in such a manner, that (a) when the second voltage is higher than the reference voltage, the first output node is at the first voltage level and the second output node is at the reference voltage level, and (b) when the second voltage is equal to the reference voltage, the first output node is at the reference voltage level and the second output node is at the first voltage level.

Abstract: An electronic circuit device has a current correction circuit that supplies a correction current which is capable of offsetting an increment or a decrement of a consumption current of a signal processor circuit that varies based on a signal level of an input signal. Therefore, even if the consumption current of the signal processor circuit varies based on the signal level of the received input signal, the variation of the consumption current is offset by the current correction circuit. As a result, even if the consumption current varies based on the signal level of the input signal, since a current that flows in a resistor does not vary, a voltage drop can be held constant. Accordingly, it is possible to accurately conduct a comparison determination by a comparator.