Abstract: A semiconductor device provided which includes: an external power supply detection circuit which detects that an external power supply is turned on and outputs a first detection signal; an internal power supply voltage generation circuit which generates an internal power supply voltage based on the external power supply; a reference voltage generation circuit which generates a first reference voltage in response to the first detection signal; a reference voltage detection circuit which detects that the first reference voltage reaches a given level and outputs a second detection signal; a bias voltage generation circuit which, in response to the second detection signal, generates a bias voltage based on a second reference voltage dependent on the first reference voltage; and a power supply voltage detection circuit which, in response to the second detection signal, compares the bias voltage with a third reference voltage and outputs a start signal.

Abstract: An apparatus for providing programmable hysteresis control using an enable pin of a device is disclosed. An enable pin is configured to receive an input signal to enable and disable an associated device responsive to the input signal. A current sink is attached to the enable pin and is responsive to circuitry that disables the current sink responsive to application of the input signal at a first voltage level and enables the current sink responsive to application of the input signal at a second voltage level.

Abstract: An voltage detection device includes a comparator circuit comprising a first input terminal connected to a system power supply, a second input terminal connected to a standby power supply, an output terminal capable of outputting a control voltage according to comparison result; an indicator circuit; and a switch circuit connected between the standby power supply and the indicator circuit, comprising a control terminal to receive the control voltage from the comparator circuit thereby to control the standby power supply supplied to the indicator circuit or not; a power state terminal of the computer connected to a node between the standby power supply and the indicator circuit, wherein the power state terminal is at a low level when the computer is turned off. The voltage detection device can ensure that all the power supplies provide power to the computer components normally.

Abstract: A switching transistor has its drain and source respectively connected to a gate and a source of an output transistor for supplying output current to a load, and its gate connected to an internal grounding wire GW to be connected to a grounding terminal GND. A resistance element R1 connects the gate to the source of the switching transistor. When a voltage not smaller than a predetermined value is generated across the resistance element R1 at turn-on, due to a parasitic capacitance existing between a power supply terminal. Vcc and the internal grounding wire GW, the switching transistor can be turned on to turn off the output transistor.

Abstract: A comparator comprises a differential amplifier (T1, T2, T8, T9) having differential inputs (IN1, IN2) forming the comparator inputs, and a first and a second amplifier output (f1, f2) forming the comparator outputs of a first comparator stage, wherein the differential amplifier has first (T1, T8) and second (T2, T9) parallel branches. The comparator has a first current source circuit (32) defines a current to be driven through the differential amplifier, a second current source circuit (34) comprising a load driven by the first branch and a third current source circuit (36), comprising a load driven by the second branch. Circuitry (T6,T7) is provided for defining the voltage difference between the first and second amplifier outputs when the differential amplifier is in a stable state providing a differential output. This arrangement drives current through the two branches independently, so that the main transistors in each branch can be kept on to enable rapid response times.

Abstract: A power-on-detection (POD) circuit includes first and second comparators, a voltage divider, a detection circuit coupled to a first voltage source node and the voltage divider, and logic circuitry coupled to outputs of the first and second comparators. The detection circuit outputs a control signal identifying if a first voltage source node has a voltage potential that is higher than ground. The control signal turns on and off the first and second comparators, which are respectively coupled to first and second nodes of the voltage divider and to a reference voltage node. The logic circuitry outputs a power identification signal based on the signals received from the outputs of the first and second comparators.

Abstract: A circuit adapting pin output levels to a reference level in which a digital comparator compares an output voltage from an output pin of a device to a reference voltage level. The comparator, relying on the polarity of the comparator output as well as the registered polarity of the comparator output on the previous clock cycle, signals a state machine, which sends a clocked signal to a sense circuit and voltage regulator. The sense circuit may modify a resistance in a switched resistor network, such that the output level is incrementally stepped at clocked intervals towards the reference voltage until the polarity of the error signal reverses. When the output voltage crosses the reference voltage threshold, the comparator flips states and continues to regulate output pin voltage to the reference voltage level.

Abstract: An integrated circuit die includes a microprocessor and a control circuit to control elements of a voltage regulator to supply power to the microprocessor.

Abstract: A comparator circuit (300) has a first field effect transistor (FET) (307) with a supply voltage (301) connection and a diode connected FET (303) connected in series to form the first circuit leg of the comparator (300). A second diode connected FET (309) and a second FET (305) in series form the second circuit leg. The first FET (307) and said second FET (305) are approximately equal sized FETs. Another embodiment is an integrated circuit (401) with two n-channel FETs. A first diode connected FET (303) is connected to the first n-channel FET (307) in series to form the first circuit leg of a comparator (300) and a second diode connected FET (309) is connected to a second n-channel FET (305) in series to form the second circuit leg of the comparator. The two n-channel FETs that form the differential pair are approximately equal in size. The trip point is high with respect to the supply voltage.

Abstract: An electronic device supplied by multiple supply voltages includes a bias current generating stage and maximum current selection stage. The bias current generating stage comprises a crude bias current generator for generating an crude bias current during a power up phase in which at least one of the multiple supply voltages has not yet reached its target supply voltage level, a reference current stage for providing a reference current having a target current value greater than the target value of the crude bias current when the multiple supply voltages have reached their target supply voltage levels. The maximum current selection stage is adapted to continuously output a bias current which is the maximum current of the crude bias current and the reference current.

Abstract: A circuit for controlling an internal voltage is provided. The circuit for controlling an internal voltage, comprising: a level detector configured to detect a voltage level of a core voltage to generate a core voltage level detection signal; a release controller configured to generate a release control signal according to the core voltage level detection signal; and a core voltage release driver configured to release the core voltage according to the release control signal.

Abstract: A semiconductor memory device of the present invention determines a logic level of a signal based on a predetermined reference voltage. And the memory device has an input terminal to which a reference signal having the reference voltage is input, a low-pass filter connected to the input terminal for passing a component of the reference voltage of the reference signal and eliminating undesired high frequency components, and one or more input first-stage circuits to each of which an output of the low-pass filter and a signal having the logic level to be determined are connected. In the memory device, the low-pass filter has predetermined attenuation at least at a frequency of an operating clock.

Abstract: The present disclosure relates to reduction in the effect of kickback in comparators by means of charge injection implemented by means of voltage controlled switches with attributes similar to those of an input differential pair. The voltage controlled switches produce charge to neutralize the charge loss during latching of inputs in the comparator.

Abstract: A wired signal receiving apparatus including a signal receiver, a signal peak detector, and a signal comparator is disclosed. The signal receiver includes an operation current detecting circuit for detecting an operation current. The signal receiver further receives a transmission signal. The signal peak detector receives the operation current, detects a peak thereof, and generates a peak current. The signal comparator compares a reference signal and the peak current to generate an output current for regulating the operation current.

Abstract: A voltage detecting circuit for comparing a voltage to be detected with a reference voltage and outputting an output signal having a level depending on the comparison is disclosed. The voltage detecting circuit includes an inverting amplifier circuit configured to receive an intermediate signal having a level depending on the comparison and output the output signal. The inverting amplifier circuit includes an active element having a control terminal. A threshold voltage of the control terminal is as low as or lower than the reference voltage. The voltage to be detected is applied to the control terminal of the active element.

Abstract: An apparatus for preventing abnormal voltage, a light emitting module, and a display apparatus are provided. The present apparatus for preventing abnormal voltage extracts the highest voltage and the lowest voltage among voltage applied from a plurality of loads, includes two voltage distribution units distributing the highest voltage and the lowest voltage, and detects whether the highest voltage and the lowest voltage applied from the voltage distribution unit are within a predetermined range. Accordingly, the apparatus for preventing abnormal voltage is not affected greatly in terms of its size and cost even if the number of loads to be protected increases.

Abstract: A start signal detection circuit includes a wave-detection circuit 1 outputting a voltage in accordance with an envelope of a radio signal from an output point B, a reference voltage generation circuit 2 outputting a voltage at the output point B at a non-signal state as a reference voltage to a reference point C, and a differential amplification circuit 3 amplifying and outputting a voltage difference between the output point B and the reference point C.

Abstract: An electric circuit device includes: a power supply line; a load circuit; a current supply controller which compares a voltage of the power supply line with a certain voltage; and a current supply circuit which supplies a electric current from the power supply line to the load circuit and changes the electric current during a supply of the electric current.

Abstract: Disclosed is a signal output circuit comprising: a first transistor of an emitter follower configuration, which receives an input signal; a second transistor of an emitter follower configuration, which receives the input signal, and has an output connected to an external load (106); a comparator circuit which has an input pair connected via resistors to emitters of the first and the second transistors; a first current mirror circuit which has an input connected to an output of a first current source transistor and an output connected to an emitter of the first transistor; and a second current mirror circuit which has an input connected to a connection node of an output of a second current source transistor and an output of the comparator circuit, and has an output connected to an emitter of the second transistor.

Abstract: A comparator circuit for providing hysteresis comprises first and second differentially coupled transistors. The first of the differentially coupled transistors provides drain current to first and second load transistors. The second of the differentially coupled transistors provides drain current to third and fourth load transistors. In one example embodiment, the drain of the first of the differentially coupled transistors also drives the gate of the first and third load transistors, while the drain of the second of the differentially coupled transistors drives the gate of the second and fourth transistors.

Abstract: An interrogation circuit for a nanowire sensor array and a method for interrogating a nanowire sensor array are provided. The circuit comprises a switch array connected to the nanowire sensor array for selectively connecting first ends of nanowire sensors of the nanowire sensor array to a reference voltage; an integration amplifier (IA) connected to second ends of the nanowire sensors at a first input of the IA and to the reference voltage at a second input of the IA, for generating an oscillating output signal clamped between first and second voltage values; wherein the switch array is further arranged for switching one of the nanowire sensors to be connected in a closed loop with the IA such that a current through said one nanowire sensor periodically charges and discharges an integration capacitor of the IA for determining a resistance of said one nanowire sensor from a frequency of the periodic charging and discharging.

Abstract: A circuit for detecting noise peaks on the power supply of an electronic circuit, including at least a first transistor having its control terminal connected to a terminal of application of a first potential of a supply voltage of the circuit and having a first conduction terminal connected to a terminal of application of a second potential via at least one first resistive element, the second conduction terminal of the first transistor providing the result of the detection.

Abstract: A comparator has P-channel field effect transistors that are supplied at respective gates with input voltages Vin and Vref, which are objects of comparison, and that act as a differential transistor pair; and N-channel field effect transistors that serve as current channels for respective drain currents of these two P-channel field effect transistors and that act as a current mirror circuit. The comparator outputs a drain voltage Vx of an N-channel field effect transistor as a signal showing a result of comparison between the two input voltages. An N-channel field effect transistor diode-connected to the comparator is interposed between drains of the N-channel field effect transistors.

Abstract: A semiconductor device includes a substrate on which an electronic circuit is provided. One or more pads may be present which can connect the electronic circuit to an external device outside the substrate. A current meter is electrically in contact with at least a part of the substrate and/or the pad. The meter can measure a parameter forming a measure for an amount of a current flowing between the substrate and at least one of the at least one pad. A control unit is connected to the current meter and the electronic circuit, for controlling the electronic circuit based on the measured parameter.

Abstract: A reset signal generating circuit outputs a reset signal having a sufficient pulse width even when the power supply voltage is fluctuated. A node B reaches a high level during a power-on reset and is at a low level during operation. When a power supply (Vcc) fluctuates during operation and as soon as a node C reaches a high level, a switch element MN50 turns on, the node B is decreased to a low level, and a stable low-level reset signal RST1 is outputted. When the node B reaches a low level, a switch element MN51 turns off with a delay and capacitors 104 and 105 are gradually charged by a charging circuit 112. When the potential at the node B exceeds a threshold level of an inverter circuit 106, the reset signal RST1 is brought back to a high level, the reset is cancelled, the switch element MN50 is turned off, and the switch element MN51 is brought to be in an on-state again (FIG. 1).

Abstract: A signal detection circuit is used for detecting signal squelch of a differential input signal to generate a corresponding digital output signal. The signal detection circuit includes: a reference voltage generator for generating a reference voltage of which the common mode voltage tracks the common mode voltage of the input signal; a real-time signal judgment circuit, real-time rectifying and amplifying a difference between the input signal and the reference voltage; and a deglitch circuit, sampling and/or amplifying an output signal of the real-time signal judgment circuit, and transforming sampling results into the digital output signal to reflect signal squelch of the differential input signal.

Abstract: The power on reset circuit includes: a comparator; a resistor string having a first end coupled to a first supply node of the comparator, a first tap point node coupled to a first input of the comparator, and a second end coupled to a second input of the comparator; and a diode connected transistor device coupled between the second end of the resistor string and a second supply node of the comparator.

Abstract: Power-down mode is activated when equal voltages are detected on a pair of differential inputs. The voltage difference across the differential inputs is equalized by an equalizer and then applied to a multiplier and smoothed and filtered by a low-pass filter to produce an average signal. The average signal is compared to a reference voltage to detect when the voltage difference across the differential inputs is too small. A power-down signal is activated when the average signal is too small. The reference voltage compared can be generated by an equalizer, multiplier, and low-pass filter to match process, temperature, and supply-voltage variations in the primary signal path. The multipliers can be implemented with Gilbert cells. The equalizers can receive control signals to control attenuation of different frequency components.

Abstract: A level detector has an input circuit adapted to accept signals of multiple signal levels for detecting a specific level. The signal levels include a first signal level and a larger second signal level. Electronic components of the input circuit have reliability levels less than the second signal level. A latch circuit is coupled to the input circuit for latching a signal consistent with a detected level of an accepted signal.

Abstract: A comparator formed by first and second stages. The second stage is formed by a pair of output transistors connected between a power-supply line and respective output nodes; a pair of bias transistors, connected between a respective output node and a current source; a pair of memory elements, connected between the control terminals of the output transistors and opposite output nodes; and switches coupled between the control terminals of the respective output transistors and the respective output nodes. In an initial autozeroing step, the first stage stores its offset so as to generate an offset-free current signal. In a subsequent tracking step, the second stage receives the current signal and the memory elements store control voltages of the respective output transistors. In a subsequent evaluating step, the first stage is disconnected from the second stage and the memory elements receive the current signal and switch the first and the second output node depending on the current signal.

Abstract: A power detect system and circuit for detecting a voltage level of an input/output supply voltage (VDDIO) in a circuit of low voltage devices is disclosed. In one embodiment, the power detect system and circuit includes a voltage divider coupled between the VDDIO and a negative supply voltage (VSS) for generating a bias voltage, a first inverter coupled between a core voltage (VDD) and the VSS for generating a first node voltage based on the bias voltage, a native device coupled between the VDDIO and the VSS for generating a second node voltage based on the bias voltage, and a switch coupled between the first inverter and the native device for controlling the second node voltage based on the first node voltage. The power detect system further includes a second inverter coupled between the VDD and the VSS for generating an output voltage based on the second node voltage.

Abstract: Provided is a voltage detection circuit that outputs a detection result when a voltage to be measured exceeds a predetermined voltage or falls below the predetermined voltage at a speed higher than that of a conventional case. The voltage detection circuit according to the present invention includes an input buffer that outputs a detection voltage to be input as an input voltage, and a voltage detection section that accelerates a rising of the input voltage in a transient state where the input voltage exceeds a predetermined threshold value, and accelerates a dropping of the input voltage in a transient state where the input voltage falls below the predetermined threshold value. The voltage detection circuit accelerates a change in the input voltage to output the detection result from an output buffer at high speed.

Abstract: An output signal generating device according to the present invention includes a control circuit for generating a control signal, a reference signal generating unit for generating a reference signal, an output signal generating unit for generating an output signal according to a comparison result between the control signal and the reference signal, an output signal detecting unit for detecting the output signal based on a sampling signal, and an output signal storage unit for storing the output signal detected by the output signal detecting unit. The control circuit includes a readout unit for reading out the output signal stored in the output signal storage unit. According to the present invention, the output signal can be stored in real time and the results thereof can be processed by software.

Abstract: A low voltage shutdown circuit comprises an input node for receiving a voltage Vin to be monitored, first and second voltage-to-current (V to I) converters arranged to receive Vin at respective inputs and to convert Vin to currents I1 and I2 at respective outputs, and a current comparison circuit arranged to produce an output which is in a first state when I1<I2 and in a second state when I1>I2. The V to I converters have respective voltage-to-current transfer functions which intersect at a non-zero threshold voltage Vth, such that the current comparison circuit output toggles when Vin<Vth. This output can be used as needed to, for example, trigger the shut down of other circuitry.

Abstract: A signal comparison circuit is provided. The signal comparison circuit includes a first amplifier, a second amplifier, a peak detector, and a comparator. The first amplifier is a zero-peaking amplifier. The first amplifier receives and amplifies a data signal. The second amplifier receives and amplifies a reference voltage. The peak detector is coupled to the first and the second amplifiers for detecting and maintaining maximum values of the amplified data signal and the amplified reference voltage, and then outputting the maintained data signal and the maintained reference voltage. The comparator is coupled to the peak detector for comparing the maintained data signal with the maintained reference voltage and outputting a result of the comparison.

Abstract: A comparator circuit, includes first and second terminals to which a reference voltage that determines a threshold voltage is inputted, a third terminal to which a standard voltage is inputted, a fourth terminal to which a target voltage that is to be detected and is based on the standard voltage is inputted, first and second transistors of a first conductivity type including control terminals connected to the first and second terminals, respectively, the first and second transistors flowing currents depending on a potential difference of the reference voltage, a third transistor of a second conductivity type connected in series with the first transistor, a fourth transistor of the second conductivity type connected in series with the second transistor, a fifth transistor of the second conductivity type through which a mirror current depending on a current flowing through the third transistor, a sixth transistor of the second conductivity type flowing a mirror current depending on a current flowing through th

Abstract: A comparing circuit of the present invention includes: a charging and discharging circuit to charge a capacitor with charging current and discharge the capacitor with discharging current alternately in response to a switch of an input pulse signal; a comparator circuit to compare a capacitor-voltage (Csig) of the capacitor with a first threshold voltage (Vth1) and the capacitor-voltage (Csig) with a second threshold voltage (Vth2), which is higher than the first threshold voltage, to generate a pulse signal responsive to a result of this comparison, and to supply an output-signal generating circuit with the pulse signal to switch a level of an output pulse-signal; and a logical operation circuit to adjust a value of the charging current and a value of the discharging current by generating a signal that is based on the pulse signal and is to adjust the value of the charging current and the value of the discharging current of the charging and discharging circuit and supplying the charging and discharging circui

Abstract: A receiving apparatus and method for compensating a clock-inconsistency between a transmitter and a receiver for a digital wavelet multi-carrier transmission. First and second wavelet transforms of received data are performed to output first and second transformed data and then a complex data generator generates the complex data by defining the first transformed data as in-phase components of complex information and the second transformed data as orthogonal components of the complex information and the complex data is output. Subsequently, an equalizer equalizes the complex data and outputs an equalized complex data a clock-inconsistency compensator compensates A clock-inconsistency between a receiver and a transmitter by using a result of a decision and the equalized complex data, and outputs a compensated complex data. A decision unit decides the compensated complex data, and outputs a result of the decision.

Abstract: A device for comparing the peak value of a periodic voltage signal or a linear combination of periodic voltage signals with a reference voltage includes a reference transconductor element for converting the reference voltage into a reference current, respective transconductor elements for converting each of the periodic voltage signals into respective periodic current signals, a current-comparison node for comparing the respective periodic current signals with the reference current, generating a comparison current as a difference between the sum of the aforesaid periodic current signals and the reference current, a current rectifier supplied with the comparison current, a hold capacitor charged with the output current of the current rectifier, and a discharge-current generator in parallel to the hold capacitor.

Abstract: A main driver amplifier generates first differential signals (Vdp/Vdn) based on pattern data (PAT). A replica driver amplifier generates second differential signals (Vcp/Vcn) based on the pattern data (PAT). Two subtractors generate electric potential difference signals (HP=RP?Vep) and (HN=RN?Ven), respectively. Two sample hold circuits sample the electric potential difference signals (HP and HN),and hold them thereafter, respectively. A comparison unit compares a differential amplitude signal (DA=HHP?HHN) with a predetermined threshold value (VOH). A latch circuit latches an output from the comparison unit. Sampling timings of the two sample hold circuits and a latch timing of the latch circuit, can be adjusted independently.

Abstract: A time constant calibration device includes: a first voltage generating circuit utilizing a first current passing through a capacitive component to generate a first voltage; a second voltage generating circuit utilizing a second current passing through a resistive component to generate a second voltage; and a comparing circuit for comparing the first voltage with the second voltage to generate a comparing signal, wherein the first voltage generating circuit comprises an analog adjusting component for adjusting the first voltage according to the comparing signal until the first voltage is equal to the second voltage, whereby an RC time constant defined by an equivalent capacitance corresponding to the first current passing through the capacitive component and an equivalent impedance corresponding to the second current passing through the resistive component reaches a predetermined value.

Abstract: An impedance buffer has a single comparator with a first input and a second input. A first leg has a first pull-up array in series with a reference resistor. The first input of the single comparator is electrically coupled to a node between the first pull up array and the reference resistor. A second leg has a second pull-up array in series with a pull-down array. The second leg is coupled through a switch to the second input of the single comparator.

Abstract: Disclosed are an input buffer, and more particularly, a technique that is capable of improving the operation speed of the input buffer by improving response speed with respect to an input signal. The input buffer includes a buffer unit that operates when an activation control signal is activated, compares the voltage of an input signal to a preset reference voltage, and outputs the result of the comparison to an output node, a driving unit that performs driving control on an output of the buffer unit, and outputs an output signal, and a pull-down control unit that outputs a pull-down control signal that has a high pulse for a predetermined time when transition of a potential of the input signal occurs.

Abstract: A voltage detector device is disclosed that includes a coarse-range voltage detector and a fine-range voltage detector. The fine-range voltage detector is configured to remain inactive, so that it consumes a relatively small amount of power, while a monitored voltage is outside a first specified range. In response to determining that the monitored voltage is within the first specified range, the coarse-range voltage detector activates the fine-range voltage detector so that it can monitor the voltage. In response to the fine-voltage monitor determining the voltage falls within a second specified range, the fine-range voltage detector provides a signal to a functional module of an electronic device so that the functional module can provide a defined response, such as executing an interrupt routine.

Abstract: A device, comprising a monitoring slicer adapted to repeatedly sample an internal analog signal to provide a sequence of digital outputs indicating a result of a comparison of the level of the internal analog signal to a reference voltage and an operative unit adapted to perform a task of the device and provide a result without using digital outputs from the monitoring slicer.

Abstract: There is provided a bulk bias voltage VBB level detector in a semiconductor memory device capable of improving tWR fail generated at a low temperature by compensating a temperature variance. The VBB level detector includes A bulk bias voltage level detector in a semiconductor memory device, comprising: a voltage divider for generating detection voltage based on an inputted bulk voltage; and a CMOS circuit for generating a output signal having predetermined logic value determined by the detection voltage wherein the voltage divider includes a first transistor having a gate coupled to a ground voltage and a second transistor having a gate coupled to an internal power voltage and a bulk coupled to the inputted bulk voltage.

Abstract: A power integration circuit includes: a first transistor having a control electrode connected to a first voltage source to be supplied with a control signal therefrom, the first transistor being connected between a switch and a ground. A sense resistor has one end connected to the ground. A second transistor has a control electrode connected to the first voltage source to be applied with a control signal therefrom, with the second transistor being connected between the switch and the other end of the sense resistor. The power integration circuit further includes: a comparator for comparing the sense voltage with the reference voltage and delivering a difference between the sense voltage and the reference voltage to a logic circuit.

Abstract: A comparator includes a plurality of switches, a capacitor, an amplifier, and a latch. The switches provide an input signal during a first period and provide a reference signal during a second period. A first switch among the switches is composed of a first transistor. The capacitor receives the input signal during the first period and receives the reference signal during the second period. The amplifier is coupled to the capacitor for receiving a difference voltage between the input signal and the reference signal and amplifies the difference voltage during the second period to generate an amplified result. The determining circuit provides a digital signal according to the amplified result.

Abstract: Power-down mode is activated when equal voltages are detected on a pair of differential inputs. The voltage difference across the differential inputs is equalized by an equalizer and then applied to a multiplier and smoothed and filtered by a low-pass filter to produce an average signal. The average signal is compared to a reference voltage to detect when the voltage difference across the differential inputs is too small. A power-down signal is activated when the average signal is too small. The reference voltage compared can be generated by an equalizer, multiplier, and low-pass filter to match process, temperature, and supply-voltage variations in the primary signal path. The multipliers can be implemented with Gilbert cells. The equalizers can receive control signals to control attenuation of different frequency components.

Abstract: An active termination circuit is used to set the input impedance of a plurality of input terminals. Each of the input terminals is coupled to a supply voltage through at least one PMOS transistor and to ground through at least one NMOS transistor. The impedances of the transistors are controlled by a control circuit that generates a first control signal to set the impedance of another PMOS transistor to be equal to a first predetermined resistance, and generates a second control signal to set the impedance of another NMOS transistor to be equal to a second predetermined resistance. The first control signal is used to control all of the PMOS transistors and the second control signal is used to control all of the NMOS transistors. As a result the PMOS and NMOS transistors coupled to each input terminal have impedances corresponding to the first and second resistances, respectively.