Abstract: A smart vehicle system is disclosed, which relates to technology for increasing efficiency of a vehicle-embedded memory. The smart vehicle system includes a host and a storage device. The host selects any one of a first mode and a second mode according to operation, process or workload of a vehicle, and transmits and receives data through different channels in response to the first mode and the second mode. The storage device stores the data received through different channels in the first core circuit and the second core circuit, or reads the data stored in the first core circuit and the second core circuit. The storage device executes different operations in the first mode and the second mode in a manner that an operation to be executed in the first mode is different from an operation to be executed in the second mode.

Abstract: A method of writing data into a memory device comprising utilizing a pipeline to process write operations of a first plurality of data words addressed to a plurality of memory banks, wherein each of the plurality of memory banks is associated with a counter. The method also comprises writing a second plurality of data words and associated memory addresses into an error buffer, wherein the error buffer is associated with the plurality of memory banks and wherein further each data word of the second plurality of data words is either awaiting write verification associated with a bank from the plurality of memory banks or is to be re-written into a bank from the plurality of memory banks. Further, the method comprises maintaining a count in each of the plurality of counters for a respective number of entries in the error buffer corresponding to a respective memory bank.

Abstract: A storage device includes a main storage and a storage controller to control the main storage. The main storage stores data and includes a plurality of nonvolatile memory devices. The storage controller loads at least one of (a) at least a portion of mapping tables and (b) at least one of a portion of directories to a host memory buffer included in an external host device, based on at least one of a size of the host memory buffer and locality information associated with a data access pattern of the host device. The mapping tables are stored in the nonvolatile memory devices and the mapping tables indicate a mapping relationship between a physical address and a logical address of corresponding ones of the nonvolatile memory devices. The directories store address information of the mapping tables.

Abstract: Various embodiments comprise methods and related apparatuses formed from those methods for placing at least portions of peripheral circuits under a DRAM memory array, where the peripheral circuits are used to control an operation of the DRAM memory array. In an embodiment, a memory apparatus includes a DRAM memory array and at least one peripheral circuit formed under the DRAM memory array, where the at least one peripheral circuit includes at least one circuit type selected from sense amplifiers and sub-word line drivers. Additional apparatuses and methods are also disclosed.

Abstract: Some memory circuitry comprises a stack of multiple tiers individually comprising memory cells individually comprising an elevationally-extending transistor. The tiers individually comprise multiple access lines that individually electrically couple together a row of the memory cells in that individual tier. The tiers individually comprise access-line-driver circuitry comprising an elevationally-extending transistor.

Abstract: A control device of the invention for a semiconductor memory device comprising an interface conforming to JEDEC standard of DDRx-SDRAM or LPDDRx-SDRAM, comprises banks, a read/write control circuit, and a transfer control circuit. Each bank comprises subarrays. Each subarray comprises memory cells arranged along bit lines and word lines. The read/write control circuit controls reading of data from and writing of data to the semiconductor memory device. The transfer control circuit controls data transfer inside the semiconductor memory device and sets to enable an additional transfer command not specified in the JEDEC standard and a transfer command for writing data, read from a transfer source memory cell, to a transfer destination memory cell without passing outside the semiconductor memory device by transmitting a first signal value not used in the JEDEC standard to the semiconductor memory device via at least one signal line of the interface.

Abstract: A Basic Input/Output System (BIOS)/Unified Extensible Firmware Interface (UEFI) on a Self-Service Terminal (SST) loads ATM resources into volatile memory of the SST during a boot of the SST in a predefined order. Each time, during an SST boot, where the order is attempting to be changed; a credential is required to change the predefined order and the credential has to be authenticated before the predefined order is changed during the SST boot.

Abstract: A security system includes a physical unclonable function circuit, a write-in protection circuit, a memory, and a readout decryption circuit. The physical unclonable function circuit provides a plurality of random bit strings. The write-in protection circuit receives a write-in address and original data, and includes an address scrambling unit. The address scrambling unit generates a scrambled address by scrambling a write-in address according to a random bit string provided by the physical unclonable function circuit. The memory stores the storage data corresponding to the original data according to the scrambled address. The readout decryption circuit reads out the storage data from the memory according to the write-in address to derive the original data.

Abstract: In one embodiment, a cache memory includes: a plurality of data banks, each of the plurality of data banks having a plurality of entries each to store a portion of a cache line distributed across the plurality of data banks; and a plurality of tag banks decoupled from the plurality of data banks, wherein a tag for a cache line is to be assigned to one of the plurality of tag banks. Other embodiments are described and claimed.

Abstract: An operation method of a memory device which includes a plurality of memory cells connected to a plurality of word lines includes receiving a first activate command from an external device, receiving at least one operation command from the external device after the first activate command is received, receiving a precharge command after receiving the at least one operation command, and receiving a second activate command from the external device after the precharge command is received. When the at least one operation command does not include a write command, the second activate command is received after a first precharge reference time elapses from a time at which the precharge command is received. When the at least one operation command includes the write command, the second activate command is received after a second precharge reference time elapses from the time at which the precharge command is received.

Abstract: The disclosed embodiments relate to a system that supports dynamic bursts to facilitate frequency-agile communication between a memory controller and a memory device. During operation, the system monitors a reference clock signal received at an interface between the memory device and the memory controller. Upon detecting a frequency change in the reference clock signal from a fullrate to a subrate, the interface operates in a burst mode, wherein data is communicated through bursts separated by intervening low-power intervals during which portions of the interface are powered down.

Abstract: Embodiments of the present disclosure pertain to switch matrix circuit including a data permutation circuit. In one embodiment, the switch matrix comprises a plurality of adjacent switching blocks configured along a first axis, wherein the plurality of adjacent switching blocks each receive data and switch control settings along a second axis. The switch matrix includes a permutation circuit comprising, in each switching block, a plurality of switching stages spanning a plurality of adjacent switching blocks and at least one switching stage that does not span to adjacent switching blocks. The permutation circuit receives data in a first pattern and outputs the data in a second pattern. The data permutation performed by the switching stages is based on the particular switch control settings received in the adjacent switching blocks along the second axis.

Abstract: According to one embodiment, a memory system, comprises a non-volatile memory; a first memory and a second memory; and a memory controller configured to receive a first logical address from a host in a first reading, read a first address conversion table corresponding to the first logical address from the non-volatile memory, and store, in the non-volatile memory, a second address conversion table of a first state stored in the first memory in a case where the first logical address corresponds to a second logical address stored in the second memory.

Abstract: The present disclosure relates to a memory hierarchy for a system-in-package. An example memory hierarchy is connectable to a processor via a memory management unit arranged for translating a virtual address sent by the processor into a physical address. The memory hierarchy has a data cache memory and a memory structure having at least a L1 memory array comprising at least one cluster. The memory structure comprises a first data access controller arranged for managing one or more banks of scratchpad memory of at least one of the clusters of at least the L1 memory array, comprising a data port for receiving at least one physical address and arranged for checking at run-time, for each received physical address, bits of the physical address to see if the physical address is present in the one or more banks of the at least one cluster of at least the L1 memory array.

Abstract: Aspects of the present disclosure provide systems and methods for operating a solid state drive (SSD) using two-level indirection architecture. The SSD receives a command to perform a data operation in a NAND array and a logical address for the data operation. The SSD then converts the logical address to a physical address using a two-stage logical-to-physical (L2P) mapping table that includes a first stage stored in a byte-rewritable memory and a second stage stored in a block-erasable non-volatile memory (NVM). The SSD performs the data operation in the NAND array based on the physical address. The byte-rewritable memory may any byte-rewritable persistent memory. The block-erasable low latency NVM may be a flash memory that has lower latency than NAND array.

Abstract: The present disclosure provides a target row generator. The target row generator includes a plurality of counting modules, a comparing module and a first processing module. Each of the plurality of counting modules is configured to generate a counting record, and includes a reset timer. The reset timer is configured to generate a reset signal to reset a corresponding one of the plurality of counting modules. The comparing module is connected to the plurality of counting modules and is configured to compare a plurality of counting records generated by the plurality of counting modules. The first processing module is connected to the comparing module and is configured to generate a target row record based on a comparison result from the comparing module. The quantity of the plurality of counting records is less than the quantity of the plurality of stressed rows.

Abstract: An apparatus is configured to render graphics content to reduce latency of the graphics content. The apparatus includes a display configured to present graphics content including a first portion corresponding to an area of interest and further including a second portion. The apparatus further includes a fovea estimation engine configured to generate an indication of the area of interest based on scene information related to the graphics content. The apparatus further includes a rendering engine responsive to the fovea estimation engine. The rendering engine is configured to perform a comparison of a first result of an evaluation metric on part of the area of interest with a second result of the evaluation metric with another part of the area of interest. The rendering engine is further configured to render the graphics content using predictive adjustment to reduce latency based on the comparison.

Abstract: A memory system may include: a memory device including a plurality of memory blocks, each memory block including a plurality of pages, each page including a plurality of memory cells operatively coupled to a word line for storing data; and a controller including a memory, the controller being suitable for performing a command operation corresponding to a command received from a host, storing data segments of user data and meta segments of metadata for the its command operation in the memory, storing the data segments in first pages included in a first memory block among the memory blocks, storing the meta segments in second pages included in the first memory block, and storing segment informations for the meta segments, in spare regions of the second pages.

Abstract: A memory device includes a non-volatile memory configured with a block including first and second portions and an address decoder mapping received command addresses to physical addresses of the non-volatile memory. The memory device includes control circuitry maintaining a current status of the first portion and the second portion and implementing an update operation, including responsive to receiving a write command sequence to the block, causing the address decoder to (i) map the write command address to one of the first portion and the second portion, selected in response to the current status and (ii) update the selected one of the first portion and the second portion with the updated information, and upon completion of the updating, changing the current status to indicate that the selected one of the first and second portion is the current area.

Abstract: A semiconductor device may include a multipurpose command latch circuit, a latched control signal generation circuit, and a training control circuit. The multipurpose command latch circuit may be configured to synchronize a multipurpose command with a first division clock signal to generate a first latched multipurpose command. The latched control signal generation circuit may be configured to latch a control signal in synchronization with the first division clock signal to generate a first latched control signal. The training control circuit may be configured to generate a training signal for executing a training operation of a chip selection signal from a first latched multipurpose command and a first latched control signal based on a training flag.

Abstract: An interconnect level is provided on a surface of a substrate that has improved crack stop capability. The interconnect level includes at least one wiring region including an electrically conductive structure embedded in an interconnect dielectric material having a dielectric constant of less than 4.0, and a crack stop region laterally surrounding the wiring region. The crack stop region includes a crack stop dielectric material having a dielectric constant greater than the dielectric constant of the interconnect dielectric material. The crack stop region may be devoid of any metallic structure, or it may contain a metallic structure. The metallic structure in the crack stop region, which is embedded in the crack stop dielectric material, may be composed of a same, or different, electrically conductive metal or metal alloy as the electrically conductive structure embedded in the interconnect dielectric material.

Abstract: A memory system may include: a memory device including a plurality of pages in which data are stored and a plurality of memory blocks which include the pages; and a controller suitable for storing data segments of user data corresponding to a write command received from a host, in the pages included in the memory blocks, generating map segments of map data corresponding to storage of the data segments and lists, and searching and updating the map segments through the lists.

Abstract: A plurality of dynamic decode circuits for decoding a plurality of input signals comprises a decoder that decodes the plurality of input signals to produce a result at a first node, the result is propagated to a second node while an evaluation clock is active by a pair of serially connected transistors consisting of a transistor receiving an evaluation clock at its gate and a transistor receiving the first node at its gate, the plurality of dynamic decode circuits sharing a conditioned node.

Abstract: A processor of an aspect includes a decode unit to decode a matrix multiplication instruction. The matrix multiplication instruction is to indicate a first memory location of a first source matrix, is to indicate a second memory location of a second source matrix, and is to indicate a third memory location where a result matrix is to be stored. The processor also includes an execution unit coupled with the decode unit. The execution unit, in response to the matrix multiplication instruction, is to multiply a portion of the first and second source matrices prior to an interruption, and store a completion progress indicator in response to the interruption. The completion progress indicator to indicate an amount of progress in multiplying the first and second source matrices, and storing corresponding result data to the third memory location, that is to have been completed prior to the interruption.

Abstract: A memory cell and processing array that has a plurality of memory are capable of performing logic functions, including an exclusive OR (XOR) or an exclusive NOR (XNOR) logic function. The memory cell may have a read port in which the digital data stored in the storage cell of the memory cell is isolated from the read bit line.

Abstract: Read stability of a memory is enhanced in low voltage operation mode by selectively boosting a cell supply voltage for a row of memory cells. The boosted voltage results from a capacitive coupling to the word line in that row. The capacitive coupling is implemented by running the metal line of the power supply line for the cell supply voltage and the metal line for the word line adjacent to each other in a common metallization level. The selective voltage boost is controlled in response to operation of a modified memory cell exhibiting a deteriorated write margin. An output of the modified memory cell is compared to a threshold to generate a signal for controlling the selective voltage boost. Word line under-voltage circuitry is further provided to control application of an under-voltage to the word line.

Abstract: A memory system includes: a memory device including a plurality of pages which include a plurality of memory cells coupled to a plurality of word lines and in which data are stored, and a plurality of memory blocks in which the pages are included; and a controller including a memory, and suitable for storing data segments of user data corresponding to a write command received from a host, in pages included in a first memory block and a second memory block among the memory blocks and generating map data corresponding to storage of the data segments by sorting map segments of the map data according to logical informations of the data segments.

Abstract: According to one embodiment, a memory system includes a first memory as a nonvolatile memory storing first data, second data as a translation table for accessing the first data, third data, fourth data as a translation table for accessing the third data, and including two memory cell arrays which are accessible in parallel, a second memory in which the second and fourth data is storable, and which stores a management table for managing information about whether the second and fourth data is stored in the second memory, a controller checking whether the second and fourth data is stored in the second memory based on the management table, a third memory storing an order of executing commands to be issued to the first memory, and a scheduler scheduling the order based on a result of the checking, two of a first command for reading the first data, a second command for reading the second data, a third command for reading the third data and a fourth command for reading the fourth data being executed in parallel in t

Abstract: A test signal transmission apparatus used in a multi-chassis test device is provided. The test signal transmission apparatus includes global buses and test signal transmission modules each including an I/O port coupled to a test controller, a test bus coupled to an in-circuit-tester system and a bridge matrix including an output unit and an input unit. The output unit either routes a first output signal from the I/O port to the test bus, or routes the first output signal to one of the global buses and routes a second output signal from another one of the global buses to the test bus. The input unit either routes a first input signal from the test bus to the I/O port, or routes the first input signal to one of the global buses and routes a second input signal from another one of the global buses to the I/O port.

Abstract: This present invention provides a fast data transfer for a concurrent transfer of multiple ROI areas between an internal memory array and a single memory where each PE can specify the parameter set for the area to be transferred independently from the other PE. For example, for a read transfer, the requests are generated in a way that first the first element of each ROI area is requested from the single memory for each PE before the following elements of each ROI area are requested. After the first element from each ROI area has been received from the single memory in a control processor and has been transferred from the control processor over a bus system to the internal memory array, all elements are in parallel stored to the internal memory array. Then, the second element of each ROI area is requested from the single memory for each PE. The transfer finishes after all elements of each ROI area are transferred to their assigned PEs.

Abstract: A nonvolatile memory module includes at least one nonvolatile memory, at least one nonvolatile memory controller configured to control the nonvolatile memory, at least one dynamic random access memory (DRAM) used as a cache of the at least one nonvolatile memory, data buffers configured to store data exchanged between the at least one DRAM and an external device, and a memory module control device configured to control the nonvolatile memory controller, the at least one DRAM, and the data buffers. The at least one DRAM stores a tag corresponding to cache data and compares the stored tag with input tag information to determine whether to output the cache data.

Abstract: An architecture for improved memory access in asymmetric memories provides a set of shared row buffers that may be freely allocated between slow and fast memory banks of the asymmetric memory. This permits allocation of row buffers dynamically between the slow and fast memory banks to improve execution speeds and also permits a lightweight memory swap procedure for moving data between the slow and fast memory banks with low processor and memory channel overheads.

Abstract: An electronic system includes: a processor configured to access operation data; a local cache memory, coupled to the processor, configured to store a limited amount of the operation data; a memory controller, coupled to the local cache memory, configured to maintain a flow of the operation data; and a memory subsystem, coupled to the memory controller, including: a first tier memory configured to store the operation data, with critical timing, by a fast control bus, and a second tier memory configured to store the operation data with non-critical timing, by a reduced performance control bus.

Abstract: A memory system may include a memory device including a plurality of memory blocks each memory block including a plurality of pages, and a controller suitable for storing data in a first memory block of the memory blocks, generating map data for the stored data in the first memory block by sorting map segments of the map data based on logical information of the data, and storing the map data in a second memory block of the memory blocks.

Abstract: A system includes a plurality of memory classes and a set of one or more processing units coupled to the plurality of memory classes. The system further includes a data migration controller to select a traffic rate as a maximum traffic rate for transferring data between the plurality of memory classes based on a net benefit metric associated with the traffic rate, and to enforce the maximum traffic rate for transferring data between the plurality of memory classes.

Abstract: A separate distributed buffer cache system may be implemented for a storage client of a distributed storage system. Storage I/O requests may be sent from a storage client to one or more buffer cache nodes in a distributed buffer cache system that maintain portions of an in-memory buffer cache to which the requests pertain. The distributed buffer cache system may send the write requests on to the distributed storage system to be completed, and in response to receiving acknowledgements from the storage system, sending a completion acknowledgement back to the storage client. Buffer cache nodes may update buffer cache entries for received requests such that they are not available for reads until complete at the distributed storage system. For read requests where the buffer cache entries at the buffer cache node are invalid, valid data may be obtained from the distributed storage system and sent to the storage client.

Abstract: Various techniques are provided to implement a logical memory in programmable logic devices (PLDs) having embedded block RAMs (EBRs). For example, a computer-implemented method includes determining a main area of a logical memory that can be fully mapped to a first one or more EBRs configured in a first depth-width configuration, mapping the main area to the first one or more EBRs, and mapping the remainder of the logical memory to a second one or more EBRs configured in a second or more depth-width configurations. The mapping of the remainder of the logical memory may be performed hierarchically by a recursive process, in some embodiments. The depth-width configurations and the corresponding mapping may be selected according to an efficiency metric, for example. Other embodiments include a system comprising a PLD and a configuration memory storing configuration data generated by such a method, and a PLD configured with such configuration data.

Abstract: A memory module includes a nonvolatile memory device and a volatile memory device connected to a first data channel through a first input/output port and to a second data channel through a second input/output port. The volatile memory device activates one of the first and second input/output ports based on an operation mode. The memory module includes a registering clock driver that transmits a first control signal for data exchange through the first input/output port and a second control signal for data exchange through the second input/output port, to the volatile memory device. A memory controller of the memory module generates the second control signal, exchanges data with the volatile memory device through the second data channel, and controls the nonvolatile memory device. The memory controller detects a request from a host or a power status and generates the second control signal based on the detection result.

Abstract: A stacked semiconductor apparatus and method of fabricating same are disclosed. The apparatus includes upper and lower semiconductor devices having a similar pattern of connection elements. When stacked connected the resulting plurality of semiconductor devices includes a serial connection path traversing the stack, and may also include parallel connection paths, back-side mounted large components, and vertical thermal conduits.

Abstract: A semiconductor apparatus may include: a data storage group including first to eight data storage areas; a first channel select pad configured to transmit a first channel select signal to the first and third data storage areas; a second channel select pad configured to transmit a second channel select signal to the second and fourth data storage areas; a third channel select pad configured to transmit the first channel select signal to the sixth and eighth data storage areas; a fourth channel select pad configured to transmit the second channel select signal to the fifth and seventh data storage areas; a first clock enable pad configured to transmit a first clock enable signal to the first and third data storage areas; a second clock enable pad configured to transmit a second clock enable signal to the second and fourth data storage areas; a third clock enable pad configured to transmit the first clock enable signal to the fifth and seventh data storage areas; and a fourth clock enable pad configured to trans

Abstract: In order to enable an improvement in the access performance of a storage, a storage includes first and second storage devices respectively including first and second storage units to and from each of which data can be written and read, the speed of the first storage device is higher than or equal to that of the second storage device, the first storage device further includes a first storage area for storing management information for access control and management of the second storage unit, the second storage device further includes a second storage area for storing management information for access control and management of the second storage unit, and the storage includes an access control unit which retrieves the management information relating to the second storage unit and used for access to the second storage unit from the first storage area of the first storage device, and retrieves the management information relating to the second storage unit from the second storage area of the second storage device

Abstract: Various implementations described herein are directed to an integrated circuit for address decoding. The integrated circuit may include an input circuit configured to provide an encoded address via multiple address lines. The integrated circuit may include an address decoding circuit configured to directly translate the encoded address provided via the multiple address lines. The address decoding circuit may include multiple decoding blocks with each block having a first stage coupled to a second stage. The first stage of each block may include a first number of decoding transistors configured to decode first address bit values from the multiple address lines. The second stage of each block may include a second number of decoding transistors configured to decode second address data bit values from the multiple address lines. The integrated circuit may include an output circuit configured to provide a decoded address to a wordline driver circuit in memory.

Abstract: A recycling method for a solid state drive is disclosed. The method includes selecting a logical block for recycle wherein the logical block includes a plurality of pages across a plurality of flash dies. The method also includes retrieving an address map index record associated with the logical block selected for recycle. For each particular address map index stored in the address map index record, the recycling method retrieves a set of address map entries referenced by the particular address map index, determines whether any page in the logical block is referenced by the set of address map entries, and if at least one page in the logical block is referenced by the set of address map entries, the method writes the at least one page to a different logical block. The method further includes erasing the plurality of pages in the logical block.

Abstract: A semiconductor memory may include: a storage unit suitable for storing a minimum operation interval between row command operations, a detection unit suitable for detecting whether row command signals inputted for the row command operations are activated at the minimum operation interval, a latching unit suitable for generating flag signals by latching the row command signals, and a shifting unit suitable for shifting the flag signals based on the minimum operation interval in response to an output signal of the detection unit, and generating an internal row command signals.

Abstract: Methods and apparatus relating to techniques for Electromagnetic Interference (EMI) mitigation on high-speed lanes using false stall are described. In one embodiment, protocol logic determines whether to perform a false stall operation on a lane in response to a determination that no data is to be sent over the lane and that data is being transmitted over the lane. The false stall operation includes sending one or more training symbols (e.g., immediately) after an End Of Burst (EOB) signal over the lane, instead of allowing the lane to stall. Other embodiments are also disclosed.

Abstract: A nonvolatile memory device includes a first memory block connected to first word lines, a second memory block arranged in a direction perpendicular to the first memory block and is connected to second word lines, first pass transistors for enabling the first word lines, and second pass transistors for enabling the second word lines. The first and second pass transistors are arranged in a horizontal direction with respect to the first and second memory blocks.

Abstract: Interaction of a user with external data sources related to the research and analysis of terms and content for improved indexing by search engines may be provided. One or more elements of the content may be used to return an analysis of those elements to the user within the experience of a word processing application environment. Systems and methods also may be provided for determining the relative competition of a term or terms to quantitatively derive the number of pages within a corpus that may be actively engaged to improve the indexing of the pages by information retrieval systems, such as search engines. Systems and methods may be further provided for determining the relative ranking of a term or terms based on the frequency and placement of the term or terms within a structured page.

Abstract: Techniques for reducing latency in address decoding are described. According to one approach, a method of operating an addressing circuit comprises partitioning range of encoded addresses into a first and second subset of encoded addresses, sending a first encoded address to a address decode circuit from a controller. In response to determining that the first encoded address is contained in the first subset, decoding the first encoded address in a first duration. In response to determining that the first encoded address is contained in the second subset, decoding the first encoded address in a second duration which is longer than the first duration and simultaneously sending a halt signal to the controller to stop sending subsequent encoded addresses for decoding for the entirety of the second duration.

Abstract: A semiconductor memory disclosed in this disclosure includes first and second memory cell arrays, a first main data line that transfers the read data read from the first memory cell array, a second main data line that transfers the read data read from the second memory cell array, a main amplifier coupled to the second main data line, and a repeater circuit coupled to the first main data line and the second main data line.

Abstract: Systems and methods for management of physiological data, for example data obtained from monitoring an electrocardiogram signal of a patient. In one example use, digital data is obtained and episodes of arrhythmias are detected. Snapshots of the digitized ECG signal may be stored for later physician review. One or more techniques may be used to avoid recording of redundant data, while ensuring that at least a minimum number of episodes of each detected arrhythmia can be stored. The system may automatically tailor its data collection to the cardiac characteristics of a particular patient. In one technique, memory is allocated to include for each detectable arrhythmia a memory segment designated to receive ECG snapshots representing only the respective arrhythmia. A shared memory pool may receive additional snapshots of as the designated memory segments fill.