Abstract: A word line driver circuit for providing a suppressed word line voltage includes a switch configured to selectively load a word line to a suppressed word line voltage node and a word line charging circuit coupled between a high power supply node and the suppressed word line voltage node. The word line charging circuit includes a first transistor device responsive to a control pulse for charging the suppressed word line voltage node to a suppressed word line voltage and a second transistor device for maintaining the suppressed word line voltage.

Abstract: A digital memory system includes a memory controller having a driver configured for generating a digital signal. A memory module has a receiver in communication with the driver. The driver is configured for selectively directing the digital signal to the receiver of the memory module. A voltage control module is configured for determining a traffic intensity at which the digital signal is directed to the receiver and dynamically adjusting the reference voltage as a function of the traffic intensity at which the digital signal is directed to the receiver.

Abstract: A spatial disturbance that occurs when an access is concentrated in a specific memory area in a volatile semiconductor memory like DRAM is properly solved by a memory controller. The memory controller includes a concentration access detection part generating a concentration access detection signal when an address for accessing a specific memory area among memory areas of volatile semiconductor memory is concentrically received. In the case that the concentration access detection signal is generated, the memory controller includes a controller for easing or preventing corruption of data which memory cells of the specific memory area and/or memory cells of memory areas adjacent to the specific memory area hold.

Abstract: For example, a semiconductor device includes latch circuits, whose input nodes are connected to an input selection circuit and whose output nodes are connected to an output selection circuit; and a control circuit, which controls the input selection circuit and the output selection circuit. The control circuit includes a shift register to generate an input pointer signal and a binary counter to generate an output pointer signal. The input selection circuit selects one of the latch circuits on the basis of a value of the input pointer signal. The output selection circuit selects one of the latch circuits on the basis of a value of the output pointer signal. Therefore, it is possible to prevent a hazard from occurring in the input selection circuit, as well as to reduce the number of signal lines that transmit the output pointer signal.

Abstract: A system and method that includes a memory die, residing on a stacked memory, which is organized into a plurality of mats that include data. The system and method also includes an additional memory die, residing on the stacked memory, that is organized into an additional plurality of mats and connected to the memory die by a Through Silicon Vias (TSVs), the data to be transmitted along the TSVs.

Abstract: A memory device includes: a plurality of word lines and bit lines specifying addresses to be accessed; and a plurality of memory cells of consecutive addresses arranged to correspond to each of the word lines. The plurality of memory cells of the consecutive addresses are accessible in parallel by the plurality of bit lines each corresponding to one of the memory cells. Among the plurality of word lines, a first word line and a second word line that specifies an address next to that of the first word line have an overlapping address range, and a first memory cell connected to the first word line and a second memory cell connected to the second word line are assigned in dual fashion to a same address.

Abstract: A memory includes memory cells, data lines, block select lines, and selection circuitry. The data lines provide data to and from the memory cells and may be grouped into blocks. Each block includes data lines. Each of the block select lines is associated with a respective one of the blocks. The selection circuitry is select a block in response to a respective block select line and the memory performs a memory operation using the selected bit line block.

Abstract: An address delay circuit of a semiconductor memory apparatus includes a first group control pulse generation unit configured to generate a first control pulse after input of a first group column address strobe pulse and passage of a time corresponding to a first set multiple of one cycle of a clock, a second group control pulse generation unit configured to generate a second control pulse after input of a second group column strobe address pulse and passage of a time corresponding to a second set multiple of the one cycle of the clock, a first address storage unit configured to receive and store a first group external address in response to the first control pulse, and output a first group internal address, and a second address storage unit configured to receive and store a second group external address in response to the second control pulse, and output a second group internal address.

Abstract: A non-volatile storage system reduces program disturb in a set of non-volatile storage elements by programming using selected bit line patterns which increase the clamped boosting potential of an inhibited channel to avoid program disturb. First, second and third sets of non-volatile storage elements are programmed in separate sequences, one after another, so that all program-verify operations occur for the first set, then for the second set, and then for the third set. Each non-volatile storage element in a set is separated from the next closest non-volatile storage element in the set at least two other non-volatile storage elements in the set.

Abstract: Integrated circuits may include configurable-port memory cells. The configurable-port memory cells may be operable in single-port mode and multiport mode. Each configurable-port memory cell may be coupled to first and second pairs of data lines. The configurable-port memory cell may include a first latching circuit having a first data storage node and a second latching circuit having a second data storage node. The first latching circuit may be coupled to the first pair of data lines through a first set of access transistors, whereas the second latching circuit may be coupled to the second pair of data lines through a second set of access transistors. An additional transistor may be coupled between the first and second data storage nodes. The configurable-port memory cell is configured in the single-port mode if the additional transistor is turned off and is configured in the dual-port mode if the additional transistor is turned on.

Abstract: Subject matter disclosed herein relates to accessing memory, and more particularly to operation of a partitioned bitline.

Abstract: Various embodiments include apparatus, systems, and methods having multiple dice arranged in a stack in which a defective cell may be replaced by a spare cell on the same die or a different die. Other embodiments are described.

Abstract: An access method for a DRAM is provided. A row address is partitioned into a first portion and a second portion. The first portion of the row address via an address bus and a first active command via a command bus are provided to the DRAM. The second portion of the row address via the address bus and a second active command via the command bus are provided to the DRAM after the first active command is provided. A column address via the address bus and an access command via the command bus are provided to the DRAM after the second active command is provided. The address bus is formed by a plurality of address lines, and a quantity of the address lines is smaller than the number of bits of the row address, and the access command is a read command or a write command.

Abstract: A semiconductor memory device includes a cell array including a plurality of regions accessed by first addresses, where the plurality of regions including at least two groups of regions having respectively different memory characteristics. The device further includes a nonvolatile array for nonvolatile storage of group information indicative of which of the least two groups each of the plurality of regions belongs.

Abstract: The present invention provides a novel wiring method for LR-DIMM of VLP type that conforms to LR-DIMM technology. The LR-DIMM comprises a plurality of DRAMs mounted on a board, two connectors mounted on the board for receiving data, and a buffer device mounted on the board for redriving data applied to the two connectors to supply the data to the plurality of DRAMs. The buffer device is located near the center of the board on which the two connectors are arranged at both ends thereof, and supplies data from each connector to DRAMs arranged on the opposite side to the connector.

Abstract: A memory includes an array of memory cells that form rows and columns. The rows include memory cell pairs. The memory cells may include two cross-coupled inverters and two pass-devices that couple to alternate sides of the cross-coupled inverters. For a read operation, a wordline drive circuit selects one memory cell of the pair, the selected memory cell being an addressed memory cell while the remaining cell is an unaddressed memory cell. In response to a wordline enable signal, a pass gate in the addressed memory cell couples the addressed memory cell via a complement bitline to an evaluation gate that resolves the data from the read operation. During the read operation, the unaddressed memory cell couples via another pass gate to a true bitline that terminates without an evaluation gate to conserve energy.

Abstract: A non-volatile storage system reduces program disturb in a set of non-volatile storage elements by programming using selected bit line patterns which increase the clamped boosting potential of an inhibited channel to avoid program disturb. Alternate pairs of adjacent bit lines are grouped into first and second sets. Non-volatile storage elements of the first set of pairs are subject to program pulses and verify operations in each of a first number of iterations, after which non-volatile storage elements of the second set of pairs is subject to program pulses and verify operations in each of a second number of iterations.

Abstract: The present invention is directed to systems and methods for improving access to non-volatile solid-state storage systems. Embodiments described herein provide a physical chunk number (PCN), or a physical page number (PPN), by which a controller can access the next available chunks (or pages) in a programming sequence optimized by concurrency. By incrementing the PCN, the controller can program consecutive chunks in the optimized programming sequence. In one embodiment, the programming sequence is determined at the time of initial configuration and the sequence seeks to synchronize data programming and data sending operations in subcomponents of the storage system to minimize contention and wait time. In one embodiment, the PCN includes an index portion to a superblock table with entries that reference specific blocks within the subcomponents in a sequence that mirrors the optimized programming sequence, and a local address portion that references a particular chunk to be programmed or read.

Abstract: A word line driver circuit and corresponding methods are disclosed. An apparatus, comprising a decoder circuit coupled to receive address inputs, and having a decoder output; and a word line clock gating circuit coupled to the decoder output and to a word line clock signal, configured to selectively output a word line signal responsive to an edge on the word line clock signal; wherein the address inputs have a set up time requirement relative to the edge of the word line clock signal, and the address inputs have a zero or less hold time requirement relative to the edge of the word line clock signal. Methods for providing a word line signal from a word line driver are disclosed.

Abstract: Disclosed herein is a device that includes: a set of address terminals supplied with a set of address signals, each of the address signals being changed in logic level; memory mats to which address ranges are allocated, respectively, the address ranges being different from each other, each of the memory mats including memory cells; and decoder units each provided correspondingly to corresponding memory mat. Each of the decoder units includes a set of first input nodes and a set of second input nodes, the set of first input nodes of each of the decoder units being coupled to the set of address terminals to receive the set of address signals, the set of second input nodes of each of the decoder units being coupled to receive an associated one of sets of control signals, each of the control signals being fixed in logic level.

Abstract: An integrated circuit includes a normal data storage unit configured to store normal data and output the stored normal data in response to a write command, a read command, and an address signal in a normal operation mode, a test data storage unit configured to store the address signal as test data in response to the write command in a test operation mode, and output the stored test data in response to the read command, and a connection selection unit configured to selectively connect a data input/output terminal of the normal data storage unit or a data output terminal of the test data storage unit to a global line based on whether the integrated circuit is in a first or second one of the normal operation mode and the test operation mode, respectively.

Abstract: A circular queue implementing a scheme for prioritized reads is disclosed. In one embodiment, a circular queue (or buffer) includes a number of storage locations each configured to store a data value. A multiplexer tree is coupled between the storage locations and a read port. A priority circuit is configured to generate and provide selection signals to each multiplexer of the multiplexer tree, based on a priority scheme. Based on the states of the selection signals, one of the storage locations is coupled to the read port via the multiplexers of the multiplexer tree.

Abstract: Address transforming methods are provided. The methods may include generating a power-up signal when a semiconductor memory device is powered-up. The methods may further include generating a randomized output signal in response to the power-up signal. The methods may additionally include transforming bits of a first address in response to the randomized output signal to generate a second address.

Abstract: A semiconductor device includes a first operation circuit configured to generate addition data by adding a column address and a page address and output a remainder obtained by dividing the addition data by a set value as seed data, a mask data output circuit configured to output mask data corresponding to the respective seed data, and a second operation circuit configured to generate random data by performing a logic operation on the mask data and program data corresponding to the column and page addresses.

Abstract: Disclosed herein is a semiconductor device that includes an access control circuit generating an internal command based on a verification result signal and an external command. The external command indicates at least one of a first command that enables the access control circuit to access a first circuit and a second command that enables the access control circuit not to access the first circuit or enables the access control circuit to maintain a current state of the first circuit. The access control circuit, when the verification result signal indicates a first logic level, generates the internal command based on the external command. The access control circuit, when the verification result signal indicates a second logic level, generates the internal command that corresponds to a second command even if the external command indicates a first command.

Abstract: In a particular embodiment, a method includes discharging a first dynamic node at a first discharge circuit of a first dynamic circuit structure in response to receiving an asserted discharge signal. The first dynamic circuit structure includes the first dynamic node at a first voltage level and a first keeper circuit that is disabled when the asserted discharge signal is received. The asserted discharge signal has a second voltage level that is different from the first voltage level. A second keeper circuit of a second dynamic circuit structure is enabled responsive to discharging the first dynamic node to maintain a second dynamic node of the second dynamic circuit structure at the first voltage level.

Abstract: A semiconductor apparatus includes an individual chip designating code setting block configured to generate a plurality of individual chip designating codes which have different code values or at least two of which have the same code value, in response to a plurality of chip fuse signals; and an individual chip activation block configured to compare the plurality of individual chip designating codes with chip selection address in response to the plurality of chip fuse signals, and enable one of a plurality of individual chip activation signals based on a result of the comparison.

Abstract: A non-volatile memory and method for controlling the same prevents a faulty operation from being generated in a read operation, resulting in increase in operation reliability. The non-volatile memory device includes a cell array configured to include a plurality of unit cells in which a read or write operation of data is achieved in a unit cell in response to a variation of resistance, a reference cell array configured to include a plurality of reference cells, each of which has the same structure as that of the unit cell, a global reference current generation circuit configured to generate a global reference current corresponding to a position of the reference cell so as to verify data stored in the reference cell array, and a sense-amplifier configured to compare a current flowing in the reference cell array with the global reference current during a write verification operation of the reference cell array, and thus sense data.

Abstract: A semiconductor memory apparatus includes a first data input/output line configured to transmit data from a first memory bank; a second data input/output line configured to transmit the data from the first memory bank; a first data output section configured to align and output data transmitted through the first data input/output line based on an input/output mode; and a second data output section configured to align and output either data transmitted through the first input/output line or the second data input/output line based on the input/output mode and an address signal.

Abstract: A row address decoder includes a first main word line decoding unit decoding first and second row addresses to generate first to fourth main decoding signals. When a data storage test is performed, the first to fourth main decoding signals are enabled at first to fourth timings, respectively. The row address decoder also includes a second main word line decoding unit decoding third and fourth row addresses to generate fifth to eighth main decoding signals. When a data storage test is performed, the fifth to eight to main decoding signals are enabled at first to fourth timings, respectively. A main word line enable signal generating unit decodes the first to fourth main decoding signals and the fifth to eighth main decoding signals to generate first to sixteenth main word line enable signals that are enabled at different times.

Abstract: Non-intrusive techniques have been developed to dynamically and selectively alter address translations performed by, or for, a processor. For example, in some embodiments, a memory management unit is configured to map from effective addresses in respective effective (or virtual) address spaces to physical addresses in the memory, wherein the mappings performed by the memory management unit are based on address translation entries of an address translation table. For a subset of less than all processes, entry selection logic selects from amongst plural alternative mappings coded in respective ones of the address translation entries. For at least some effective addresses mapped for a particular process of the subset, selection of a particular address translation entry is based on an externally sourced value. In some embodiments, only a subset of effective addresses mapped for the particular process are subject to dynamic runtime alteration of the address translation entry selection.

Abstract: A semiconductor memory device includes a bank including a first cell region and a second cell region, an active signal generation unit configured to generate a first row active signal and a second row active signal having different activation periods from each other in response to a refresh command, and an address counting unit configured to count the refresh command and generate a row address, wherein a word line of the first cell region designated by the row address is activated when the first row active signal is activated, and a word line of the second cell region designated by the row address is activated when the second row active signal is activated.

Abstract: A multi-port memory array is disclosed. The memory array includes a plurality of memory subblocks and an output network. Each memory subblock includes a plurality of single-read-port memory cells. The output network is configured to redirect information read for a first read port to a second read port on a condition that an equivalence signal indicates that read addresses for the first read port and the second read port are the same. The latching and multiplexing operation may be integrated. The memory cells may be 6-transistor synchronous random access memory (SRAM) cells, 8-transistor SRAM cells, or any type of memory cells.

Abstract: A provided memory device is compatible with a mono-rank or multi-ranks. A plurality of memory layers are stacked in the memory device. The memory device receives an address signal and chip select signals in response to a chip identification signal and a mode signal used to determine a mono-rank or multi-ranks. The plurality of memory layers operate as the mono-rank accessed by the address signal, or operate as the multi-ranks accessed by the chip select signals.

Abstract: When an I/O number is 8 bit, a semiconductor device includes a first memory mat that is selected when X13 is (0) and X11 and X12 are (0, 0), a second memory mat that is selected when X13 is (1) and X11 and X12 are (0, 0), and a third memory mat that is selected irrespective of a value of X13 when X11 and X12 are (0, 0). When the I/O number is 16 bit, X13 is ignored, and the first to third memory mats are selected when X11 and X12 are (0, 0). In this manner, because the third memory mat is shared between so-called upper side and lower side, control is prevented from becoming complicated and an area is prevented from increasing.

Abstract: A memory bank includes memory cells and an additional cell to determine an operating voltage of the memory bank. The additional cell has an operating margin that is less than a corresponding operating margin of the other memory cells in the memory bank.

Abstract: A memory integrated circuit has control circuitry that accesses memory cells of the memory integrated circuit. The control circuitry is responsive to commands including a first command and a second command. The first command specifies a high order set of address bits. The second command specifies a low order set of address bits. The high order set of address bits and the low order set of address bits constitute a complete access address of the memory integrated circuit. The first command and the second command have different in command codes.

Abstract: A semiconductor memory has a memory cell array having a plurality of real word lines, a plurality of redundant word lines, a plurality of bit lines crossing with the real and redundant word lines, a plurality of memory cells provided at crossing section of the real and redundant word lines and the bit lines, and a row selection circuit for selecting the real word line or the redundant word line in accordance with a row address being supplied. The row selection circuit selects the real word line or the redundant word line at an ordinary operation, and multi-selects the redundant word lines at a first test mode.

Abstract: A non-volatile memory storage device has a non-volatile memory, e.g., a flash memory, and a controller coupled to the non-volatile memory. The controller comprises a plurality of control circuits and an arbitration circuit. Each control circuit is configured to generate a request to update the chip-enable (CE) signals for non-volatile memory, and the arbitration circuit is configured to determine when the requests are acknowledged. The arbitration circuit generates acknowledge signals to the control circuits when all of the requests of the control circuits have been received by the arbitration circuit. The CE signals for non-volatile memory are updated when requests are acknowledged.

Abstract: Systems (100) and methods (600) for reading data from a memory device (106). The methods involve (606) receiving first read request signals (118, 120, 122, 126, 128) for first data stored in the memory device. In response to the first read request signals, (608) retrieving a first page of data from a cell array (268) of the memory device. The methods also involve (616) receiving second read request signals for second data stored in the memory device. (618) Next, a determination is made as to whether at least a portion of a memory address for the second data is the same as at least a respective portion of a memory address for the first data. (622) If it is determined that the respective portions of the memory addresses are the same, then a read access to the cell array is disabled.

Abstract: The present invention discloses a multi-chip module with master-slave analog signal transmission function. The multi-chip module comprises: a master chip having a first setting input pin for receiving an analog setting signal to generate an analog setting in the master chip, and the master chip duplicating the analog setting to output a first analog output; and a first slave chip for receiving the first analog output from the master chip to generate an internal setting of the first slave chip.

Abstract: Various embodiments include apparatus, systems, and methods having multiple dice arranged in a stack in which a defective cell may be replaced by a spare cell on the same die or a different die. Other embodiments are described.

Abstract: A microcomputer includes a CPU, a protection information storage configured to store memory protection information specifying an access permission or prohibited state to a memory space by a program executed by the CPU, a memory access control apparatus configured to determine whether or not to allow a memory access request from the CPU according to the memory protection information and a reset apparatus configured to invalidate the memory protection information stored in the protection information storage according to a reset request signal output from the CPU.

Abstract: A semiconductor memory device includes a random address generation unit configured to receive a multi-bit source address and generate a multi-bit random address and a signal mixing unit configured to mix the multi-bit random address with a data, wherein the random address generation unit has a plurality of transmission lines configured to electrically connect the plurality of input terminals respectively corresponding to bits of the source address and the plurality of output terminals respectively corresponding to bits of the random address in one-to-one correspondence regardless of an order of the bits of the source address.

Abstract: A semiconductor device includes a first bit line section coupled to a first cell string, a second bit line section coupled to a second cell string, a page buffer coupled to the first bit line section and a switching circuit formed between the first bit line section and the second bit line section, wherein the switching circuit couples the first bit line section to second bit line section in response to a select signal.

Abstract: A semiconductor memory segment includes a first memory bank having a first tracking cell disposed in a first tracking column. A second memory bank includes a second tracking cell disposed in a second tracking column. A first tracking circuit is coupled to the first and second tracking cells and is configured to output a first signal to memory control circuitry when the first and second tracking cells are accessed. The memory control circuitry is configured to set a clock based on the first signal.

Abstract: In a non-volatile memory storage system such as a flash EEPROM system, a controller switches the manner in which data sectors are mapped into blocks and metablocks of the memory in response to host programming and controller data consolidation patterns, in order to improve performance and reduce wear. Data are programmed into the memory with different degrees of parallelism.

Abstract: A data transfer circuit has a reduced number of lines for transferring a training pattern used in a read training for high speed operation, by removing a register for temporarily storing the training pattern, and a semiconductor memory device including the data transfer circuit. The data transfer circuit includes a latch unit and a buffer unit. The latch unit latches one bit of a training pattern data input together with a training pattern load command whenever the training pattern load command is input. The buffer unit loads a plurality of bits latched in the latch unit, including the one bit of training pattern data, in response to a strobe signal.

Abstract: A semiconductor device is capable of reducing the coupling capacitance between adjacent bit lines by forming an air-gap at an opposite side of a one side contact when forming a buried bit line or increasing a thickness of an insulating layer, thereby improving characteristics of the semiconductor devices. The semiconductor device includes a plurality of line patterns including one side contacts, a bit line buried in a lower portion between the line patterns, a bit line junction region formed within each of the line patterns at one side of the bit line, and an air-gap formed between the other side of the bit line and each of the line patterns.

Abstract: An integrated circuit includes a global I/O line (GIO) for transmitting read data and write data between a peripheral region and a core region when a read/write operation is activated, and a test circuit for transmitting/receiving test data through the global I/O line to test the integrated circuit, when a test operation is activated.