Abstract: A clock distribution and control system (10) includes one counter (30) in a clock generation domain and another counter (40) in a phase-delayed clock domain. The phase-delayed domain counter (40) output is combined with a programmable offset value chosen based on the phase delay of the clock distribution system. The result is used to insure that communication between logic in the clock generation clock domain and logic in the phase-delayed clock domain occurs deterministically on the correct clock edge for a range of clock frequencies.

Abstract: A method and apparatus for reducing unwanted harmonics in direct digital synthesizer (DDS) output. The method comprises the steps of providing a set of k phase-shifted clock signals, examining, in succession, each DDS accumulator state, and determining whether the DDS accumulator state has a defined transition-state. For each DDS accumulator state having a defined transition-state, an interpolation is performed based upon the value of the preceding DDS accumulator state, an element of the set of phase-shifted clock signals is selected based upon the interpolation, and the most significant bit (MSB) is repositioned using the selected element of the phase-shifted clock signals. The apparatus comprises means for providing a set of k phase-shifted clock signals, means for examining, in succession, each DDS accumulator state, and means for determining whether the DDS accumulator state has a defined transition-state.

Abstract: Systems for controlling the frequency of the output signal of a controllable oscillator in a frequency synthesizer are provided. One such system comprises a controllable oscillator and a frequency control circuit. The controllable oscillator is configured to generate an output signal that has a predefined frequency. The controllable oscillator is also configured with a plurality of operational states that are controlled by the frequency control circuit. Each operational state of the controllable oscillator defines a distinct frequency for the output signal of the controllable oscillator. The frequency control circuit receives the output signal of the controllable oscillator and determines the distinct frequency for the output signal that best approximates the predefined frequency.

Abstract: The invention is a method and demodulator which detects periodic synchronization signals. The method of the invention includes multiplexing orthogonal signals in a wireless transmission into a signal stream; applying the signal stream to a synchronization signal detector which produces an output signal including detection of a unique code representing the synchronization signals within the signal stream; demultiplexing the output signal into orthogonal signals; calculating a function of the demultiplexed orthogonal signals and combining the function of each of the orthogonal signals into a combined output signal; averaging the combined output signal over a time period during which the synchronization signals repeat to produce an averaged signal; detecting peaks in the averaged signal; and synchronizing a demodulator in response to the peaks which demodulates the wireless transmission.

Abstract: There is provided a method of detecting a block sync signal in which a sync signal and code sequence can be distinguished from each other to recognize the head of a block composed of a plurality of code words at the time of data reading or reception. A sync word detector (10) is supplied with a window signal Sync_window generated based on a parity OK signal supplied from a parity check circuit (12) and indicating a period between the sync word included in signal read from the medium (1) and the ID information, and detects the sync word as to a bit string detected by a PRML Viterbi detector (6) with the use of the Sync_window signal.

Abstract: A method and apparatus for plesiochronous synchronization of an integer N plurality of subscriber networks to a hub network. Each subscriber network including a sub's clock, and the hub network includes a hub's clock.

Abstract: A phase detector customized for Clock Synthesis Unit (CSU) is disclosed. The phase detector improves jitter performance by providing minimal activity on VCO control lines and pushing ripple frequency to one octave higher, while maintaining wide linear characteristic. Moreover, it provides a frequency-scalable circuit that unlike a conventional phase-and-frequency detector (PFD), does not rely on asynchronous elements.

Abstract: An improvement for a phasor fragmentation engine and method, whereby a phasor flipping algorithm is applied when determining fragment phasors for a non-constant envelope modulation signal (e.g. OFDM). The phasor flipping algorithm avoids sharp phase transitions for the fragment phasors, which cause an increase in bandwidth, by performing a comparison of the phasor angle separation between the prior and current time samples. This comparison corresponds to a determination of whether the modulation signal V has passed near or through zero.

Abstract: In a security system, a method and apparatus for two-way frequency hopping communications between the control panel and each peripheral device which maintains channel synchronization through the assignment of fixed beacon frequencies for the transmission of synchronizing data. The use of frequency hopping provides high immunity to jamming and interference, reduced occurrence of multi-path phenomena, and allows for transmissions at a much higher output power than conventional fixed-frequency communications, to thus increase the effective range of the peripheral devices while providing effective and reliable two-way communications between the control panel and the peripheral devices. The invention also provides a large number of channels, which allows for actuators such as sirens, strobes and line seizing devices to be wireless in addition to sensors.

Abstract: A method and apparatus provide efficient synchronization recovery at the receiver end for a digital transmission system. At the receiving end, a digital signal is received including a transmitted data portion and a guard period. A signal envelope for the received digital signal is determined, and the signal envelope is filtered to find the center of the guard period, which provides a time reference for the received digital signal. Embodiments of the present invention described herein may be used for optimal operation of a digital transmission system by efficiently recovering synchronization from a received digital signal during noisy conditions without being dependent on signal shape or requiring complicated threshold calculations.

Abstract: A method for providing a message-time-ordering facility is disclosed. The method comprises initiating the message-timer ordering facility for a message at a sender system. Initiating includes setting a delay variable to zero. The message is sent to a receiver system in response to initiating the message-time-ordering facility. Sending the message includes marking the message with a first departure time-stamp responsive to a sender system clock and transmitting the message to the receiver system. The message is received at the at the receiver system, receiving includes delaying the processing of the message until the time on a receiver system clock is greater than the first departure time-stamp and recording a time associated with the delaying the processing of the message in the delay variable. A response to the message is sent to the sender system in response to receiving the message.

Abstract: Briefly, in accordance with one embodiment of the invention, a verifier and a method for verifying synchronization of at least one pilot signal pattern of a wireless communication system are disclosed. A method and a module of frequency acquisition are also disclosed.

Abstract: A method and system is provided for acquisition of the initial timing for a digital phase lock loop timing recovery system. A modified loop filter and post filter allows for an instantaneously change the oscillation frequency of a controllable oscillator and an instantaneous relative change of the sampling phase of the sampled data. These two features are used for initial timing recovery, in which the process of frequency and phase acquisition is separated into two independent steps. Once the initial timing is acquired, the timing recovery system is operated as a conventional digital phase lock loop timing recovery system to track additional frequency and phase drifts at the receiver with respect to the transmitter.

Abstract: A synchronization establishing and tracking circuit for a CDMA base station is composed of a first spreading code generator, a first correlator, a second spreading code generator, a second correlator, and a phase determining circuit. The first spreading code generator generates a first spreading code sequence. The first correlator calculates first correlation between the first spreading code sequence and a first quasi-coherent signal corresponding to a first received signal received by the CDMA base station. The second spreading code generator generates a second spreading code sequence. The second correlator calculates second correlation between the second spreading code sequence and a second quasi-coherent signal corresponding to a second received signal received by the CDMA base station. The phase determining circuit determines a first phase of the first spreading code sequence based on an added quasi-coherent signal to which the first and second quasi-coherent signals are added.

Abstract: A demodulator for demodulating digital data includes a receiver for receiving a digital data signal, a determining device to determine if a fractional sample delay added to a demodulator's symbol sampling timing would improve synchronization timing, an implementing device implementing the fractional sample delay if the determining device determines that a fractional sample delay would improve the demodulation synchronization timing, and a demodulating device for demodulating the digital data signal. A method for demodulating digital data includes the steps of receiving a digital data signal, determining if a fractional sample delay added to a demodulator's symbol sampling timing would improve synchronization timing, implementing the fractional sample delay if it is determined in the determining step that a fractional sample delay would improve the demodulation synchronization timing, and demodulating the digital data signal.

Abstract: A system and method for controlling a transverter from a wireless modem unit (WMU). A WMU delivers a control signal to a transceiver. This signal is outside the IF signal data range (preferably below 11 MHz). The signal is carried on the cable between the transceiver and the WMU. This signal is detected by the transceiver, and determines the timing and the control information. The signal is ASK modulated to enable low data rate transfer of messages between the WMU and the transceiver. The control signal is detected at the transverter using a detector circuit. Additionally, specific transverter detection circuits are disclosed to detect the control signal.

Abstract: A method of apparatus for achieving and maintaining alignment of a data receiver to data frames in the presence of noise is taught. A statistical weighting process is employed to sample synchronization symbols that reoccur in data frames. The information is used to maintain alignment to the data frames by tolerating a greater number of data errors. A plurality of synchronization symbols are decoded with a weighted probability of error in decoding determined for each. The weighted probabilities are combined and the resultant value is compared to a threshold value. If the threshold is met, then alignment is achieved or maintained based upon the statistical process. Improved performance in lower SNR environments is achieved.

Abstract: A channel quality assessment with short assessment time and good frequency resolution is disclosed. Some channels are grouped and their detecting results are collected as whale to determine the channel quality. The channel quality is determined by interference collision ratio, which is the ratio of the number of interference events to the sum of the number of interference events and interference-free events. Interfered channels are disabled form the group. The Channel quality of each of plurality of channels is determined from detection results of each of plurality of groups so as to have a short assessment time and meanwhile a good frequency resolution may be retained.

Abstract: A method of compensating for carrier frequency and phase errors of a received multi-carrier modulated signal. The received multi-carrier signal including modulated carriers for transmitting known data and unmodulated carriers for error correction, comprising, time domain down converting the received multi-carrier signal to base-band to provide a down-converted signal, the down-converted signal including a plurality of modulated carriers for transmitting known data and unmodulated carriers for error correction. Sampling an unmodulated carrier of the down-converted signal to provide received data samples. Providing a reference signal derived from the unmodulated carrier of the down-converted signal. And, estimating phase errors from a phase difference between the ummodulated carrier and the reference signal derived from the unmodulated carrier of the down-converted signal to provide a plurality of received sample phase error estimates for each modulated carrier.

Abstract: The present invention discloses a method and system for synchronizing processing modules. More specifically the present invention utilizes a master clock signal and associated synchronization information to coordinate the function dictated by packets within a synchronization stream. The master clock has multiple sources. Each module in the system is connected to each clock source to ensure that if one source fails, the module will not fail. The clock signal to each module is further passed through a locked oscillator, which will continue to maintain the clock signal should the master clock signal fail. Each module contains a sync decoder to decode the SYNC packets in the synchronization stream, into system time events. The system time events are then passed to a plurality of event receivers. Each event receiver contains at least one flywheeling counter to ensure that each event receiver remains in synchronization with the system time events being passed by the sync decoder.

Abstract: Described is a system and method for providing a synchronization pattern in a communication system. The method includes generating a synchronization pattern with good randomness properties; packing a signal for transmission with m headers, each header consisting of the synchronization pattern 1/m symbol-time shifted from the previous header; and transmitting the signal. A further method provides for the sampling the transmitted signal with m headers of symbol-time shifted synchronization patterns; and determining symbol timing offset by computing and reordering correlation peaks from the synchronization patterns. A system includes a transmitting system, a receiving system, and a data channel. The transmitted signal includes m headers with 1/m symbol-time shifted synchronization patterns. The receiving system undersamples the transmitted signal with m synchronization patterns to simulate an oversampled synchronization pattern.

Abstract: A modulator, and demodulator, apparatus and method for use in a multiple sub-channel communication system is taught. A commutator is employed for fractionally sampling, or distributing, signals from, or to, a multiple channel polyphase filter. The filter is coupled with a discrete Fourier transform, or its inverse, such that the relationship between the base-band sampling rate of a plurality of sub-channel signals, the frequency spacing of the sub-channel signals, and the sampling rate of a composite signal can be related by any rational number, thereby freeing designers to optimize system design respecting channel spacing, bandwidth, and signaling rates. The advantages of the present invention are realized by adjusting the interpolation and decimation rates of the filter, and by adjusting the resolution and decimation rates of the transform.

Abstract: A variable-mode digital logic circuit is provided for accepting and serializing a parallel data word, so that the parallel data word may be transmitted from the digital logic circuit over a single one-bit wide trace. In some embodiments, the variable-mode digital logic circuit may include a plurality of parallel data traces for receiving the parallel dataword, a plurality of select-capable multiplexor circuits for sequentially activating certain ones of the parallel data traces and for multiplexing the received data into a serial data stream, a ring counter for controlling a frequency of specific operations performed within the circuit, and at least one additional multiplexor circuit array for receiving data output from the plurality of select-capable multiplexor circuits and for further serializing the received data for output on the single one-bit wide trace. The digital logic circuit may be adapted to operate according to one of a plurality of variable modes.

Abstract: A frequency estimate of an incoming data input is generated and transmitted with network traffic to a receiver. At the receiver, the estimate is recovered, decoded, and is used to seed an algorithm for locking the data access rate of the receiver to the incoming data. Data is buffered in buffers at each end of the system, and data flow out of the buffers is managed depending upon data rate.

Abstract: A receiver configured to receive signals corresponding to spread spectrum information symbol streams by pseudorandom binary sequences includes at least one channel (V1) with an adapted filter (20) and with a symbol clock signal (Hs) recovery circuit (12) and other channels (V2, . . . , Vk) with a sliding correlator (302, . . . , 30k) using the symbol clock signal (Hs) produced by the channel (V1) with adapted filter.

Abstract: A clock signal recovery circuit that is implemented in a receiver of a universal serial bus (USB) and a method for recovering a clock signal. The clock signal recovery circuit comprises a phase detector, a bidirectional shift register, a multiphase clock signal generator, and a phase selector. The phase detector detects a difference in phases between received data and a predetermined recovery clock signal and generates a first control signal indicative of the detected phase difference. The shift register is shifted in response to the detected signal and outputs a second control signal.

Abstract: An apparatus and method for estimating a frequency and/or a phase of a digital input signal by determining phase values of the input signal. The phase values are then added over a predetermined summation length N/B. The sampling rate of the added-up phase values are reduced by a factor N/B in comparison with the sampling rate of the phase values. The added-up phase values are delayed in a chain of at least B?1 delay elements. The differently-delayed added-up phase values are then added or subtracted to create a resulting. pulse response of the frequency such that the resulting pulse response of the frequency is constant positive in a first interval, is zero in a second interval and is constant negative in a third interval, so that a resulting pulse response of the phase is constant in at least a middle interval or is otherwise zero.

Abstract: A synchronizing signal processing circuit for use in a video apparatus such as a display apparatus and an information recording/reproducing is disclosed. The synchronizing signal processing circuit is capable of not only removing false synchronizing pulses included in incoming synchronizing signals and compensating for missing signals, but also causing its output to follow its input quickly after a phase of the incoming synchronizing signals has shifted abruptly.

Abstract: A reception interface unit in a transmission system wherein time series data is divided into data groups and a data packet with reproduction specification time data specifying a time at which each data piece in the data groups should be reproduced, added to the data groups is transmitted on a transmission bus in a time division manner.

Abstract: A frequency and phase synchronizer system comprises a processor for executing a sequence of operations, which include: a) initializing a frequency error estimate value and phase error estimate value; b) separating discrete samples of a continuous phase modulation signal into a first sequence of odd numbered samples of the signal, and a second sequence of even numbered samples of the signal; c) determining an unknown frequency offset value from the first and second sequences, frequency error estimate, and phase error estimate; d) determining an unknown phase offset value from the first and second sequences, frequency error estimate, phase error estimate, and a first discrete data sample of said discrete samples of the continuous phase modulation signal; f) updating the frequency error estimate from the unknown frequency offset value; and updating the phase error estimate from the unknown phase offset value.

Abstract: Transmitter frequency locking across a full duplex communications link. An offset in one transmitter results in an offset at the corresponding receiver. That receiver offset shifts its transmitter in a corresponding manner, causing a correcting offset in the first receiver, which is used to correct the first transmitter. A first embodiment uses filtered received frequency information derived from a baseband demodulator to correct transmitter frequency. A second embodiment uses filtered frequency information from a frequency detector to correct transmitter frequency.

Abstract: A digital subscriber line network allows a plurality of remote modems to communicate without interfering with the communication to the central office. Each symbol of a superframe is converted to a tone vector, and the tone vectors are integrated over a plurality of superframes. The tone vectors of the data symbols are random, and tend to cancel each other out. The tone vector of the synchronization symbol remains constant among the plurality of superframes, and the sum of these tone vectors over a plurality of superframes becomes large. By identifying the largest integrated tone vectors, the network may identify the position of the synchronization symbol. The modems may then align using the position of the synchronization symbol.

Abstract: A method and apparatus for time-shift extraction in a wideband transmitted signal containing strong narrowband interference or noise. The time-shift extraction is based on the time domain and frequency domain relation of symbol misalignment. The invention uses the sign of the product of a recieved signal sample and a reference symbol in the frequency domain to determine the time-shift. It does not rely on the signal magnitude and is therefore less dependent on the signal gain. It also does not rely on the soft phase values, which have ambiguity for values more than three hundred sixty (360) degrees.

Abstract: An apparatus for synchronizing the system clocks of wireless devices in a digital communications system is presented. A digital phase-locked loop is employed. The phase-locked loop may include a counter which is incremented by a local device system clock and latched by a frame synchronization marker received from a remote device, whereby the counter output comprises a feed forward signal. The phase-locked loop may alternatively include a counter that reflects the level of data stored in receive and/or transmit FIFO buffers. The loop output signal controls the frequency of the system clock oscillator.

Abstract: A time division multiple access communication system is provided having multiple sub-channels according to known quadrature amplitude modulation techniques. Each sub-channel has a pre-determined time duration and is divided by a pre-determined number of symbol position time divisions. The symbol positions carry color codes and ACP codes in addition to sync, pilot and data symbols. Pilot symbols in the second half of the slot are replaced with dual purpose color code and ACP symbols. The dual purpose symbols are either modulated with a lower order modulation than data symbols or are repeated values of dedicated symbols located earlier in the same slot, or both. Slot throughput is attained with a minimal bit error rate penalty.

Abstract: A method of determining a transfer speed of an encoded data signal including a clock signal and a data signal is provided. First, the encoded data signal is decoded to generate a decoded clock signal. Then, a data transfer speed of the encoded data signal is determined using the decoded clock signal.

Abstract: A clock extracting part has a first phase comparator circuit, a first up/down counter, a weighting circuit, a charge pump and a low-pass filter forming a voltage value determining part, and a voltage controlled oscillator circuit. A retiming clock generating part has a second up/down counter and a phase switching circuit. Furthermore, a phase adjusting part has a first counter, a second counter, a second phase comparator circuit and a third up/down counter forming a phase adjusting part. A clock data recovery circuit is formed by said clock extracting part, the retiming clock generating part, the phase adjusting part, and a first-in first-out memory part. Thereby, a clock data recovery circuit is obtained, in which jitter transfer characteristics and jitter tolerance satisfy the standards of both the SONET and SDH.

Abstract: A method for modulating a basic clock signal for digital circuits, in which distances between adjacent switching edges are altered, the basic clock signal being conducted via a changing number of delay units for altering the distances between the adjacent switching edges, the method comprising the step of calibrating delay times of the delay units (D1-Dn), wherein the delay units (D1-Dn) each have a plurality of delay elements (10) which are controlled to impart zero delay or a non-zero value of delay to a clock signal individually or in groups of the display elements; wherein the respective distance between two adjacent switching edges is derived from numbers of a random number generator; and wherein the distance between two successive switching edges is derived as a function of the random number and a modulation factor.

Abstract: A synchronization system in accordance with the principles of the invention includes a central synchronizing management unit, at least one synchronization distribution unit, and at least one network element. Each synchronization distribution unit receives synchronization and management information from the central synchronization management unit. This information may be transmitted directly from the central synchronization management unit, or it may be transmitted though another synchronization distribution unit in a group of a daisy-chained synchronization distribution units. The daisy-chained arrangement employs both active and passive optical paths. The central synchronizing management unit may query any synchronization distribution unit within the system to obtain performance statistics.

Abstract: The synchronization technique invention uses inherent characteristics of the frequency domain representation of the data symbols. By computing a differential-in-frequency function across a large number of OFDM tones, robust estimates of time and frequency offset can be easily obtained. The technique also allows the system designer to directly trade performance in the presence of channel impairments against signal processing complexity. Analysis and simulation have shown good performance in the presence of noise and channel delay dispersion, impairments that are the harshest in a wireless environment. Prior techniques for OFDM synchronization have focussed on the time domain representation of the signal. Those that have recognized the translation of time and frequency offset to the frequency domain have not considered the systematic modification of the signal by the offsets.

Abstract: Disclosed is a digital variable oscillator which has: a cycle change detector for detecting the change of cycle between two input data; a decoder for outputting a predetermined signal in relation to the detection result of the cycle detector; an adder for adding signal output from the decoder a predetermined time; and a frequency adjuster for adjusting the frequency of window signal in relation to the addition result of the adder.

Abstract: Uniform distribution of a correction determined by a PLL over the subordinate clock signals is undertaken by dividing a phase-regulated value by the number of subordinate clock signals. Division by way of successive addition is performed such that time conflicts with subordinate clock signals generated in real time are successfully avoided despite the required time duration of such a division. The synchronicity can be further raised by also uniformly distributing a division remainder. A particularly effective implementation of this division employs subsequent rounding for real time use.

Abstract: The invention concerns a method of checking the synchronization between at least two nodes Ni?1, Ni, with i=1, . . . , n in a network, each of said nodes having respectively an internal clock having a respective clock frequency Fi?1, Fi, wherein said method includes the following steps: a) transmitting the frequency Fi?1 of the internal clock from the node Ni?1 to the node Ni, b) comparing the frequency Fi?1 of the internal clock of the node Ni?1 transmitted to the node Ni with the frequency Fi of the internal clock of said node Ni, c) checking the synchronization between the nodes Ni?1 and Ni using the result of the comparison between the frequencies Fi?1 and Fi.

Abstract: An offset value corresponding to the difference between counter values of cycle time counters in two buses is obtained and stored, so that the buses are connected, the value of a first cycle time counter is compensated for buy an offset value. The counter value of the first cycle time counter is compared with the counter value of a second cycle time counter, and a time stamp of data is changed corresponding to the offset value.

Abstract: Methods and apparatus for enhanced timing loop are provided for a partial-response maximum-likelihood (PRML) data channel in a direct access storage device (DASD). An acquisition timing circuit for generating an acquisition timing signal includes a plurality of compare functions for receiving and comparing consecutive input signal samples on an interleave with a threshold value. The acquisition timing circuit includes a majority rule voting function coupled to the plurality of compare functions for selecting a timing interleave. Tracking timing circuitry for generating a timing error signal during a read operation includes a channel data detector. The channel data detector receives disk signal input samples and includes a multiple-state path memory. The tracking timing circuit includes a low latency detector receiving disk signal input samples. A selector function is coupled to an output of the low latency detector and is coupled to the multiple-state path memory for selecting a state.

Abstract: A data transmission system comprising a transmitter and a receiver that use a single external word clock to generate all needed clocks locally using a clock generator and a phase locked loop. Data words are transmitted on a transmission line based on a single transition of the word clock. The transmitter and receiver may each be incorporated on a single chip.

Abstract: The present invention refers to methods and apparatuses for providing synchronization in a time division multiplexed network, wherein data is transferred on multi-access bitstreams in circuit-switched channels that are defined by respective time slots of regularly recurrent frames of said bitstreams, said frames being defined by regularly recurrent frame synchronization signals transferred on said bitstreams. According to the invention an auxiliary regularly recurrent frame synchronization signal is generated and selected as a basis for defining said frames on a bitstream if the frame synchronization signal that is used as a basis for synchronizing said frames during normal operation is not detected in accordance with an expected frame rate.

Abstract: There is disclosed an improved system and method for providing frequency domain synchronization for a single carrier signal such as a vestigial sideband signal. The system comprises a synchronization circuit that is capable of obtaining a coarse frequency estimate of the single carrier signal and a fine frequency estimate of the single carrier signal. The system also comprises a three state machine for obtaining an accurate frequency estimate from three separately obtained frequency estimates. The system also comprises a DC estimator circuit that is capable of providing a time domain DC estimate. The system provides a pilot carrier recovery circuit for single carrier signals that has a linear transfer function.

Abstract: An apparatus that reduces sampling errors for data communicated between devices uses phase information acquired from a timing reference signal such as a strobe signal to align a data-sampling signal for sampling a data signal that was sent along with the timing reference signal. The data-sampling signal may be provided by adjustably delaying a clock signal according to the phase information acquired from the strobe signal. The data-sampling signal may also have an improved waveform compared to the timing reference signal, including a fifty percent duty cycle and sharp transitions. The phase information acquired from the timing reference signal may also be used for other purposes, such as aligning received data with a local clock domain, or transmitting data so that it arrives at a remote device in synchronism with a reference clock signal at the remote device.

Abstract: A clock signal extracting circuit extracting a clock signal from N-pieces of data bit signals, where said N is an integer of two or more, including N-pieces of phase comparators, each of which compares a phase of each of the data bit signals with a phase of an extracted clock signal and generates a up-signal and a down-signal in accordance with a compared result, N-pieces of charge pumps, each of which generates a current in accordance with the up-signal and the down-signal inputted from each phase comparator, an adder for adding currents generated by the N-pieces of charge pumps, a loop filter for generating a control voltage in accordance with an added current by the adder, and a voltage control oscillator for generating the extracted clock signal of a frequency in accordance with control voltage. With this configuration, it is possible to prevent a retiming margin in a parallel digital interface from increasing.