Abstract: A method that allows a digital communications system to detect the presence of transmitted messages in noisy environments. The system includes an OFDM transmitter and an OFDM receiver. The OFDM transmitter converts a digital signal to be transmitted to a plurality of sub-signals, each corresponding to a respective sub-carrier frequency. The signal is a packet including a preamble field having a known data pattern. The transmitter pre-codes the preamble data pattern, maps the data to corresponding phase information, converts the sub-signals to the time domain, and converts the sub-signals to analog form for subsequent transmission. The OFDM receiver receives the transmitted sub-signals, converts the sub-signals to digital form, converts the sub-signals to the frequency domain, and subjects the sub-signals to preamble detection processing to detect the signals' presence.

Abstract: An apparatus that reduces sampling errors for data communicated between devices uses phase information acquired from a timing reference signal such as a strobe signal to align a data-sampling signal for sampling a data signal that was sent along with the timing reference signal. The data-sampling signal may be provided by adjustably delaying a clock signal according to the phase information acquired from the strobe signal. The data-sampling signal may also have an improved waveform compared to the timing reference signal, including a fifty percent duty cycle and sharp transitions. The phase information acquired from the timing reference signal may also be used for other purposes, such as aligning received data with a local clock domain, or transmitting data so that it arrives at a remote device in synchronism with a reference clock signal at the remote device.

Abstract: A communication test circuit for allowing a tolerance test to be carried out in a general testing environment. The communication test circuit includes an adder and a second clock generation block. When an offset is input to the adder, the adder adds the offset to a phase adjustment signal for adjusting the phase of a clock signal for data detection and outputs the result to the second clock generation block. The second clock generation block outputs a second clock signal adjusted in accordance with the phase adjustment signal to which the offset has been added. Accordingly, a clock signal shifted in accordance with the offset from a natural clock signal along the time axis is generated at a test.

Abstract: A circuit to synchronize the phase of a distributed clock signal to a received clock signal. Embodiments include a control loop comprising a phase interpolator, a clock distribution network, and a data receiver. The clock distribution network provides a sampling clock signal to clock the data receiver. The data receiver receives as its input the received clock signal. Control logic maps a subset of the output samples to a value, and this value is added to the phase introduced by the phase interpolator to provide an updated phase. Embodiments include a second phase interpolator and a second distribution network to clock a second data receiver, where the second data receiver receives the data. The control logic adjusts the second phase interpolator in the same way that it adjusts the phase interpolator. The two data receivers are matched to each other, and the two clock distribution networks are matched to each other. Other embodiments are described and claimed.

Abstract: A method and system for an optimal one-shot estimate of phase and frequency for timing acquisition employ a maximum a posteriori (MAP) formulation to calculate a cost function that is a function of an estimated frequency and an estimated phase. A plurality of cost functions are calculated each using a different estimated frequency and a different estimated phase, and the minimum value cost function is selected. The estimated frequency and estimated phase values are selected from a range of frequency and phase values. The minimum value cost function corresponds to the optimum frequency and the optimum phase.

Abstract: A test system using direct digital synthesis for generation of a spectrally pure, agile clock. The clock is used in analog and digital instruments in automatic test system. A DDS circuit is synchronized to the tester system clock because it is clocked by a DDS clock generated from the system clock. Accumulated phase error is reduced through the use of a parallel accumulator that tracks accumulated phase relative to the system clock. At coincidence points, the accumulated phase in the DDS accumulator is reset to the value in the system accumulator.

Abstract: A frequency error correction device for an OFDM receiver is proposed. The receiver receives an OFDM signal with a preamble section and a payload section including pilot carriers. The frequency error correction device includes a first frequency correction unit for correcting a relative phase error in a predetermined period of time based upon a frequency error in the preamble section of the OFDM signal in time domain, and a second frequency correction unit for correcting a remaining phase error in every predetermined period of time based upon the pilot carriers of the OFDM signal in frequency domain.

Abstract: A phase drift compensation scheme for multi-carrier systems. According to the invention, a timing offset compensator is provided to compensate for a timing offset in a current symbol after taking an N-point FFT. Then a phase estimator computes a phase estimate for the current symbol based on a function of a channel response of each pilot subcarrier, transmitted data on each pilot subcarrier, and a timing compensated version of the current symbol on the pilot subcarrier locations. From the phase estimate, a tracking unit can generate a phase tracking value for the current symbol. Thereafter, a phase compensator uses the phase tracking value to compensate the timing compensated version of the current symbol for the effect of phase drift.

Abstract: A packet stream multiplexer may include one or more control loops (e.g., digital phase locked loops) for tracking the source clock frequency associated with a packet stream. A first control loop may slowly drive an error between a received timestamp and an estimated timestamp to zero. A second control loop may more quickly drive a first derivative of the error to zero. The second control loop may include a set of digital filters ordered according to tracking speed. The output of the slowest filter is initially selected for updating the source clock frequency estimate. As time progresses, the faster filters are selected in succession. The estimated source clock frequency is used to restamp packets of the packet stream as they are sent out onto an output channel.

Abstract: Synchronization and impairment estimations can be performed jointly, thereby saving valuable time for decoding of the received packet. An initial synchronization in a TDMA system can be performed. Using this synchronization, the frequency offset choices and timing offset choices can be advantageously bounded within predetermined ranges. At this point, an algorithm can find the minimum error that gives the best frequency offset choice and timing offset choice combination over their respective ranges, together with the estimates of the signal magnitude and phase and at least one of a DC offset magnitude and phase, and a spur magnitude and phase.

Abstract: The present invention relates to a signal processing device and a signal processing method that are capable of processing various types of signals. The signal processing device comprises a frequency detecting unit detecting a frequency of a data signal by checking synchronization between the data signal and a reference signal, an oscillation unit supplying the reference signal to the frequency detecting unit, a frame detecting unit detecting a frame organizing the data signal, and a control unit changing a frequency of the reference signal supplied by the oscillation unit to take frequency synchronization between the data signal and the reference signal in checking the synchronization by the frequency detecting unit, and setting information of the frequency, of which the frequency synchronization has been taken, in the frame detecting unit.

Abstract: A sync pattern detection apparatus includes a sync pattern detection unit configured to detect a sync pattern from an input signal, a plurality of sync pattern protection units configured to protect the sync pattern detected by the sync pattern detection unit, a reliability evaluation unit configured to evaluate the reliabilities of a plurality of sync pattern protection situations by the plurality of sync pattern protection units, and a selection unit configured to select a sync pattern protected by a predetermined sync pattern protection unit, on the basis of the reliability evaluation of the plurality of sync pattern protection situations by the reliability evaluation unit.

Abstract: A method of frame synchronization includes: inserting synchronous pilots including odd synchronous pilots and even synchronous pilots in a frame; transmitting first signals on the odd synchronous pilots, and transmitting second signals of inverse values of the first signals transmitted on the odd synchronous pilots on the even synchronous pilots; synchronizing the frame according to the odd synchronous pilots and the even synchronous pilots. With the method provided by embodiments of the present invention, complexity of the frame synchronization may be decreased and delay of the frame synchronization may be reduced.

Abstract: A delay locked loop includes a delay line for delaying an input signal generated from an external signal. A delay controller controls the delay line to keep the external and internal signals synchronized. The delay locked loop also includes cycle control circuitry for controlling the cycle time of the signal entering the delay and the cycle time of the signal exiting the delay line.

Abstract: Detection method and device for a receiver in a digital communication system designed to process a frame comprising a periodic sub-set of length n, said method comprising the following steps: —determining a first vector u having a length n;—determining a second shifted vector v;—calculating a correlation function between said first and second vectors; —calculating a quadratic error function between said first and second vectors;—calculating a first cost function that is a linear combination of both preceding functions and, according to the sign of the result,—calculating a second cost function of frame beginning estimate; and—starting the communication system receiver.

Abstract: In an orthogonal frequency division multiplexing (OFDM) system, a receiver of an OFDM signal via an air interface defines training symbols to be included in the frame structure of the air interface and a post-FFT receiver algorithm that can efficiently estimate a fractional frequency offset (e.g., a frequency offset less than a single intercarrier spacing). The algorithm may be modified to estimate a large frequency offset (e.g., of more than a single intercarrier spacing) using increased hardware complexity. The algorithm does not need a correlator block in its simplest implementation. The frequency detection itself features excellent performance in a very low SNR environment. However, if noise plus timing error is present, system parameters may be designed to substantially assure good performance in low SNR.

Abstract: The phase of a data signal relative to a reference clock signal is approximated relatively accurately using only relatively coarse increments of phase shift between trial version of a sampling clock signal (derived from the reference clock signal). Information about which amounts of progressively greater phase shift in the sampling clock signal cause loss of alignment between a training pattern and training data in the data signal can be used for such purposes as identifying the amount of phase of shift of the reference clock signal that will be best for use in sampling the data signal during normal (post-training) operation.

Abstract: Systems, methods, and other embodiments associated with a repeatable communication system are disclosed. One example system for receiving signals from an electronic component over a plurality of point-to-point communication links comprises a repeatability logic operably connected to each of the plurality of point-to-point communication links and configured to apply a delay offset to the signals received to compensate for frequency changes in signal transmissions over the plurality of point-to-point communication links.

Abstract: A method for processing an input burst signal comprising a first step for identifying an additive DC component and generating an output signal, which is representative for an estimated value of said DC component. The method further comprises a second step for detecting a predetermined signal portion from a plurality of possible signal portions included in the input burst signal and generating a control signal indicating the presence of the predetermined signal portion in the input burst signal. The method is characterized in that the first step and the second step are performed in parallel i.e. in a commonly defined time interval from a starting time of the burst.

Abstract: A system and method for aligning an input signal (24) synchronized to a first clock signal (22) with a second clock signal (26) The invention includes a mechanism (106) for generating a third clock signal (354) and an arrangement (352) for loading the input signal (24) in accordance with the third clock signal (354) and reading out an output signal in accordance with the second clock signal (26). In an illustrative embodiment, the invention is used in a sensor system (350) to align detector input data (24), which is synchronized to a data-capture clock (22), with a signal-processing clock (26). The register (352) acts as a data path transitioning stage between the actual time the input data is sampled and the time a processing system (102) clocks in the sampled data.

Abstract: An improved apparatus (and corresponding methodology) for discovering beacon signals in a spread spectrum radio communication system is provided, wherein the beacon signals comprise a plurality of different code sequences having index values assigned thereto and having portions that overlap one another. Correlation is performed over an extended search window. Ambiguities between correlation peaks are resolved by identifying correlation peak pairs corresponding to overlapping code sequences and having time offsets that fall within a predetermined tolerance window. Each pair is analyzed to identify the peak with a lower power level metric, and information pertaining to this lower power level peak is discarded from output and processing operations that follow therefrom.

Abstract: A circuit according to an embodiment of the present invention comprises a first power supply region supplied with a first power supply voltage, and having a first clock distribution network, a second power supply region supplied with a second power supply voltage, and having a second clock distribution network, a PLL circuit which provides a first output signal obtained by making a phase of a reference clock signal for controlling a data input/output coincident with a phase of a clock signal at an end point of the first clock distribution network, to a start point of the first clock distribution network, and a PLL circuit which provides a second output signal obtained by making the phase of the reference clock signal coincident with a phase of a clock signal at an end point of the second clock distribution network, to a start point of the second clock distribution network.

Abstract: A probability estimating apparatus and method for peak-to-peak clock skews for testing the clock skews among a plurality of clock signals distributed by a clock distributing circuit, and for estimating the generation probability of the peak-to-peak value or peak value of the clock skews. The probability estimating apparatus for peak-to-peak values in clock skews includes a clock skew estimator for estimating clock skew sequences among the plurality of clock signals under test and a probability estimator for determining a generation probability of the peak-to-peak values in the clock skews among the plurality of clock signals under test based on the clock skew sequences from the clock skew estimator by applying Rayleigh distribution. The generation probability of the peak-to-peak value is estimated based on RMS values of the clock signals and the Rayleigh distribution.

Abstract: A master unit sends a start signal to a slave unit. When receiving the start signal from the master unit, the slave unit sends, to the master unit, a synchronization field that is a data train (pulse signal) indicative of a transfer clock with which the slave unit is able to perform transferring and receiving operations. The master unit sends, to the slave unit, command data in accordance with the transfer clock indicated by the synchronization field sent from the slave unit. In response to the command data sent from the master unit, the slave unit sends, to the master unit, response data in accordance with the transfer clock indicated by the synchronization field. Thus, in a communication system employing a serial data transferring apparatus of the present invention, the master unit establishes the synchronization for the data transfer, while the slave unit is free from a burden of establishing the synchronization for the data transfer.

Abstract: A system, method and computer program product for detecting a frequency burst in a received signal at a wireless receiver is disclosed. The invention predicts the current sample of the received signal by filtering the past samples of the received signal through an adaptive filter. A prediction error is further obtained by subtracting the actual current sample and the predicted current sample. The prediction error is then used to adapt the adaptive filter. Since the frequency burst is a substantially predictable signal, the adaptive filter adapts to accurately predict the samples of the frequency burst. Therefore, the prediction error decreases when the frequency burst is received at the receiver. The end of the frequency burst is identified using the prediction error at each discrete time instant.

Abstract: The invention relates to the distribution of a synchronization signal in an optical communication system which is inherently asynchronous. In order to accomplish a cost-efficient mechanism for transmitting a synchronization signal in such a system, the amplitude of a payload signal is modulated with the synchronization signal, whereby an amplitude-modulated payload signal is obtained. This amplitude-modulated payload signal is transmitted as an optical signal to the opposite end of an optical link, where the synchronization signal is separated from the payload signal.

Abstract: A frame boundary discriminator has a first input for receiving a high speed master clock signal having a multitude of master clock pulses within a frame, and a second input for receiving synchronized input frame pulses subject to jitter. An output frame pulse generator controlled by the high speed master clock signal generates output frame pulses. A control circuit for compares the timing of the synchronized input frame pulses with said master clock pulses and adjusts the timing of said output frame pulses to average out jitter in the input frame pulses.

Abstract: A bit synchronization circuit composed of a multiphase data sampling unit for converting each received burst data sets to multiphase data trains, a phase determination unit for generating a control signal indicating an optimum phase data train, an output data selector for selectively passing optimum phase data train indicated by the control signal, and a data synchronization unit for converting the optimum phase data train to a data train in synchronization with a reference clock. The phase determination unit repeatedly detecting the optimum phase data train during the same burst data set is received. When optimum phase varies, the output data selector dynamically switches the optimum phase data train to be supplied to the data synchronization unit.

Abstract: A frequency offset compensation estimation system and method for a wireless local area network. First, a preamble sequence of a frequency package is sent to a frequency offset estimation (FOE) device so that an initial frequency offset signal amount is obtained and sent to the frequency offset compensation (FOE) device for compensation. Then, the compensated signal is sent to a frequency offset residual phase estimation (FOS RPE) device so as to calculate an offset amount of the frequency and send it to the frequency offset residual phase compensation (FOS RPC) device for compensation. The present invention mainly employs a residual frequency offset estimation device (Residual FOE device) to estimate the residual frequency offset signal of each of the frequency signals compensated by the frequency compensation device and feedback it to the frequency compensation device for compensation.

Abstract: A reference timing architecture is disclosed that provides a level of flexibility that was not available with the architecture in the prior art. In particular, the present invention provides for multiple reference timing outputs that can be routed to equipment nodes relying on the timing information, wherein each of the timing processing paths that provide timing outputs can be controlled independently of one another.

Abstract: A status indication detection apparatus comprises an input storage stage, an intermediate storage stage and an output storage stage. Status indications are input into the input register of the input stage and are shifted to the intermediate and to the output stage. The input and intermediate storage stages operate with a first reference clock in a first clock domain whilst the output storage stage operates with a different second reference clock in the second clock domain. In accordance with the invention a reading out of the intermediate register of the intermediate stage is only possible during the generation of a hold signal which keeps a current status indication in the intermediate storage stage and blocks a transfer of a new status indication from the input stage.

Abstract: A method is provided for fast acquisition in a wireless network. This method involves receiving a first wireless signal at a receiving device, sent from a transmitting device; determining a first transmitting clock phase of the transmitting device by performing first acquisition and tracking processes on the first wireless signal; storing the first transmitting clock phase in the receiving device; receiving a second wireless signal at a receiving device, sent from the transmitting device after the first wireless signal; and determining a second transmitting clock phase of the transmitting device by performing a second acquisition process on the second wireless signal using the first transmitting clock phase as starting phase data. By using the stored first transmitting clock phase information as a starting point for acquisition, the receiving device can perform a second acquisition process that is much faster than a blind acquisition.

Abstract: A method for adjusting a phase difference between a received code modulated signal and a replica code sequence where, in order to enlarge the control range, it comprises a step of determining measurement values representing a phase difference between a received code modulated signal and a generated replica code sequence. The proposed method further comprises determining coefficients for a loop filter operation, which coefficients optimize a predetermined function specified for current properties of the received signal. Then, a loop filter operation is applied to the measurement values to obtain an indication of a required correction of a current frequency of the generated replica code sequence, which loop filter operation utilizes the determined coefficients. Finally, the frequency of the generated replica code sequence is adjusted based on the indication of a required correction. The invention relates equally to a corresponding unit and to a corresponding system.

Abstract: A timing error correction technique for use in data communications receivers such as WLAN (Wireless Local Area Network) receivers is provided where an input signal is received that has a timing error, the timing error is corrected, and a signal having a corrected timing error is output. The timing error correction comprises performing an early-late correlation on the signal that has the corrected timing error. The early-late correlation comprises the generation of at least one early and late sample pair, the generation of an error signal that is indicative of the difference between the early and late samples, and the generation of at least one control signal based on the error signal. A time offset correction algorithm is performed dependent on the control signal.

Abstract: Improved frequency drift and phase error compensation in a VOFDM receiver. The invention is operable to compensate for frequency drift and phase error within a window that may include a single frame, a sub-frame, or multiple frames. The compensation is performed after having performed estimation of the phase within the particular window; any phase error and frequency drift may be identified and an appropriate form of compensation may be identified to perform curve fitting of the phase within the compensation window. The curve fitting of the phase is performed using linear techniques in one embodiment; an average phase and appropriate slope/ramp are calculated to match the phase as accurately as possible. Other alternative compensation techniques may also be performed, including higher order curve matching techniques. The receiver is operable to perform any necessary compensation before passing the now-compensated data to a symbol processing functional block.

Abstract: Stereo recovery circuitry for a digital receiver is disclosed that provides increased accuracy and efficiency in recovering stereo signal information from transmitted stereo signals. The stereo decoder includes a digitally controlled oscillator that recovers a pilot tone signal from transmitted stereo signal information. By processing demodulated stereo signals on the digital side and digitally controlling the oscillator, the stereo decoder has increased efficiency and accuracy. In one embodiment, the oscillator may be a phase-locked-loop having a loop filter and an amplitude stabilized tunable resonator. Additional circuitry is disclosed for utilizing the pilot tone signal to recover left and right channel signal information from the demodulated stereo signals.

Abstract: A receiver determines a symbol synch time for recovering data from a symbol of signal samples generated in accordance with Orthogonal Frequency Division Multiplexing. Each symbol includes a guard period which carries data repeated from a data bearing part of the symbol and pilot signal samples. The receiver compromises a pilot assisted tracker, a guard adapted filter processor and a filter controller. The controller is operable to excite the filter with the symbol signal samples to generate an output signal which provides a further representation of the channel impulse response. A symbol time adjustment estimator is operable to adjust the symbol synch time in accordance with the adjustment provided by at least one the pilot assisted tracker and the guard adapted filter processor. The pilot assisted tracker estimates the symbol synch time from a channel impulse response estimate generated from pilot signal samples.

Abstract: A circuit for receiving multiple serial datastreams in parallel is disclosed. A bit clock is recovered from each data stream, there being one data bit for each transition of the clock signal both positive and negative going. The phases of the bit clocks are compared and are adjusted by 180 degrees so that the positive going edges of all occur close to each other. The bits of each stream are assembled into words under the control of a word clock. In one embodiment a common word clock is derived form the set of bit clocks as a whole. In another embodiment each stream is provided with its own word clock which is aligned to positive edges of the respective bit clocks that are close to each other.

Abstract: Digital broadcasting receiver, and method for compensating a color reproduction error therein, the digital broadcasting receiver including a channel decoder, a TP part for demultiplexing a TP stream from the channel decoder for being provided with a PCR (Program Clock Reference), and receiving a receiver side STC (System Time Clock), and providing a PCR jitter which is a difference between the PCR and an STC value, an STC compensating part for providing the STC value to the TP part from a system clock, and varying the system clock so that the PCR value and the STC value are identical, to generate a reference system clock in which the PCR jitter value becomes ‘0’, a decoder for receiving the reference system clock from the STC compensating part, and decoding a received picture, a display clock generator for providing a display clock generated by receiving the reference system clock as singular system clock, a video format and display processor for receiving the reference system clock and the display clock, and

Abstract: A phase lock loop frequency synthesizer includes a phase rotator in the feedback path of the PLL. The PLL includes a phase detector, a low pass filter, a charge pump, a voltage controlled oscillator (“VCO”), and a feed back path connecting output of the VCO to the phase detector. The feedback path includes a phase rotator connected to the output of the VCO and to an input of a frequency divider. Coarse frequency control is implemented by adjusting the input reference frequency to the phase detector or by adjusting the divider ratio of the frequency divider. Fine frequency control is achieved by increasing or decreasing the rotation speed of the phase rotator. The phase rotator constantly rotates phase of the VCO output, thereby causing a frequency shift at the output of the phase rotator. The rotation speed of the phase rotator is controlled by an accumulator and a digital frequency control word.

Abstract: A method and apparatus is provided for use in an inband signaling system for quickly resynchronizing devices in the system after synchronization is lost. Synchronization is quickly established by continuing to apply a synchronization technique even while the devices are synchronized, as opposed to starting the synchronization technique only after synchronization is lost.

Abstract: Method and apparatus for OFDM synchronization and channel estimation. In a temporal embodiment, received embedded system pilot symbols are inverse Fourier transformed at expected index locations and correlated with computed complex conjugates of inverse Fourier transforms of pilot symbols for providing a correlation function for the channel impulse response. In a frequency domain embodiment, embedded system pilot symbols are augmented with pilot-spaced inferred guard band symbols, multiplied by scaled complex conjugates of computed pilot systems, and inverse Fourier transformed into the channel impulse response. Time and frequency are synchronized in feedback loops from information in the channel impulse response. The channel impulse response is filtered, interpolated, and then Fourier transformed for determining channel estimates for equalization.

Abstract: There is disclosed a sample selection and data alignment circuit that is able to recover (retime) a data on a predefined phase of a multiphase clock signal. A plurality of over sampled signals (G0, . . . , Gn?1) is obtained by over sampling an incoming serial binary data (bits) stream with the n phases (G0, . . . , Gn?1) of a multiphase clock signal. A reliable over sampled signal is selected according to a selected signal (G0, . . . , Gn?1) generated by an edge detector which designates which over sampled signal is the best for subsequent processing.

Abstract: A method and related apparatus for reproducing a periodic signal received over a communication channel, or signal window of a desired profile, wherein the resolution of the reproduced signal or window is not limited by a digital sampling interval. The profile can be selected to match and compensate for known or estimated characteristics of a communication channel. A frequency difference, due to a Doppler frequency shift or other errors between received signals and locally generated signals, is determined in a receiver and utilized to derive a fine code phase measurement that is then usable to generate a succession of magnitudes that reproduce the desired signal or window profile.

Abstract: A receiving apparatus and method for a synchronizing process in the digital communication system is disclosed. A receiving apparatus includes: a A/D converting unit for performing an over-sampling process and outputting over-sampled points; a sample classifying unit for classifying the over-sampled points; a integration unit for integrating classified symbol values; a symbol synchronizing unit for selecting a point of symbol synchronization; a frequency estimating unit for estimating a frequency error; and a digital demodulating unit for demodulating values outputted from the symbol synchronizing unit and the frequency estimating unit to a signal. The present invention can simplify a configuration of the apparatus and reduce an amount of parameter-control. Moreover, the present invention can be used in a burst mode of a digital communication system.

Abstract: Device and method for tracking a phase error in a digital TV receiver, wherein a phase noise compensated I signal is subtracted from I level reference signals of VSB signal, to obtain an error of the I signal, a sign of the Q signal having a phase noise thereof compensated is multiplied to the error of the I signal from the error determining part, to estimate a basic phase error, and a phase error compensating area is determined, a preset constant ‘?’ is multiplied to the basic phase error to provide a final phase error in the determined phase error compensating area, and the basic phase error is provided as it is as the final phase error in other areas, thereby estimating the phase error more accurately.

Abstract: A system and method for aligning an input signal (24) synchronized to a first clock signal (22) with a second clock signal (26). The invention includes a mechanism (106) for generating a third clock signal (354) and an arrangement (352) for loading the input signal (24) in accordance with the third clock signal (354) and reading out an output signal in accordance with the second clock signal (26). In an illustrative embodiment, the invention is used in a sensor system (350) to align detector input data (24), which is synchronized to a data-capture clock (22), with a signal-processing clock (26). The register (352) acts as a data path transitioning stage between the actual time the input data is sampled and the time a processing system (102) clocks in the sampled data.

Abstract: Techniques of designing a digital phase lock loop are disclosed. In one embodiment, the digital phase lock loop comprises a synchronization unit producing a producing a plurality of clock signals in accordance with a seed clock signal having a frequency, each of the clock signals having a modified frequency over the frequency of the seed clock signal and a phase shift from each other; a phase-frequency detection unit receiving an input signal and a feedback signal, and sampling the input signal and the feedback signal in accordance with the clock signals to determine differences in phase and frequency between the input signal and the feedback signal; a digital control oscillator receiving the clock signals and producing an output signal in reference to the differences from phase-frequency detection unit, and subsequently, a digitally controlled clock signal is produced.

Abstract: A method and circuit to produce an optimal sampling phase for recovery of a digital signal is achieved. A digital signal is over-sampled by sampling on each phase of a multiple phase clock to generate a sample value per phase. The multiple phase clock may be generated by a DLL. A voted value is determined per phase comprising a majority value of a set of consecutive sample values. Transition phases are sensed. A transition phase is defined as two consecutive voted phases comprising different values. The transition phases are compared to a stored phase state to determine a signal shift direction. The signal shift direction is filtered to generate a state update signal. The stored phase state is updated based on the state update signal. The stored phase state corresponds to an optimal sampling phase for recovery of the digital signal.

Abstract: A timing error compensation system in an OFMD/CDMA communication system includes an analog-to-digital converter for converting an OFDM signal, comprised of a data symbol stream in which a pilot symbol is inserted at intervals of a prescribed number of data symbols, received from a transmitter, to a digital OFDM symbol stream by prescribed sampling synchronization, a guard interval remover for removing a guard interval inserted in the OFDM symbol by prescribed frame synchronization, and a fast Fourier transform (FFT) device for performing fast Fourier transform on the guard interval-removed OFDM symbol and outputting a data symbol stream. In the time error compensation system, a pilot symbol detector receives the data symbol stream and detects the pilot symbols inserted in the data symbol stream at prescribed intervals.