Abstract: An approach is provided for supporting carrier synchronization in a digital broadcast and interactive system. A carrier synchronization module receives one or more signals representing a frame that includes one or more overhead fields (e.g., preamble and optional pilot blocks and one or multiple segments separated by pilot blocks). The module estimates carrier frequency and phase on a segment by segment basis and tracks frequency between segments. Carrier phase of the signal is estimated based upon the overhead field. Estimates carrier phase of random data field are determined based upon the estimated phase values from the overhead fields, and upon both the past and future data signals. Further, the frequency of the signal is estimated based upon the overhead fields and/or the random data field. The above arrangement is particularly suited to a digital satellite broadcast and interactive system.

Abstract: PCR jitter is improved when writing an input stream TS having a packet with a PCR in a memory 10 and reading it at a high speed. An oscillator 44 oscillates a local clock signal having a frequency of a reference clock for the input TS and a counter 46 counts the local clock signal. When a PCR detection section 38 detects the PCR in the input TS, a latch circuit 42 latches a counted value of the counter and a PCR exchange section 40 exchanges the original PCR with a result of subtracting the latched count value from the PCR of the input TS.

Abstract: An apparatus for determining phase difference information between a first signal and a second signal includes a first detector, a second detector and a counter. The first detector is used for detecting a first value of the first signal, the second detector is used for detecting a second value of the second signal, and the counter is used for counting a timing when the first signal is at the first value and a timing when the second signal is at the second value with a reference clock signal to generate a counter value which serves as a basis of the phase difference information.

Abstract: An apparatus and method for adjusting transmission phasing in a point-to-point communication link is disclosed. The relative phases of the transmissions from each antenna are adjusted before transmission to give optimum gain when received by two or more antenna elements and a signal combining element. The signal includes a data component, consisting of a subset of the subcarriers modulated with the input data, which is common to transmissions from all antenna elements; and a phase reference component consisting of a subset of the subcarriers that are modulated with a predetermined phase. The signal combining element is operable to receive the components and extract phase information.

Abstract: In one embodiment, a timing-offset estimator calculates a correlation value for each sample of an OFDM signal having a cyclic prefix for each OFDM symbol. The correlation value is provided to a tapped delay line that applies a separate weight to each of 2V correlation values, where V is the length of the cyclic prefix and the weights are based on a triangular weighting scheme that increases linearly from the first value, peaks at the Vth value, and decreases linearly to the 2Vth value. A stream of combined, squared correlation values is generated by combining and squaring the 2V weighted correlation values for each sample of the OFDM signal. For each cyclic prefix of the OFDM signal, a timing-offset estimate is determined based on a detected peak value in the stream of combined, squared correlation values. A timing-offset estimator with triangular weighting scheme may be implemented using recursive processing.

Abstract: A discussion of improving integrated device deterministic response to test vectors. For example, limiting the transmission delay for an integrated device's response within known bounds by synchronizing an initialization training sequence to a reset deassertion. Specifically, the proposal facilitates response determinism from the DUT by synchronizing training sequences and subsequently synchronizing flit transmission to reset assertion as sampled by reference clock.

Abstract: A composite signal includes a high power beacon signal and low power corresponding wideband synchronization signal and is communicated over a time interval exceeding a single OFDM transmission time interval. A base station transmits one or more different such composite broadcast signals in a recurring timing structure. Each different potential beacon signal, e.g., a single tone signal, is paired with a unique wideband synchronization signal. A wideband synchronization signal includes at least some predetermined null tones and at least some predetermined non-null tones. For a given wideband synchronization signal, the predetermined null tones carry predetermined modulation symbol values, A wireless terminal receives a composite signal, identifies a beacon, determines a corresponding known wideband synchronization signal, compares received to known wideband synchronization signals, and determines at least one of a timing adjustment, frequency adjustment and channel estimation.

Abstract: A frequency detecting circuit and method and a semiconductor apparatus including the frequency detecting circuit, in which the frequency detecting circuit includes an edge detecting circuit, a clock signal generating circuit, and a determination circuit. The edge detecting circuit detects an edge of an input clock signal. The clock signal generating circuit generates a selection clock signal, which is a periodic pulse signal, in response to the detected edge. The determination circuit generates a frequency detection signal based on the number of occurrences of the selection clock signal in a period of the clock signal. The semiconductor apparatus includes the above-described frequency detecting circuit and a processor resetting the semiconductor apparatus in response to the frequency detection signal. Since a frequency is detected every half period, that is every high/low level period, of the clock signal in a digital manner, the reliability and the accuracy of frequency detection is improved.

Abstract: A receiver is configured to receive signals corresponding to spread spectrum information symbol streams. The receiver includes a plurality of channel circuits for receiving signals. Each channel circuit is responsive to a received signal for recovering an associated information signal therefrom. The associated information signal is spread by a sequence associated with the respective channel circuit. Each channel circuit is controlled by a clock signal derived by at least a first channel circuit of the plurality of channel circuits. The at least first channel circuit is responsive to the received signal for generating the clock signal by digitally filtering the received signal using digital filter coefficients adapted to the sequence associated with the at least first channel circuit.

Abstract: A communication system for pulse based communication using a sequence acquisition system using the correlation method in UWB communications which generates a pulse detection signal differing in phase by exactly a predetermined period (?) from the transmission information of a pulse signal of a predetermined period at the transmission side and reception side, uses the pulse detection signal to establish synchronization at the reception side, then generates transmission information at the reception side by making its phase different by exactly a predetermined time from the synchronized pulse detection signal so as to establish synchronization between the reception signal and the transmission information, whereby it is possible to enable synchronization acquisition and shorten the synchronization acquisition time without complicating the hardware and even without the presence of information in the transmission signal.

Abstract: A time synchronized measurement system has a master device and a slave device. The master device and the slave device each have a time measurement device for assigning a corresponding time of sending and/or receiving a piece of measurement information. The master device also has a reference clock pulse-generating device for transmitting a reference clock signal to the slave device. The reference clock signal is modulated by a piece of information on a common time basis for the master device and the slave device.

Abstract: A receiving apparatus 100 in accordance with an exemplary aspect of the present invention is including a receiving unit 1 that receives an analog signal, a sample signal generation unit 2 that converts an analog signal received by the receiving unit 1 into a digital signal, and generates a sample signal by performing oversampling, a correlation unit 51 that obtains correlation between the sample signal and a known signal pattern, a symbol section estimation unit 53 that estimates timing of a symbol section based on the correlation value, and a sampling position determination unit 54 that determines a sampling position based on timing of a symbol section estimated by the symbol section estimation unit 53.

Abstract: An Orthogonal Frequency Division Multiplexing (OFDM) synchronization module includes a window generator module, a symbol timing estimator module, and a reliability metric calculator. The window generator module generates a sampling window that bounds a plurality of samples of OFDM symbols. The symbol timing estimator module generates an estimated symbol timing from the plurality of samples before a fast Fourier transform operation is performed on the plurality of samples. The reliability metric calculator calculates a reliability metric for the estimated symbol timing based on the estimated symbol timing. The window generator module changes at least one parameter of the sampling window based on the reliability metric.

Abstract: A system and method are provided for controlling the duty cycle and frequency of a digitally generated clock. The method accepts a first clock signal having a fixed first frequency. A frequency control word with a first pattern is loaded into a first plurality of serially-connected registers. A duty cycle control word with a second pattern is loaded into a second plurality of serially-connected registers. A register clock signal is generated in response to the first clock and the first pattern. Then, a digital clock signal is generated having a frequency and duty cycle responsive to the register clock signal and the second pattern.

Abstract: A signal strength estimation circuit for a code division multiple access system comprises a channel compensator, a demodulator, an extractor and an average circuit. The channel compensator compensates different channel effect upon a received signal and outputs first and second compensated signals wherein the received signal comprises a first signal and a second signal. The demodulator electrically connected to the channel compensator demodulates the first and second compensated signals and outputs first and second demodulated signals wherein the demodulator demodulates the first and second compensated signals by corresponding 4 bits pilot patterns when each of the first and second compensated signals only has 2 pilot bits in a slot and the second signal is obtained by space time transmit diversity encoding the first signal. The extractor coupled to the demodulator respectively extracts first and second pilot signals from the first and second demodulated signals.

Abstract: A synchronization timing detecting apparatus includes a correlation calculator configured to generate a first correlation value by calculating a cross-correlation between an input signal being sampled and a reference signal or an auto-correlation of the sampled input signal, an interpolation processor configured to generate a second correlation value interpolating a plurality of the first correlation values having a different combination of sampling points of the input signal, and a detector to detect a synchronization timing based on the first and the second correlation values.

Abstract: A semiconductor memory device includes an aligning signal generator, a data aligning unit, a data transmitting controller and a data transmitter. The aligning signal generator receives a data strobe signal to output aligning signals. The data aligning unit aligns a plurality of data pieces input in succession in response to the aligning signals. The data transmitting controller generates a data transmitting signal synchronized with the transition of the aligning signal. The data transmitter transmits an aligned data output from the data aligning unit to a data storage area in response to the data transmitting signal. A method for driving the semiconductor memory device includes aligning data pieces input in succession as parallel data in response to a data strobe signal, generating a data transmitting signal corresponding to transition of the data strobe signal and transmitting the parallel data to a data storage area in response to the data transmitting signal.

Abstract: Disclosed are a method of and a system for controlling frame synchronization for European Digital Audio Broadcast (DAB), the method including the steps of generating a frame synchronization start-signal with respect to an incoming signal which is input when power is supplied, keeping symbol count values with the value “0” after the frame synchronization start-signal is input, transmitting a frame offset value with respect to the incoming signal, and restarting symbol counting for frame synchronization depending on the frame offset value after the frame offset value is input, wherein the frame synchronization unit may preferably transmit the frame offset value after estimating the frame offset value. In accordance with the method and system described herein, it is possible to achieve frame synchronization in short time, thereby reducing a startup time of a DAB receiver and power consumption which is needed for the frame synchronization.

Abstract: An apparatus and method is disclosed for synchronizing a timing signal for a computational system to different reference clock signals without impairing the operation of the computational system. A corresponding “offset” register is provided for each of the reference clock signals (RCS) for storing signal timing differences between the timing signal and RCS. When one of the reference clock signals not used for synchronizing the timing signal, is selected as the signal for synchronizing the timing signal, the corresponding offset register R0 (for the newly selected reference clock signals) retains its last value prior to the switch, and another register R1 stores subsequent signal timing differences between the timing signal and the newly selected reference clock signals.

Abstract: In a method of recovering timing information over a packet network at a local receiver, timing information is received at intervals timing from a remote source and compared with a locally generated clock signal to generate an input signal y(k) subject to noise representative of the phase difference between the source clock signal and the local receiver clock signal. The input signal is applied to a state feedback controller, preferably including a Kalman filter, to generate a control signal with reduced noise. The control signal is used to control an oscillator in a way so as to reduce the phase difference and generate a slave clock.

Abstract: Frequency error estimation and frame synchronization are performed at a receiver in an OFDM system based on a metric that is indicative of detected pilot power. The metric may be defined based on cross-correlation between two received symbols obtained in two OFDM symbol periods. For frequency error estimation, a metric value is computed for each of multiple hypothesized frequency errors. The hypothesized frequency error for the metric value with the largest magnitude is provided as the estimated frequency error. For frame synchronization, a correlation value is obtained for each OFDM symbol period by correlating metric values obtained for NC (e.g., most recent) OFDM symbol periods with NC expected values. The expected values are computed in a manner consistent with the manner in which the metric values are computed. Peak detection is performed on the correlation values obtained for different OFDM symbol periods to determine frame synchronization.

Abstract: The present invention relates to a method for automatic gain control (AGC) before an initial synchronization of a mobile station modem in OFDM system, and an apparatus thereof.

Abstract: A time domain symbol timing synchronization circuit is disclosed, which comprises: an autocorrelation function calculator for calculating cyclic prefix autocorrelation functions and an offset time estimator for searching peak positions of cyclic prefix autocorrelation functions to indicate symbol boundary of received communication symbols. The offset time estimator compares a current peak position and a previous peak position. If (a) the difference of the positions is larger than a threshold and (b) the current peak is smaller than a reference average peak, the current peak is determined as false; the offset time estimator weeds out and replaces the current peak position by the previous peak position; and the current peak is not introduced in the reference average peak calculation.

Abstract: A sampling frequency conversion apparatus having sampling frequency conversion circuits for a plurality of channels includes a detector detecting phase information of digital signals inputted to the conversion circuit for each channel, and an input section inputting setting information for the conversion circuits for two or more channels to be phase-synchronized. The apparatus further includes a phase information supplier supplying the phase information for the conversion circuit for a specific channel designated by the setting information inputted into the input section to the conversion circuits for the remaining channels of those for two or more channels other than the conversion circuit for the specific channel, and a sampling frequency converter performing sampling frequency conversion on the phase information of the conversion circuits for the remaining channels in synchronization with the phase information for the specific channel supplied from the phase information supplier.

Abstract: Header information is used to facilitate coarse frequency and frame recovery. The coarse frequency and frame recovery is thereafter utilized to perform adaptive phase and frequency synchronization on a frame-by-frame basis.

Abstract: An autocorrelation filter for use with a spread spectrum receiver. The autocorrelation filter can be used as a prefilter stage to reduce phase distortion present in a spread spectrum signal. The autocorrelation filter can be used to process the output from a lattice filter. The lattice filter is configured to remove magnitude distortion from the spread spectrum signal. The autocorrelation filter performs a series of correlations on the output of the lattice filter. The results of these correlations are integrated over a period of time to generate a running impulse response for characterizing and removing the phase distortion in the spread spectrum signal.

Abstract: Upon a triggering event, a delay chain shifts data out at a higher rate than incoming packets and a processor controls bypassing circuitry to reduce the latency of hardware implementations of, for example, 802.11a OFDM receivers, with long delay chains. The signal processing algorithms used to recover symbol timing need a large number of samples stored in a delay chain, often consisting of pipelined registers. Such a delay chain introduces a large lag between the time samples have been acquired by the data converters and the time they are processed. This delay makes it difficult for higher level network layer implementations to meet the deadlines of 802.11a WLAN protocol. The proposed scheme implements dynamic reduction in the depth of the delay chain once timing recovery has been performed. A multi-step scheme achieves exponential reduction in the number of elements in the delay chain in every step.

Abstract: The apparatus (20) for determining a frequency offset error comprises an input (24.1) for receiving a digitally coded frequency demodulated signal (demod Ip2). The frequency demodulated signal (demod Ip2) is processed by digital means (35) for performing a correlation, and by digital means (36) for performing a minimum-maximum evaluation. In order to determine whether a conflation criterion and a minimum-maximum criterion are fulfilled, the apparatus (20) comprises digital processing means (38) to calculate the current offset of the frequency demodulated signal (demod Ip2) and to cancel the current offset if both criteria are fulfilled.

Abstract: The present application relates to a method and an apparatus for synchronising a receiver timing to a transmitter timing using a known preamble of a signal. In at least one embodiment of the method and/or the apparatus of the present application, a power normalised cross-correlation metric (PNCC metric) is estimated based on a signal power and a noise floor power. According to a first embodiment, two cross-correlation functions, one based on the PNCC metric and the other based on a cross-correlation metric, are used to decide if synchronisation events occur and based on the analysis of time indexes and PNCC magnitude values, a timing synchronisation index used to synchronise receiver timing to transmitter timing is determined. According to a second embodiment, the cross-correlation function based on the PNCC metric is used to decide if synchronisation events occur and based on an analysis of time indexes and PNCC magnitude values using a clustering approach, a timing synchronisation index is determined.

Abstract: Provided are a reference synchronization signal sharing apparatus and a method thereof. The reference synchronization signal sharing apparatus according to the present invention includes a reference signal generator that generates an internal or external reference synchronization signal, and a system clock generator that generates a common system clock for detailed blocks of a wireless communication system in synchronization with the internal or external reference synchronization signal.

Abstract: The phase locked loop (PLL) with adjustable phase shift is described. The PLL includes a voltage controlled oscillator which is capable of generating multiple phase shifted output signals, and multiple phase detectors capable of determining the phase differences between the output signals and a reference clock. The PLL further includes a weighting device capable of weighting the phase differences and generating a control signal for the voltage controlled oscillator.

Abstract: One embodiment of an equalizer circuit has an FIR filter 116 in the asynchronously oversampled domain with a filter coefficient adaptation module that adapts the filter coefficients to the transfer function of a data read channel. Applications include tape drives, drives for optical and magnetic discs as well as receivers. The filter adaptation is performed on the basis of an error signal delivered by a slicer 128 which operates on synchronous samples after timing recovery and sample reconstruction.

Abstract: A clock and data recovery circuit that tracks the frequency and phase fluctuation of serial data includes a feedback controller for monitoring tracking speed of an extraction clock with respect to the frequency and phase fluctuation of the serial data and applying feedback control to an integrator adaptively and moment to moment, thereby raising the tracking speed of the recovered clock and improving the jitter tolerance characteristic.

Abstract: The invention relates to an orthogonal frequency division multiplexing system with PN-sequence. In the synchronization of the invention, both timing offset and frequency offset are estimated and compensated by utilizing a time and frequency synchronization device. In addition, the PN-sequence with the cyclic prefix is added to the OFDM symbol before transmitting. The time and frequency synchronization device of the invention comprises two synchronization circuits from the cyclic prefix and PN-sequence when calculating the timing offset and frequency offset of receiving signal. As a result, the OFDM system of the invention not only has better performance in fading channel, but also has the better bandwidth utilization without extra bandwidth for transmitting the PN-sequence.

Abstract: A transmitter which transmits information in transmission frame to a receiver, the transmission frame including multiple transmission symbols and guard intervals obtained by replicating a fixed time period of a transmission symbol, generates a transmission frame by making phases of one transmission symbol out of two transmission symbols and a guard interval thereof continuous with phases of the other transmission symbol and a guard interval thereof, when the two continuous transmission symbols are the same.

Abstract: A synchronization extraction apparatus for a communication system and a method thereof are disclosed. A frame synchronization is obtained in a manner that the sum of an input signal and a delay signal is obtained without obtaining a simple correlation value between the input signal and the delay signal, and then a correlation value between a summed signal and the delay signal is obtained. The synchronization extraction apparatus and method can reduce the implementation complexity and power consumption in obtaining the frame synchronization, and thus increase the battery cycle of a terminal provided with the synchronization extraction apparatus or method.

Abstract: Inter-carrier interference (ICI) in a kth sub-carrier of an orthogonal frequency division multiplexing (OFDM) signal received at time t is reduced, wherein the received OFDM signal comprises a plurality of sub-carriers. This is achieved by generating a self-interference term, ICIk?L,k?L, for a signal received on sub-carrier k?L, wherein L ? [ . . . , ?3,?2,?1,1,2,3, . . . ], and wherein the self-interference term is an estimate of the data received at time t on the sub-carrier k?L, weighted by a rate of change of the channel through which sub-carrier k?L passes at time t. An ICI cancellation coefficient, GL is obtained, and an estimated ICI term is generated by adjusting the self-interference term, ICIk?L,k?L, by an amount based on the ICI cancellation coefficient, GL. The estimated ICI term is then subtracted from a term representing a signal received on the kth sub-carrier at time t.

Abstract: A wireless communication apparatus is provided for receiving packets transmitted with delay amounts different for the respective transmission branches. The wireless communication apparatus includes a plurality of reception branches, a synchronous processing unit for detecting synchronous timing independently for the respective reception branches; and a signal processing unit for performing decoding processing and other kinds of processing subsequent to the synchronous timing for the respective reception branches.

Abstract: An apparatus and method is disclosed for synchronizing a timing signal for a computational system to different reference clock signals without impairing the operation of the computational system. A corresponding “offset” register is provided for each of the reference clock signals (RCS) for storing signal timing differences between the timing signal and RCS. When one of the reference clock signals not used for synchronizing the timing signal, is selected as the signal for synchronizing the timing signal, the corresponding offset register R0 (for the newly selected reference clock signals) retains its last value prior to the switch, and another register R1 stores subsequent signal timing differences between the timing signal and the newly selected reference clock signals.

Abstract: The time required for the receiving device to synchronize to a desired timeslot is reduced. In operation, a transmitting device selects a synchronization pattern associated with the desired timeslot that is at least mutually exclusive from synchronization patterns associated with other timeslots on the same frequency in the system. Once selected, the transmitting device transmits a burst embedding the synchronization pattern that was selected, where appropriate. If the receiving device detects the synchronization pattern, it immediately synchronizes with the timeslot with confidence that it is synchronizing to the desired timeslot.

Abstract: A circuit and method for timing recovery. The circuit for timing recovery comprises an converter, a timing recovery controller, and a initial phase generator. The converter converts an input signal to sample data with a sampling signal. The timing recovery controller is coupled to the converter, and determines the sampling signal. And the initial phase generator is coupled to the AD converter, detects a change with the sample data only, produces an initial phase based on the change, and controls the sampling signal.

Abstract: Header information is used to facilitate coarse frequency and frame recovery. The coarse frequency and frame recovery is thereafter utilized to perform adaptive phase and frequency synchronization on a frame-by-frame basis. A digitized signal representative of a wireless signal may be received. A frame identifier in a physical layer header in the signal may be identified by correlating the digitized signal to one or more known frame identifiers. The identified frame identifier may be used to estimate a phase or frequency error.

Abstract: An integrated circuit device for use in a node of a communication system is provided. The integrated circuit device includes a memory configured to store data written thereto by a receiver associated with the node in accordance with a receiver clock, and to read data therefrom by a transmitter associated with the node in accordance with a transmitter clock. The integrated circuit device also includes a control logic circuit that is in communication with the memory, and is configured to send a control signal to the transmitter to adjust a speed of the transmitter clock responsive to an operating condition of the memory.

Abstract: An OFDM transmitter and receiver realizing high-speed cell search and having a reducible circuit scale. A base station device (100) serving as an OFDM transmitter comprises an SCH inserting section (125) for constructing a frame where a synchronization sequence in a predetermined position from the head of a first sub-frame is arranged and a synchronization sequence composed of the symbols of the former synchronization sequence and the symbols whose I, Q components are interchanged is arranged in a predetermined position from the head of a second sub-frame adjacent in the time-axis direction to the former sub-frame, an IFFT section (130), a P-SCH conversion section (135), and an RF transmitting section (150) for transmitting this frame. Thus, the receiving end of the frame can locate the position of either of the synchronization sequences and determine the frame timing from the position, thereby increasing the speed of the cell search.

Abstract: A computing platform includes a wireless interface and other devices that may cause interference to the wireless interface. The other devices may change frequencies of operation or data rates to steer signal spectrum away from current wireless channels and reduce interference to the wireless interface.

Abstract: An apparatus for frequency synchronization is proposed to detect a synchronization signal from the baseband signals. It is featured that three types of detection values are introduced to detect whether the synchronization signal is received or not. More particularly, the claimed frequency synchronization apparatus provides at least one signal quality generator for receiving a predetermined number of symbols of the baseband signals, and further calculating an average quality value therefor. Further, the apparatus includes a signal selector for producing a first detection value according to the average quality value. Still further, the apparatus provides a decision unit to produce a second detection value. After that, a signal processor inside the decision unit is used to calculate a third detection value as combining the first detection value and the second detection.

Abstract: A bit clock recovery apparatus for digital storage readout employing sync frames, where an oversampled readout signal is stored in memory, sync patterns are located in the signal using DSP means, distances of consecutive sync pattern locations are calculated, and bit clock is recovered from these distances and the knowledge about the data framing structure.

Abstract: A phase generator includes a phase-shift enable and disable signal generator connected to configuration bits at its first input and connected to a reset signal at its reset input for generating a control signal; the configuration bits corresponding to the phase shift desired. The phase generator includes a logic signal generation device connected at its control input to the output of the phase-shift enable and disable signal generator and connected to a reset signal at its reset input for providing a phase generating signal; and a feedback element connected between the output of the logic signal generation device and control input of the phase-shift enable and disable signal generator for providing controlled clock signal to the phase-shift enable and disable signal generator.

Abstract: A semiconductor integrated circuit including a first power supply region supplied with a first power supply voltage, and having a first clock distribution network, a second power supply region supplied with a second power supply voltage, and having a second clock distribution network, a first phase synchronizer which provides a first output signal obtained by making a phase of a reference clock signal for controlling a data input/output coincident with a phase of a clock signal at a first point of the first clock distribution network, to a second point of the second clock distribution network, and a second phase synchronizer which provides a second output signal obtained by making the phase of the clock signal at a third point of the first clock distribution network coincident with a phase of a clock signal at a first point of the second clock distribution network, to a second point of the first clock distribution network.

Abstract: A rake receiver for DS-CDMA UWB system and a DS-CDMA receiver having the same are provided. The rake receiver includes: a channel estimator for estimating a channel having a predetermined chip duration by using a synchronization acquisition sequence; a tracking module for detecting a channel variation and adjusting a synchronization position value when the channel variation is detected; a first switch for selecting one of an output value of an analog-to-digital converter and an output value of a correlator and outputting the selected value; a second switch for selecting one of the output value of the analog-to-digital converter and the output value of the correlator; and a plurality of demodulators having a parallel processing structure to demodulate received signals by using the channel estimation value inputted from the channel estimator, the synchronization position value stored by the tracking module, and an output value of the second switch.