Abstract: Provided are an apparatus for estimating frequency offset from received signal and method for the same. The apparatus and method estimates frequency offset precisely without increment of autocorrelator by performing moving average filtering on a noised signal to thereby alleviate jitter. The frequency offset estimating apparatus includes: moving average filter for alleviating jitter of received signal; multiplier for multiplying a filtered signal by conjugate complex operanded pilot signal; phase-rotation value calculator for calculating a phase-rotation value from multiplicand operanded signal by using of symbol delay and an autocorrelation function; frequency offset estimator for estimating frequency offset from the phase-rotation value based on a smoothing function multiplication.

Abstract: In a data receiving apparatus, a measuring section measures a first pulse width of a first pulse, a second pulse width of a second pulse and a third pulse width of a third pulse, during each of which a first signal level of a reception signal is continuous. The first pulse, the second pulse, and the third pulse are sequentially and continuously received by putting a portion of a second signal level different from the first signal level between the first and second pulse and the second and third pulse. A first comparing section performs a first determination based on a measured value of the first pulse width and a measured value of the second pulse width, and the first determination is that the first pulse indicates a start of the reception signal and the second pulse indicates a synchronization signal.

Abstract: Detecting a boundary within a transmitted packet is disclosed. A first symbol of the transmitted packet is received in a band. A second symbol of the transmitted packet is received in the band. The first and second symbols are compared. The boundary within the transmitted packet is detected based at least in part on the comparison of the first symbol and the second symbol and the band.

Abstract: A self-tuning 3rd order type III phase-locked loop (PLL) is disclosed. In one aspect, the PLL provides frequency control that is implemented in three (3) parallel paths. The PLL provides frequency response tracking using a number of elements including a triple control voltage-controlled oscillator (VCO), a frequency-to-current (F2I) converter, and a switched capacitor loop filter. In addition to compensation for feedback ratio variation, near constant F2I gain over process variations and switched capacitor filters synchronized to a reference signal, near constant VCO gain over process variations allows the open loop frequency response to be tailored to track the reference signal. A high-speed locking technique is employed which significantly reduces acquisition time in low bandwidth cases. This PLL may be fabricated in a 0.18 ?m CMOS logic process.

Abstract: The apparatus contains a counter that is synchronized to the reference time in the mobile station. The counter counts sampled chips of the radio signal to produce a count. The apparatus further includes a controller that controls the processing of the radio signal, activates the processing of the radio signal when the count matches a begin count, and deactivates the processing of the radio signal when the count matches an end count, wherein the begin count and the end count are determined by a signal processor as a function of the time frame offset of the radio signal with respect to the reference time in the mobile station.

Abstract: A clock synchronization buffer for a counter clock flow pipelined circuit including a cascade of processing modules that receive data from a previous module and provide output results to a following module. The clock synchronization buffer receives a clock input signal and provides clock signals to a local processing module and to the next pipeline stage. The clock synchronization buffer includes a selectable delay stage that receives a clock input signal and a delay select signal and outputs a clock signal having a selected delay. An amplifier connected to the selectable delay stage provides the delayed clock signal to a local processing module that corresponds to the clock synchronization buffer circuit. An inverting amplifier connected to the selectable delay stage provides the delayed clock signal to the next pipeline stage. A clock synchronization controller synchronizes the phases of reference clock input and synchronized clock input signals.

Abstract: A method and apparatus for detecting and synchronizing packets of data with a repeated sequence as a pilot symbol received by a communications system are provided. The method and apparatus include receiving data, detecting a packet within the received data, producing an estimate of the time-varying frequency offset of the received data, estimating the start of the packet of the received data, estimating the time-varying phase offset of the received data and estimating the time-varying time offset of the received data. Methods for assessing each one of the time-varying frequency offset, the time-varying phase offset, the time-varying time offset and the start of packet are also provided.

Abstract: An apparatus that reduces sampling errors for data communicated between devices uses phase information acquired from a timing reference signal such as a strobe signal to align a data-sampling signal for sampling a data signal that was sent along with the timing reference signal. The data-sampling signal may be provided by adjustably delaying a clock signal according to the phase information acquired from the strobe signal. The data-sampling signal may also have an improved waveform compared to the timing reference signal, including a fifty percent duty cycle and sharp transitions. The phase information acquired from the timing reference signal may also be used for other purposes, such as aligning received data with a local clock domain, or transmitting data so that it arrives at a remote device in synchronism with a reference clock signal at the remote device.

Abstract: An apparatus and method for frequency synchronization is proposed to obtain the pilot tones and evaluate the frequency offset and time offset for frequency synchronization. The frequency synchronization method has the following steps: filtering a baseband signal of a frequency correction burst by using multiple pre-filters; measuring the baseband signal and the signals output from the pre-filters to produce the first power value and the second power values respectively; normalizing the maximum second power value by using the first power value so as to produce the first detection value; using the samples of the baseband signal at different time points and a predetermined mathematical function to produce the second detection value; combining the first and second detection values to produce the third detection value; and using the third detection value to determine whether the frequency correction burst is received or not.

Abstract: A method is provided for determining the modulation sequence of the downlink synchronization codes. The method comprises: the method comprises a three step process: step one is to measure the phase of the downlink synchronization code. Step two is to generate an accurate of the phase of the downlink synchronization code by removing the frequency drift effect, step three is to determine whether the sequence S1 or S2 is finally detected. The method allows for high accuracy to be achieved for determination of the modulation sequence of the downlink synchronization codes.

Abstract: A clock rate used in rendering broadcast streaming audio/video data is adjusted to converge on a clock rate associated with broadcasting the streaming data. The clock rate is adjusted by monitoring the buffer depth associated with a receive buffer that stores the incoming streaming data. The buffer depth provides an estimate of clock drift between the two clock rates. From the estimate of clock drift, the clock rate used in rendering broadcast streaming data is adjusted to avoid the clock drift causing skips or pauses in the rendered audio/video data.

Abstract: A receiver arrangement including a received data reproducing device includes an RF (Radio Frequency) receiver configured to determine the signal strength of a received signal and feed it to a clock frequency determining circuit. Number-of-error information, included in the outputs of a clock phase detector and produced during error detection effected with a sync word, a packet header and a payload of a packet field by field, are also fed to the clock frequency determining circuit. The clock frequency determining circuit designates a subject to deal with the packet and selects single clock frequency information out of clock frequencies determined. The clock frequency information thus selected is input to the clock phase detector.

Abstract: There is provided a communication apparatus capable of reducing power consumption. The communication apparatus in accordance with the present invention includes a synchronization detection block 30 which detects synchronization by performing a receiving process using a plurality of clocks whose phase differs from each other with respect to synchronization information contained in a first frame as well as identifies the synchronization detected clocks as candidate clocks to be selected; a clock phase selection block 40 which selects a sampling clock to be used for sampling of the transmission signal from the candidate clocks to be selected, selects a stop clock separated by a predetermined phase from the selected sampling clock, and outputs an instruction for the stop clock; and a clock gate unit 60 which, terminates supplying the stop clock from the plurality of clocks to the synchronization detection block 30 as well as supplies other clocks to the synchronization detection block 30.

Abstract: A phase selection circuit having a selection circuit, binary weighted current sources, and an amplifier circuit. The phase selection circuit is configured for selecting adjacent phase signals from a number of equally-spaced phases of a clock signal, based on a phase selection value. The selection circuit outputs the adjacent phase signals to respective first and second binary weighted current sources, along with a digital interpolation value. The first current source outputs a contribution current onto a summing node based on the first adjacent phase signal and the digital interpolation control value, and the second current source outputs a second contribution current to the summing node based on the second adjacent phase signal and an inverse of the digital interpolation control value, resulting in an interpolated signal. An amplifier circuit outputs the interpolated signal as a phase-interpolated clock signal according to the phase selection value.

Abstract: A communication control apparatus includes a signal receiver for receiving a state variable signal indicating a timing of data transmission from a neighboring node. The apparatus also includes a calculator for forming a communication timing, by varying plural phase signals different in oscillation period in response to the state variable signal, synchronizing respective states of the phase signals so that they interact with each other, and temporally multiplexing plural data transmission periods different in time slot width and representing a transmission time period between its own node and the neighboring node based on respective oscillation periods of the phase signals. The calculator includes a state manager for managing states of phase signals for the own node and the neighboring node different in oscillation period, and prescribing an order relationship of time-slot allocation.

Abstract: The tracking of the phase of a received signal having a known preamble is accomplished by the steps of: initializing a phase-locked loop in accordance with estimated phase parameters, which are generated during an estimation interval by processing samples of the known preamble; delaying the preamble; generating phase error parameters by processing samples of the delayed preamble; and training the phase locked loop by tracking the phase-tracked signal in accordance with the tracking error parameters during a training interval after the estimation interval. The timing of the sampling is likewise trained in a closed timing loop in accordance with timing error parameters generated during the training interval after the timing loop has been initialized by estimated timing parameters generated during the estimation interval. The duration of the delay of the preamble is one-half the duration of the estimation interval.

Abstract: Improve efficiency of sampling of an A/D converter while suppressing power consumption. A packet receiving section receives six packets included in one frame transmitted from a base station, a sample timing control section shifts sample timing of the A/D converter by a half clock between former three packets and latter three packets out of six packets included in one frame.

Abstract: Systems and techniques to acquire a gated pilot signal by searching for a first gated pilot signal, deriving timing information from the search for the first gated pilot signal, and searching for a second gated pilot signal using the timing information. This can be implemented in a variety of fashions including a receiver with a searcher configured to generate a bit sequence, a correlator configured to correlate a received signal with the bit sequence, and a processor configured to detect a first gated pilot signal as a function of the correlation, derive timing information from the first gated pilot signal, and detect a second gated pilot signal by using the timing information to control the bit sequence generated by the searcher.

Abstract: An arrangement for synchronizing a transmission time of a digital data stream in individual high-frequency transmitters of a common-wave network operating according to an ATSC standard and transmitting identical data at an identical frequency. The stream generated in a master station is supplied to the transmitters as a periodic succession of data frames, and a setpoint transmission time is calculated in the transmitters from a synchronizing time stamp inserted into the data frames within the master station and from a time reference used in the master station and transmitters, while the transmission of the frames by the transmitter is determined by a system clock in the transmitters. The setpoint transmission time is compared with the actual transmission time determined by the clock, and the clock frequency is regulated by a regulating circuit so that the actual transmission time determined by the clock corresponds with the calculated setpoint transmission time.

Abstract: A data reception apparatus is disclosed. The data reception apparatus includes a strobe extractor for receiving a transmission signal and extracting a strobe signal from the transmission signal, the transmission signal including the strobe signal inserted between data signals and a clock signal following the strobe signal, the strobe signal having a different magnitude from a magnitude of a data signal, and the clock signal having an equal magnitude to the magnitude of the data signal, a clock recoverer for recovering the clock signal from the transmission signal, using the extracted strobe signal, and a sampler for sampling the data signals included in the transmission signal in response to the recovered clock signal. The probability of generating a timing skew error in the time interval between a clock signal and a data signal is minimized. Even though the level of a common component might change, the clock signal can be recovered accurately and the size of the clock recovery circuit can be reduced.

Abstract: A method of synchronizing two electronic devices connected by a wireless link with at least one path including a transmission channel and a reception channel. The two devices are included in a network, such as a mobile telephone network. Synchronization information is transmitted directly from one electronic device to the other, as a clock pilot signal, via the channels. After recovery, the clock pilot signal is used for synchronization of a reference frequency of the receiving electronic device.

Abstract: Methods and systems of generating a frequency switching local oscillator signal are disclosed. One method includes generating a reference clock signal, and clocking a counter with the reference clock signal. The counter controls selection of a one of a plurality of analog values stored in at least one of a plurality of periodic signal generators. The frequency switching local oscillator signal is generated by selecting an output of a one of the plurality of periodic signal generators.

Abstract: Methods and apparatus for rate control are provided. An isochronous circuit controls data transmission between a first device and a second device. The first device outputs a set of data packets to the isochronous circuit at a first data rate, and the second device pulls the set of data packets from the isochronous circuit at a second data rate. The isochronous circuit comprises a buffer, a rate calculator and a register. The buffer buffers the set of data packets bound to the second device through a USB. The rate calculator monitors occupation of the buffer to estimate the second data rate. The register is coupled to the rate calculator for storage of the second data rate. The first device may access the estimate of the second data rate from the register to update the first data rate.

Abstract: A radio transmitting apparatus and a radio transmitting method wherein a guard interval having a variable length is used to allow a radio receiving apparatus to precisely and easily obtain a symbol synchronization. In the radio transmitting apparatus, a GI adding part (103) adds a short GI or a long GI, which is longer than the short GI, to the head of each of data parts into which a modulated signal outputted from a modulating part (102) has been put by a predetermined number of symbols. In a case of adding the short GI, the GI adding part (103) copies the symbols of a portion of the data part including the rear thereof, and adds the copied symbols to the head of that data part, thereby providing a GI. In a case of adding the long GI, the GI adding part (103) copies the symbols of a portion of a second data part, which immediately follows the first data part, including the rear of the second data part.

Abstract: A communication system, communication method, transmitting apparatus, and receiving apparatus are disclosed herein. The communication system includes: a first clock correlating unit, adapted to correlate a clock to be transmitted with a clock of a data frame at a transmitter of a clock transparent-transmission network; and a second clock correlating unit, adapted to correlate a clock of a data frame at a receiver of a clock transparent-transmission network with a clock to be recovered. The method includes: correlating the clock to be transmitted with the clock of the data frame at the transmitter of the clock transparent-transmission network, and correlating the clock of the data frame at the receiver of the clock transparent-transmission network with the clock to be recovered.

Abstract: A phase interpolator includes a first circuit to generate a first signal having a first phase delay and a second signal having a second phase delay and a phase mixer. The phase mixer is coupled to receive the first and second signals from the first circuit. The phase mixer includes multiple current drivers each including a current driver input coupled to selectively delay one of the first or second signals and a current driver output coupled to output a phase delayed signal. The current driver outputs of the current drivers are coupled together to combine the phase delayed signals from the current drivers to generate an output phase delayed signal having a phase interpolated from the first and second signals.

Abstract: A synchronous clock signal can be adjusted relative to a data signal by decreasing a delay in the synchronous clock signal if a transition of a data signal occurs before a pulse of an offset clock signal which is delayed by one half cycle relative to the synchronous clock signal. The synchronous clock signal can be delayed if the transition of the data signal occurs after the pulse of the offset synchronous clock signal.

Abstract: Various embodiments of the present invention provide systems, circuits and methods that allow for switching between two or more multiphase clocks. As one example, a system for switching between multiphase clocks is disclosed. The system includes a multiphase clock multiplexer. The multiphase clock multiplexer receives a first multiphase clock and a second multiphase clock. The first multiphase clock includes at least a first phase clock and a second phase clock, and the second multiphase clock includes at least a third phase clock and a fourth phase clock.

Abstract: The present invention relates to a OFDM signal receiver device that performs weighting for branch metrics based on average noise power or signal-to-noise power ratio and conducts Viterbi decoding based on the result of the weighting. In the present invention, based on a demodulated signal, electric power corresponding to a noise component contained in the demodulated signal is calculated. A noise power signal corresponding to the result of the calculation is output from a noise power-calculating unit 8. Based on the noise power signal and a transmission channel characteristic corresponding to a subcarrier component that is output from an interpolation filter unit, a weighing factor for a branch metric is calculated by a weighting factor-calculating unit 9, and based on the weighting factor, the demodulated signal is decoded by decoding unit 10.

Abstract: The present invention relates to a demodulation device and a demodulation method, and its object is to demodulate subcarrier components utilizing estimated delay profiles to control the timing for performing a Fourier transform and the pass band of an interpolation filter used in interpolating transmission channel characteristics along a frequency axis so as to suppress unnecessary noise components, whereby an error rate after the demodulation is reduced. To achieve the object, in a demodulation device according to the present invention, a Fourier transform unit 1 performs a Fourier transform according to a timing signal and an interpolation filter unit 18 sets a pass band of a frequency interpolation filter used for interpolation along the frequency axis based on a signal corresponding to a maximum delay time, whereby the frequency band of a transmission channel characteristic corresponding to a subcarrier component is restricted when it is output.

Abstract: A Kerdock decoder of the present invention generates correlation reliability from a relation between correlation values to output together with a Kerdock-decoded map data. A map deciding unit receives a field sync signal, a field identifying signal, the Kerdock-decoded map data and the correlation reliability to identify whether a current field is an odd or even field and whether there is a map change in case of the even field. And, the map deciding unit decides a current map data by performing map acquisition and tracking according to the corresponding result.

Abstract: A digital broadcast system and a data processing method are disclosed. A data processing method of a digital broadcast transmission system includes delaying a reference time of a program clock reference (PCR) based on a size of mobile service data, when processing a broadcasting signal including main service data and the mobile service data, verifying a transport stream system target decoder (T-STD) model based on the PCR of the delayed reference time, and storing a packet of the main service data in an auxiliary buffer, when overflow of a buffer in the T-STD model is estimated as the verification result of the T-STD model.

Abstract: An integrated circuit isolator for providing data transfer of digital data signals across a voltage isolation barrier includes an integrated circuit package having a first plurality of input data pins on one side of the isolation barrier and a corresponding plurality of output data pins on the other side of the isolation boundary. First circuitry is associated with the first plurality of input data pins and second circuitry is associated with the plurality of output data pins. A communications interface provides across the voltage isolation barrier a first communications channel for communicating data from the first circuitry to the second circuitry and a second communications channel for communicating synchronization clock data from the first circuitry to the second circuitry.

Abstract: A method optimizes a selection of primary synchronization channel (P-SCH) sequences from an available set of P-SCH indices for a dedicated Multimedia Broadcast/Multicast Service (MBMS). The criteria for selecting P-SCH indices include coprimeness, frequency offset sensitivity, multipath sensitivity, cross-correlation property in the time domain, auto-correlation property in the time domain and computation complexity at the receiver.

Abstract: A phase determination unit in a signal processing circuit generates sampling clocks with different phases in a clock generator and sequentially provides them to an analog-to-digital convertor. Then, the phase determination unit obtains differences between each adjacent two signal levels in each sampled digital signal by use of the sampling clocks, and monitors a polarity change in the differences, extracts a more inappropriate phase for use in sampling from phases of the sampling clocks on the basis of the absolute values of the differences where the polarity change is detected, and determines an antiphase of the extracted phase as a phase of the sampling clock to be provided to the analog-to-digital convertor.

Abstract: Buffer circuitry receives data to be processed by electronic circuitry using a first clock signal associated with a first clock domain. The buffered data is output using a second clock signal associated with a second clock domain. The buffering of the data is associated with a buffering delay. Counting circuitry receives at a start count input a write timing signal associated with the first clock domain and with writing data to the buffer circuitry. The counting circuitry receives at a stop count input a read timing signal associated with the second clock domain and with reading data from the buffer circuitry. A count value accumulated between receiving the write timing signal and the read timing signal corresponds to the buffering delay. Control circuitry performs a control operation based on the count value.

Abstract: A BPSK type reception device that includes a decoder for decoding a digital input signal, first and second comparators for delivering a decoded data signal and a data capture clock signal also includes a clock generator for generating a replacement clock signal, first and second latches controlled by the replacement clock signal to store the data taken, respectively, from the decoded data signal and from a signal that represents the sign of the signal at the output of the decoder, and a selection circuit for capturing, at each pulse edge of a clock signal that is offset with respect to the replacement clock signal, either the stored data originating in the sign signal in the case of loss of the previous data capture clock pulse edge at the output of the clock comparator, or the stored data originating in the data signal.

Abstract: Disclosed is a method and an apparatus for generating a preamble sequence for an adaptive antenna system supporting a space division multiple access in an OFDMA communication system. Particularly, disclosed is a method for forming a preamble sequence identifying each of a plurality of mobile subscriber stations located within a cell or a sector of a communication system which includes a plurality of sub-channels assigned to the mobile subscriber stations, each of the sub-channels including a plurality of bins each of which includes n number of contiguous subcarriers in a frequency domain, the preamble sequence being transmitted before each of the sub-channels is transmitted, the method including the step of generating a preamble sequence by phase-shifting a predetermined sequence according to a predetermined phase shift sequence in the frequency domain.

Abstract: A wireless communication system is provided that detects a frequency burst (FB) through analysis of the autocorrelation function of received signals. The system can accommodate the relatively large frequency offsets that are associated with less expensive reference frequency crystals. In one embodiment, the system includes FB search hardware that operates in two modes, namely an FB location mode with narrowband interference (e.g. CW or continuous wave) detection and an FB location mode without such narrowband interference detection, depending on whether a CW signal (carrier or other narrowband interferer) is present or not.

Abstract: The DSP MSP invention provides an implementation of programmable algorithms for analyzing a very wide range of low and high frequency wave-forms. The DSP MSP comprises a synchronous sequential processor (SSP) for real time capturing and processing of in-coming wave-form including a programmable computing unit (PCU) for controlling SSP operations and supporting adaptive signal analysis algorithms. The DSP MSP further comprises a Sequential Data Recovery from Multi Sampled Phase (SDR MSP) for a receiver of an optical wave-form.

Abstract: For EMI reduction the current modulation profile is preferably used for frequencies over 1 GHz while the frequency deviation is increased at least to ±2.5 MHz and the modulation frequency is increased to at least 150 kHz, preferably about 260 kHz. In an alternative embodiment, the modification frequency is 1 MHz or greater so that a segmented spectrum is achieved. For clocks having basic frequency below 1 GHz, but having strong harmonics higher than 1 GHz, modulation of the foregoing is combined with the slower modulation currently used. EMI reduction is realized both at the lower and the higher harmonics.

Abstract: The recording condition setting device according to the present invention includes (i) a specific pattern detection circuit for detecting, as a specific pattern, one or more patterns having been set by recording information, from one or more decoded bit sequences generated from a reproduction signal received from an optical disc, (ii) a path metric difference classification circuit for classifying one or more specific path metric differences into one or more by-recording-information path metric differences corresponding to one or more by-recording-information patterns, said specific path metric differences being obtained by extracting one or more path metric differences corresponding to the detected specific patterns from path metric differences generated from the reproduction signal, and (iii) a recording condition setting circuit for setting the recording condition based on the classified by-recording-information path metric differences.

Abstract: A synchronization and detection method in a wireless device may include performing coarse detection and synchronization with respect to a received signal. The synchronization and detection method may also include performing fine detection and synchronization for acquisition of the received signal. Results of the coarse detection and synchronization may be used for the fine detection and synchronization. The synchronization and detection method may also include performing tracking mode processing when the acquisition of the received signal has been achieved.

Abstract: A circuit is designed with a measurement circuit (746) coupled to receive an input signal from at least one of a first antenna and a second antenna of a transmitter. The measurement circuit produces an output signal corresponding to a magnitude of the input signal. A control circuit (726) is coupled to receive the output signal, a first reference signal (?1) and a second reference signal (?2). The control circuit is arranged to produce a control signal in response to a comparison of the output signal, the first reference signal and the second reference signal.

Abstract: An electronic circuit exhibiting synchronization with an external synchronization signal, the electronic circuit comprising: an input connection arranged to receive a synchronization input signal; a triangular waveform oscillator operatively associated with the synchronization signal input connection and responsive to a condition of the received synchronization input signal to initiate a triangular waveform; and a pulse train generator operatively associated with the triangular waveform oscillator, the pulse train generator arranged to generate a plurality of pulse trains having a fixed non-zero phase relationship between them and a frequency responsive to the condition of the synchronization input signal.

Abstract: The invention provides a receiver comprising a data input and a strobe input. The strobe signal transitions whenever two consecutive bits in the data signal are the same. The receiver comprises combining means for generating a recovered clock signal from a combination of the data and strobe signals. The receiver also comprises a first sampling stage arranged to sample the data signal in dependence on the recovered clock signal, the first sampling stage comprising a plurality of sampling circuits and being arranged to obtain consecutive samples of the data signal using alternating ones of the sampling circuits. A second sampling stage is arranged to sample the data from the first sampling stage in dependence on a local system clock signal.

Abstract: A method and a device for detecting a synchronization signal with a high identification rate are provided, which are suitable for a wide-area Orthogonal Frequency Division Multiplexing (OFDM) system. The method and device can precisely detect information of a synchronization signal, without being interfered by transmission channels and noises in an external environment. Three sliding windows are used to obtaining a balance value as an offset value for the output signal of the method and the device. A peak position of the output signal is identified and then compensated for a delay caused by the length of one of the sliding windows. Such a position is an edge of the synchronization signal.

Abstract: A device for signal synchronization in a communication system, the device comprising a first detector configured to perform a first sliding correlation for a received signal and a pseudo-random noise (PN) sequence to obtain information on symbol timing, a second detector configured to identify a fractional carrier frequency offset (FCFO) using the information on symbol timing and the cyclic extension property of the PN guard interval (GI), a first multiplier configured to provide a first product by multiplying the received signal with the FCFO, and a third detector comprising a set of second multipliers configured to provide a set of second products by multiplying the first product with each of a set of phases related to integral carrier frequency offsets (ICFOs), a set of sliding correlators each being configured to perform a second sliding correlation for the PN sequence and one of the set of the second products, the set of sliding correlators providing a set of peak values, and a peak detector configured t

Abstract: The present invention provides an audio data sync format detecting circuit that can minimize both the hardware configuration software processing, and furthermore, has a large flexibility with respect to unknown formats. Audio data is written in sequence into a data register, where the audio data are units having a predetermined number of bits. Samples of the format that is the object of detection are written in sequence into a register. A comparator compares the data in the sample register and the data in the data register. A control circuit receives hit signals and outputs an interrupt signal to the controller, and the controller writes in sequence samples of the format that is the object of detection into the register each time an interrupt signal is received. When hit signal is continuously output a predetermined number of times, a match detection circuit outputs a format match signal.

Abstract: A frequency calibration apparatus and method are provided. A frequency calibration method includes determining a frequency band according to results of frequency comparisons between a synchronized reference signal whose phase is synchronized to a phase of a prescale signal and a divided signal, and performing a Phase Locked Loop (PLL) operation on a reference signal and the divided signal at the determined frequency band to lock the divided signal.