Abstract: A technique for operating a wireless communication device includes assigning a reference signal bandwidth to a reference signal. Cyclic shift control bits (associated with the reference signal) are then allocated based on the assigned reference signal bandwidth. The allocated cyclic shift control bits specify a cyclic shift associated with the reference signal.

Abstract: Circuitry is provided in a programmable logic device incorporating clock-data recovery circuitry on I/O channels to allow the use of otherwise unused noise-reduction circuits in the I/O channels, such as decision-feedback equalization (DFE) circuits, to cancel or minimize cross-talk with other channels or other sources of cross-talk. Selectable connections are provided to allow various potential sources of cross-talk to be programmably connected to the DFE circuits instead of unused CDR output taps. When a user finalizes a user logic design, the user can determine the sources of cross-talk and the unused taps relative to a particular channel, and programmably connect the sources to the DFE circuits corresponding to those unused taps. DFE coefficients may then be adjusted to cancel or at least minimize the cross-talk. Programmable time delays can be provided to adjust for clock differentials between the cross-talk source and the particular channel under consideration.

Abstract: Embodiments of the present invention include a frequency synthesizer comprising a first plurality of dividers receiving a first signal having a first frequency and generating a first plurality of divided signals and a frequency combination network including a plurality of mixers, the frequency combination network receiving one or more of the first plurality of divided signals and generating a plurality of synthesized signals having different frequencies. The frequency combination network may further include additional dividers and multiplexers for more flexibility in synthesizing different frequencies. In one embodiment, the frequency combination network is coupled to dividers in the feedback path of a phase locked loop. The present invention is particularly advantageous for synthesizing frequencies above one (1) gigahertz.

Abstract: A system and method are provided for holding the frequency of a non-synchronous communication signal in a clock and data recovery (CDR) device frequency synthesizer. The method initially acquires the phase of a non-synchronous first communication signal having a first frequency, and divides a first synthesized signal by a selected frequency ratio value, creating a frequency detection signal having a frequency equal to a reference signal frequency. In response to losing the first communication signal and subsequently receiving a second communication signal with a non-predetermined second frequency, the frequency ratio value is retrieved from memory based upon the assumption that the second frequency is the same, or close to the first frequency. Using a phase-frequency detector (PFD), the reference signal, and the frequency ratio value, a second synthesized signal is generated having an output frequency equal to first frequency.

Abstract: Methods and circuits for detecting variations in signal propagation rates within an electronic device, and for adjusting the output timing of the device in response to the variations in signal propagation rates. According to an embodiment of the invention, a signal may be propagated through an uncompensated delay chain and a compensated delay chain. If the signal passes through the compensated chain slower than through the uncompensated delay chain, then the device may delay a clock signal such that the output timing of the device will remain within the specification parameters. In contrast, if the signal passes through the uncompensated delay chain slower than through the compensated delay chain, the device may not delay the received clock signal such that the output timing of the device will remain within specification parameters.

Abstract: A parallel decoder for decoding a code division multiplexed (CDM) signal. The parallel decoder has two matched filters, both operating at a frequency equal to half the chip rate of the CDM signal. One matched filter correlates odd-numbered chips of the CDM signal with odd-numbered chips of the spreading code. The other matched filter correlates even-numbered chips of the CDM signal with even-numbered chips of the spreading code. The two resulting correlated signals are combined, and the decoded signal is obtained from the combined signal. This arrangement doubles the maximum possible chip rate of the CDM signal.

Abstract: The present invention relates to a linear time code (LTC) generator that is adapted to generate LTC data. The LTC generator comprises a rising edge detector that is adapted to detect a frame sync input corresponding to a beginning of a frame time of video data and to generate a first synchronization signal corresponding to the frame sync input and a frame length measurement block that is adapted to count a number of clock cycles in the frame time. The LTC generator further comprises a bit rate calculator that is adapted to determine a bit rate of the frame time based on the number of clock cycles in the frame time and a bit rate counter block that is adapted to generate a second synchronization signal corresponding to the bit rate.

Abstract: The phase locked loop (PLL) with adjustable phase shift is described. The PLL includes a voltage controlled oscillator which is capable of generating multiple phase shifted output signals, and multiple phase detectors capable of determining the phase differences between the output signals and a reference clock. The PLL further includes a weighting device capable of weighting the phase differences and generating a control signal for the voltage controlled oscillator.

Abstract: When data bursts are transmitted between a base station and a mobile receiver, a changeover is made between a plurality of modulation methods during an existing radio link for modulation of the data. For resynchronization of the receiver in the event of the changeover, synchronization information items are determined from a first part (ET) of the data burst modulated by a first modulation method, and are used for synchronization with a second part (ZT) of the data burst modulated by the second modulation method.

Abstract: A serial data communication system (10) comprises—a local clock generation device (12) adapted for generating a clock signal (16) with a duty cycle depending on a control signal (18), and—a serial data communication control device (14) adapted for generating the control signal (18) depending on the receipt of a serial data signal and for deriving a transmit and receive clock signal (20, 21) from the clock signal (16) received from the local clock generation device (12).

Abstract: A mobile station in a TDMA network can perform automatic frequency using burst in all or any slot in a control channel. This is achieved by identifying the training sequence of an arbitrary set of or all received bursts.

Abstract: A timing recovery loop includes a random walk filter counter for counting early, nominal and late arrivals of data transitions pulses of an input baseband signal waveform encoding a digital bit stream, and provides magnitude counts that are compared to a threshold value that when exceeded by the magnitude counts results in a delay adjustment of the generated adjusted timing pulses then remaining synchronized with the actual bit timing for maintaining bit timing lock. The adjusted timing pulses can then be used by a data detector for reliable data detection and reconstruction of the digital bit stream. The threshold value can be adaptively adjusted for reducing drop lock rates in the presence of changing channel environments.

Abstract: The disclosure relates to improved direct digital frequency synthesizers. A synthesizer in one embodiment is comprised of an accumulator that provides a phase signal and an interpolator having two or more interpolation polynomials. The polynomial that processes the phase signal is selected by comparing the phase signal to a threshold value. A reduced complexity digital circuit is provided for implementing the improved synthesizer.

Abstract: According to one embodiment, an information processing apparatus has a radio communications unit, and has a first mode in which communications are established at a first communication speed and a second mode in which communications are established at a second communication speed lower than the first communication speed, and includes a determining unit configured to determine whether or not the apparatus is in a predetermined state, and a control unit configured to lower the communication speed of the radio communications unit and shift the first mode to the second mode if it is determined by the determining unit that the apparatus is in the predetermined state in the first mode.

Abstract: In a communication system including nodes laid out in a grid, each node operates on a repetitive internal timing cycle, at certain phases in which the node transmits data and state variable signals. The state variable signals transmitted by a node indicate its internal phase and its position in the grid. The advance of the phase at each node is governed by a phase response function, which drives neighboring nodes whose data transmissions could collide out of phase with each other, and a synchronization alliance function, which brings certain nodes having positional relationships that preclude data collisions into phase with each other. A highly efficient data transmission timing pattern can thereby be established autonomously.

Abstract: An apparatus comprising a first multiplexer circuit (MUX) to receive a plurality of clock phase signals at a corresponding plurality of MUX inputs and to output a first clock signal and a second clock signal that are out of phase with each other, a phase delay circuit to receive the output of the first MUX and to generate adjusted first and second clock signals that have reduced phase error with respect to detected edges of incoming data, an output MUX to receive the adjusted first and second clock signals and to output a recovered clock signal, and a control circuit coupled to output MUX select inputs. The control circuit includes logic circuitry to select the first adjusted clock signal as the recovered clock signal and to select the second adjusted clock signal as the recovered clock signal when the first adjusted clock signal nears a phase limit due to drift of the detected data edges. Other devices and methods are disclosed.

Abstract: A transmitter sets a time length, determines a time point at which phases of frequency signals coincide within a range of the time length, defines a determined time point as a time reference point, aligns the phases of the frequency signals based on the time reference point, combines phase-aligned frequency, and transmits combined frequency signals to a receiver by the time length as the communication signals. The receiver receives the communication signals, extracts the phases of the frequency signals, obtains a time point at which the phases coincide, and determines an obtained time point as the time reference point.

Abstract: The method disclosed in the invention comprises setting a plurality of subcarrier position hypotheses for a received preamble according to a plurality of ideal subcarrier positions and the maximum amount of integer carrier frequency offset (ICFO), generating a plurality of preamble pattern hypotheses by retrieving the received preamble according to the subcarrier position hypotheses, calculating the correlation between the preamble pattern hypotheses and a plurality of specified preamble patterns, determining to which sector the received preamble belongs according to a correct preamble pattern, the specified preamble pattern having the highest correlation with the preamble pattern hypotheses, obtaining a correct subcarrier position according to the sector to which the received preamble belongs; and estimating the ICFO by calculating the offset between the correct subcarrier position and the subcarrier position hypothesis of the preamble pattern hypothesis having the highest correlation with the correct preamb

Abstract: A reception apparatus for receiving an OFDM signal having a plurality of pilot carriers that transmit predetermined pilot signals at predetermined symbols. The reception apparatus transforms the received OFDM signal to a frequency-domain OFDM signal, determines channel responses corresponding to the transmitted pilot signals for each of the pilot carriers among a plurality of carriers constituting the frequency-domain OFDM signal, determines, based on channel responses corresponding to first, second and third pilot signals transmitted sequentially in a same carrier, a channel response at a symbol between the second pilot signal and the third pilot signal, compensates a waveform distortion in the frequency-domain OFDM signal according to the channel response at the symbol between the second pilot signal and the third pilot signal and outputs the results.

Abstract: An adaptive equalizer system for use in a serial communication link uses timing information generated by a phase detector of a clock and data recovery circuit of the serial communication link and a frequency pattern of the recovered data to determine whether the data received over the serial communication link is over-equalized or under-equalized. The equalizer strength of the adaptive equalizer system is adjusted based on such determination.

Abstract: To provide a method for making a receiving-sensitivity control parameter for deciding the receiving sensitivity of an optical receiving circuit automatically follow the optimum position by using the jitter value of a binary-equalizing-data signal obtained by binary-converting an input signal as a parameter showing the quality of the input signal. A binary-equalizing-data signal output from a limiter amplifier and a clock extracted by a clock-extracting circuit are input to a jitter-detecting circuit. The jitter-detecting circuit outputs a voltage corresponding to the jitter value of the binary-equalizing-data signal. A control circuit receives an output of the jitter-detecting circuit and performs an arithmetic processing by using a DSP or the like, and controls the identification voltage of the limiter amplifier so that the jitter value of the binary-equalizing-data signal (output of jitter-detecting circuit) is minimized.

Abstract: A transmitting/receiving arrangement comprises a baseband module (1) and a radio-frequency module (3), which are connected to one another via a bidirectional data line (21) and a bit clock line (22) of a digital interface (2). In order to eliminate the influence of delay loops during the transmission of data in the opposite direction to the bit clock either the data bits are transmitted repeatedly or a bit clock frequency is set which is lower than the bit clock frequency for rectified transmission of bit clock signal and data signal.

Abstract: A user equipment (UE) for establishing a communication link comprising a first module for processing a received communication signal and generating an index value associated with a primary synchronization code within said communication signal; a second module for generating a scrambling code group number, a slot offset, and secondary synchronization code based on output provided by the first module; a third module for retrieving a primary scrambling code based on the scrambling code group number and slot offset; and a controller coupled to said first module, second module, and third module for controlling an a search frequency of the UE for establishing a communication link.

Abstract: Apparatuses and methods are disclosed herein for implementing dormant mode with paging in a WLAN. Power savings in the computing device and reduction in traffic across the network are achieved by requiring a computing device to inform the WLAN of its location only when it crosses a paging area boundary or is to receive IP traffic. Dormant mode with paging is implemented in a protocol that supports dormant functionality and paging functionality but does not itself provide methods or standards for implementing such functionality, such as the IEEE 802.11. The methods and apparatuses disclosed herein provide the methods needed to implement dormant mode with paging in such a protocol. Generally, the methods and apparatuses for implementing dormant mode with paging basically include (1) establishing paging areas; (2) communicating access group information to a computing device; and (3) locating a computing device.

Abstract: The present invention provides a method of processing a baseband signal including user signals transmitted by a plurality of users. The method includes applying frequency offset compensations to the baseband signal, thereby to form respective frequency-shifted baseband signals. Each frequency compensation shifts the baseband signal by a multiple of a selected frequency offset and each resulting frequency-shifted baseband signal includes frequency-shifted user signals. The method also includes assigning at least some of the frequency-shifted user signals to groups. Each group corresponds to one of the frequency compensations and the assignment is carried out so that each group includes frequency-shifted user signals that have an estimated frequency offset that lies within a range determined by the corresponding frequency compensation.

Abstract: Described is an apparatus for suppressing spurious spectral lines in a frame based bit-serial data stream, in which frames include payload data and frame markers. The apparatus includes means (16) for randomizing first frame marker elements (START) in a first position within each frame and means (18) for correlating second frame marker elements (STOP) in a second position within each frame with the randomized first frame marker element.

Abstract: A physical layer device comprises a first port that embeds a first clock into data transmitted over a first physical medium; a second port that embeds a second clock into data transmitted over a second physical medium; a first selection module that outputs the first clock to the first port based on one of a locally generated clock and a recovered clock; and a second selection module that outputs the second clock to the second port based on one of the locally generated clock and the recovered clock. A method comprises embedding a first clock into data transmitted over a first physical medium; embedding a second clock into data transmitted over a second physical medium; generating the first clock based on one of a locally generated clock and a recovered clock; and generating the second clock based on one of the locally generated clock and the recovered clock.

Abstract: A method and apparatus are disclosed for clocking a DSP at a frequency which is always a constant integer multiple of the fundamental frequency of the input analog signal. This invention applies in situations where the analog signal exhibits certain characteristics in which a fixed clock frequency is not desired, but rather what is needed is a clock which tracks the fundamental frequency of the analog signal, for example, a signal from a monophonic musical instrument or a polyphonic instrument being played one note at a time.

Abstract: A system and method for generating a clock signal having spread spectrum modulation. The method involves generating a clock signal by generating edge positions for edges of the clock signal from a digital representation of a timing for each edge to impart spread spectrum modulation to the clock signal. A programmable modulator is provided that generates digital values representing edge positions for edges of a clock signal based on at least one of a time-varying period value and a time-varying duty-cycle value. The programmable modulator may comprise a first circuit, called a period modulation circuit, that generates a time-varying digital period value, and a second circuit, called a duty-cycle modulation circuit, that generates a time-varying digital duty-cycle value. The time-varying period values and time-varying duty cycle values are processed to produce a digital edge position value that specifies an edge position for a clock signal.

Abstract: The invention provides a method and system for synchronizing a transmitter and a receiver wherein the transmitter generates phase difference information indicating a phase difference between an internal and an external clock, the phase difference information is transmitted to the receiver, and the receiver generates a clock signal dependent on the transmitted phase difference information.

Abstract: Remote frequency synchronization is achieved between two or more nodes in a packet-switched network using differential timestamps. A line is fit to multiple differential time values using a minimum delay principle. Frequency synchronization and/or absolute time synchronization between the two nodes may be achieved using one or both of uplink and downlink differential time values and fitting one or both of first and second lines to differential time values by different means of the minimum delay principle.

Abstract: A receiver includes a matched filter matched to a synch pulse and generates a matched filter output signal having peaks and valleys with one of the peaks corresponding to the synch pulse. An orthogonal filter is inversely matched to the synch pulse and generates an orthogonal filter output signal having peaks and valleys with one of the valleys corresponding to the synch pulse. A detector determines the synch pulse based upon a largest difference between the matched filter output signal and the orthogonal filter output signal.

Abstract: A digital filter operates on the basis of a first clock having a first frequency. A stereo modulator operates on the basis of a second clock having a second frequency higher than the first frequency and being asynchronous. The stereo modulator performs a predetermined process on output data of the digital filter. A frequency modulator operates on the basis of a third clock having a third frequency whose origin is the same as that of the second clock, and performs frequency modulation on an output signal of the second digital computing unit. A sampling converter receives output data having the first frequency from the digital filter, converts a sampling frequency to data synchronized with the second clock, and outputs the obtained data to the stereo modulator.

Abstract: There is provided a flexible transmission device capable of automatically setting an optimal point for a signal decision making with high accuracy, so that highly reliable high-quality signal regeneration control is achieved. A clock timing extraction circuit dynamically sets a frequency-dividing ratio based on the transmission rate of an input signal to perform a phase synchronization control so that there is a fixed phase difference between the input signal and an oscillation output, whereby clock timing based on the transmission rate can be extracted. A regeneration control circuit sequentially sweeps a voltage threshold level and the phase of the extracted cock with respect to the input signal and determines whether the levels of adjacent monitor points match, whereby a decision point within the valid zone of the eye pattern can be automatically measured and used as the optimal point for regeneration control.

Abstract: A process for providing a phase synchronization of a pilot aided carrier of an input digital signal z(k), the signal z(k) having signal fields of Ls symbol signals, namely a block of LP pilot symbol signals ZP(k) and a data field of (Ls?LP) data symbol signals Zd(k), and characterized for each signal field (l) by: extracting the pilot symbol signals ZP(k) and calculating an unwrapped phase estimate {circumflex over (?)}(lLs) over the pilot block of said signal field (1) and: interpolating said unwrapped phase estimates of successive signal fields (l, +1 . . .

Abstract: A technique for filter-enhanced clock synchronization is disclosed. In one particular exemplary embodiment, the technique may be realized by/as a method for filter-enhanced clock synchronization. The method comprises subjecting a clock error signal to a first exponentially weighted moving average (EWMA) filter to generate a first output signal, where the first EWMA filter comprises a first gain element. And the method further comprises subjecting the first output signal to a second EWMA filter to generate a second output signal, where the second EWMA filter comprises a second gain element and the second EWMA filter is coupled with a feedback loop having a delay element and a summing junction.

Abstract: A receiving apparatus includes a voltage-controlled oscillator to generate a local signal, a synchronous unit to receive the local signal and a reference clock, to divide the local signal by an average dividing number obtained by switching a plurality of dividing numbers by time-division, to compare a phase of the local signal with a phase of the reference clock, and to control the voltage-controlled oscillator in order to synchronize the compared phases, and a fixed divider to divide the local signal in a fixed dividing number and to output the divided signal.

Abstract: Provided is a self-calibrating time code generator and method for generating an accurate time code (e.g., an accurate IRIG waveform). The self-calibrating time code generator includes a phase-locked loop configured to provide a generated output signal based on a phase difference between an absolute time reference signal and a compensated generated input signal, an IRIG encoder configured to couple a present time value with the generated output signal to form an IRIG waveform, a delay difference indicator configured to provide a time interval value based on a comparison of corresponding pulse edges of the generated output signal and the IRIG waveform, and a numerical delay component configured to delay the generated output signal by the time interval value to form the compensated generated input signal used to time-align the IRIG waveform with the absolute time reference signal to form the accurate IRIG waveform.

Abstract: A serial interface connecting circuit includes a first IC (10) with a signal transmitting and a signal receiving terminal, a second IC (20) with a signal transmitting and a signal receiving terminal, and a connecting circuit (30) coupled between the first IC (10) and the second IC (20). The connecting circuit (30) includes a first photocoupler (16) having a first luminous element and a first optical receiving block, an anode of the first luminous element is coupled to a first power source (Vcc), a cathode of the first luminous element is coupled to the signal transmitting terminal of the first IC (10), a collector of the first optical receiving block is coupled to a second power source (Vdd) and the signal receiving terminal of the second IC (20), and an emitter of the first optical receiving block is coupled to ground.

Abstract: A base point of a communication frame is detected by only using a reception signal, and an offset amount from the base point and the like are estimated. A device includes: an extraction unit for extracting self correlation processing signals from a digital communication signal having a signal frame for synchronization by using a pair of correlation processing windows of a variable size; a correlation unit for performing self correlation processing to the self correlation processing signals extracted; a matching unit for performing pattern matching processing between the correlation-processed signal, obtained through the self correlation processing, and a reference signal; and a computation unit for estimating the base point of the signal frame and an offset of the digital communication signal with respect to the base point, based on distance information of the pattern matching processing.

Abstract: A method to receive channels in an undersampled broadband receiver comprising mixing bands of assigned channels with an oscillator to generate downconverted bands, wherein each assigned channel has an assigned unique identifying code. The method further includes undersampling the downconverted bands and determining if the unique identifying code associated with a desired channel is detectable. When the unique identifying code is detectable, the method further comprises detecting the unique identifying code associated with the desired channel. When the unique identifying code is undetectable, the method further comprises tuning the oscillator and detecting the unique identifying code associated with the desired channel based on the tuning.

Abstract: A method and apparatus for searching the synchronization signal of a next frame in encoded digital signal without the need of referring to a frame length indication signal. The encoded digital signal contains a plurality of frames, wherein each frame may have varying length and contain a synchronization signal. The method includes determining a search region, and locating the synchronization signal in the search region.

Abstract: A method of correlating a signal to a synchronization pattern is disclosed. The signal has a waveform with frequency and phase angle components that may be varied, at each repeated signal pulse, to communicate a change in a bit pattern of the signal. A synchronization pattern is generated using knowledge of phase rotation direction due to two consecutive bits in a synchronization key. The signal is compared with the synchronization pattern. It is determined whether the comparison of the signal and the synchronization pattern indicate a correlation between the signal and the synchronization pattern.

Abstract: An apparatus for transmitting signals over a signal line includes a transmitter with an output connectable to the signal line, for a synchronization signal in a power saving mode and a wanted signal in a normal mode of operation, wherein the synchronization signal has a reduced amplitude as compared to an amplitude of the wanted signal and has a periodic data pattern so that the synchronization signal permits maintaining an alignment of the synchronization signal and a reference signal in the receiver.

Abstract: Disclosed is a method for compensating for a residual frequency offset in an orthogonal frequency division multiplexing system comprising the steps of: a) performing a fast fourier transform for an input signal to convert the input signal into a serial signal; b) detecting signal power of the serial signal to control the passthrough a signal greater than a predetermined critical value; c) selecting each section of a quadrant for each passed signal; d) estimating a phase error in each section of the quadrant for one orthogonal frequency division multiplexing symbol with respect to the selected section of the quadrant; and e) frequency-oscillating a signal based on the estimated phase error, generating the input signal by multiplying an oscillated signal by a band-passed signal, and then returning to step a).

Abstract: An approach is provided for supporting carrier synchronization in a digital broadcast and interactive system. A carrier synchronization module receives one or more signals representing a frame that includes one or more overhead fields (e.g., preamble and optional pilot blocks and one or multiple segments separated by pilot blocks). The module estimates carrier frequency and phase on a segment by segment basis and tracks frequency between segments. Carrier phase of the signal is estimated based upon the overhead field. Estimates carrier phase of random data field are determined based upon the estimated phase values from the overhead fields, and upon both the past and future data signals. Further, the frequency of the signal is estimated based upon the overhead fields and/or the random data field. The above arrangement is particularly suited to a digital satellite broadcast and interactive system.

Abstract: The present invention provides an FFT window spread generating method used in the modulation of an OFDM system. When OFDM-modulated received signals each having a time length greater than or equal to an effective symbol length are demodulated by FFT processing using a spread FFT window, the spread FFT window makes use of received signals each having the time length greater than or equal to the effective symbol length. Spreading windows spread before and/or after the effective symbol length are provided. Received signals lying within the spreading windows are added to their corresponding received signals lying within the effective symbol length and different in time position by the effective symbol length, and the amplitudes of the added received signals are reduced to half respectively, thereby generating the spread FFT window.

Abstract: In a system for encoding, transmitting, and decoding data in real time, irrespective of the jittering in a transmission path and the encoding bit rate used, synchronization is established between encoder end decoder ends with ease and reliability in the present invention. A change of a difference ‘d’ between STC (output value of STC counter) at the decoder end and SCR extracted from an encoding stream (MPEG2-PS) is integrated over a given time. Depending on whether the integrated value is positive or negative, a determination is made whether the data processing speed at the decoder end is faster than the encoder end. When the integrated value is positive, the input clock frequency of the STC counter at the decoder end is reduced, and when the integrated value is negative, the input clock frequency thereof is increased.

Abstract: Difference between a received signal which is an OFDM modulated signal having a guard interval and a delayed signal acquired by delaying the received signal by time equivalent to a data interval is calculated, a reference signal of an FFT calculation window is generated based upon the acquired result of the calculation of the difference and a predetermined threshold and a boundary between symbols is detected. As a result, the boundary between symbols can be stably detected, compared with a method of detecting a boundary between symbols based upon the result of the correlation calculation of the guard interval and the demodulation of received data is also stably enabled in multipath phasing and ghost.

Abstract: A method, communication system and communication unit for synchronisation for multi-rate communication by transmitting a signal (FIG. 4A) having a synchronisation portion at a first, predetermined chip rate and containing an indication of chip rate used for a further portion; receiving the transmitted signal, recovering the indication from the synchronisation portion at the first, predetermined chip rate, and recovering information in the further portion at the chip rate indicated by the indication. This provides improved efficiency in supporting multi-chip rates.