Abstract: A wideband amplifier circuit provides high current gain and a wide bandwidth by employing only npn transistors, which have better high-frequency characteristics than those of pnp transistors, in the signal path. Wideband current amplification is achieved using npn transistors in a current-mirror configuration, with base-emitter voltage matching to permit the current gain to be easily set as a function of transistor area. The wideband amplifier circuit can also be used in a differential wideband amplifier configuration to obtain a combination of high current gain, wide bandwidth and wide output swing not obtainable with conventional differential amplifiers.

Abstract: Optoelectronic semiconductor devices which have a groove-shaped waveguide in an oxide layer provided on a silicon substrate are compact, easy to manufacture, and--when the waveguide comprises a non-linear optical material--applicable inter alia for frequency doubling of laser radiation. In known devices, scattering losses occur in the waveguide owing to the roughness of the groove which arises during etching of the groove. Here, the groove and a portion of the oxide layer are formed by local, preferably thermal, oxidation of the silicon substrate. The groove formed at the area of the oxidation mask has a smoother surface and as a result the waveguide has lower losses. When the device includes a GaAs/AlGaAs diode laser, it forms an efficient, compact, inexpensive and blue-emitting laser source which is suitable for use in an optical disc system. Preferably, the diode laser is situated in a deeper and wider further groove in the oxide layer.

Abstract: A semiconductor device with a semiconductor body (1) whose surface (4) is provided with a barrier layer (8) of Ti.sub.x W.sub.1-x, with 0.1<x<0.3. The barrier layer (8) is used, for example, between contact zones (3) of silicon or metal silicides provided in the semiconductor body (1) and conductor tracks (9) of aluminium provided on the surface (4) with the purpose of counteracting chemical reactions between silicon and aluminium. According to the invention, the barrier layer (8) is so deposited that in this layer the distance between the (100) lattice faces of tungsten is greater than 2.25.ANG.. It is achieved in this way that the barrier layer (8) has equally good or even better barrier properties as/than a Ti.sub.x W.sub.1-x layer which has been exposed to air for a few days. It is found that, if the barrier layer (8) is deposited by means of a sputter deposition process, the distance between the (100) lattice faces of W is determined by the voltage applied to the sputter target during deposition.

Abstract: A method of realizing an integrated circuit on a substrate (10) includes steps for forming a high electron mobility transistor (HEMT), including the realization of a superimposed structure (11) of layers on the substrate, among which are present at least a first layer (31) or channel of a material with a narrow bandgap and weakly doped, a second layer (22) or spacer of a material of wider bandgap and weakly doped, and a third layer (23) or donor of a material of wide bandgap and strongly doped, which layers are covered by a fourth layer (24) or Schottky layer, and the realization of an insulating zone completely surrounding the transistor relative to the other elements of the integrated circuit.

Abstract: A method of fabricating thin film structures on the surface of a transparent substrate (10) in which a light shielding pattern (20, 54) is provided adjacent the opposing substrate surface and in which deposited thin film layers are photolithographically patterned by directing radiation onto the light shielding pattern and by varying the angle of the exposing radiation for respective layers whereby the thin film layers are patterned differently while using the same light shielding pattern. Various thin film structures can be fabricated inexpensively and reliably using this approach together with standard processing techniques such as the use of temporary layers and lift-off procedures. In particular, by appropriate design of the light shielding pattern and selection of deposited materials, active matrix arrays, e.g. comprising MIMs or TFTs with associated conductors, for use in liquid crystal display devices can be produced.

Abstract: A method of manufacturing a device, preferably a semiconductor device, whereby a mask (3) with an opening (4) extending down to a bare body (1) is provided on a surface (2) of this body (1), after which a substance (5) is implanted into the body (1) through the opening (4), upon which the mask (3) is removed. The mask (3) is provided by depositing a first and a second layer (6, 7, respectively) on the surface (2), and these layers are provided with the opening (4), while the first layer (6) can be selectively removed relative to the material of the body (1), and the second layer (7) is of the same material as the body (1). Since the same material is used for the second layer (7) as for the body (1), the body (1) is not polluted with material from the mask (3) in the opening (4) during implantation.

Abstract: A method of manufacturing a semiconductor device in which a surface zone (3) adjoining a surface (2) is formed in a silicon semiconductor body (1) by local application of carbon and dopant atoms, the carbon atoms being provided by means of implantation (4). Halogen atoms are provided simultaneously with the carbon atoms by means of an implantation with ions of a carbon-halogen compound, after which a heat treatment is carried out such that non-bonded halogen atoms are removed from the surface zone (3). Such a method is suitable for making a surface zone (3) which has a greater bandgap than silicon. The surface (3) is suitable, for example, for making an emitter region of a heterojunction bipolar transistor (HBT).

Abstract: A semiconductor component (1a) has first and second insulated gate field effect devices (T1 and T2) formed within the same seminconductor body (2). The devices (T1 and T2) have a common first main electrode (D) and an arrangement (20) provides a resistive connection (20b) between a second main electrode (S2)of the second device (T2) and the insulated gate (G1) of the first device (T1). The second device (T2) is formed so as to be more susceptible than the first device (T1) to parasitic bipolar transistor action for causing, when the first and second devices (T1 and T2) are turned off and a voltage exceeding a critical voltage (V.sub.

Abstract: A programmable frequency divider circuit includes a prescaler which consists of p cascade-connected dividing cells, a cell of rank i in the cascade having a normal division factor 2 and also being programmable so as to divide by 3 the input frequency applied to the cell. Each cell of rank i supplies, as a signal enabling the programmed mode for the preceding cell of rank i-1, a signal which is referred to as a gating signal and which is calibrated as regards duration and position in time at the operating frequency of the cell i, the prescaler (PPSC) being associated with counting means (CNT) for producing a programmable division factor (R) which is equal to M.2.sup.p +N, where M is an integer number applied to the counting means (CNT), p is the number of cells of the prescaler (PPSC), and N is an integer number applied to the programming inputs of the prescaler (PPSC).

Abstract: A semiconductor device of the RESURF type with a lateral DMOST (LDMOST), comprising a semiconductor body (1) of substantially a first conductivity type and a surface region (3) of a second conductivity type adjoining the surface (2). The LDMOST comprises a back gate region (5) of the first conductivity type provided in the surface region (3), with a source region (6) of the second conductivity type in the back gate region (5) and a channel region (7) defined between the source region (6) and an edge of the back gate region (5). A drain region (8) of the second conductivity type is at a distance from the back gate region (5). A number of breakdown voltage raising zones (9) of the first conductivity type are provided between the back gate region (5) and the drain region (8).

Abstract: A JFET configuration is obtained whose pinch-off voltage can be set by means of mask dimensions, without process changes, and which is at the same time suitable for operation at very low and very high voltages by cascoding of a first JFET with a diffused or implanted channel which is pinched off in lateral direction, parallel to the surface of the semiconductor body, with a second JFET with a high breakdown voltage and a higher pinch-off voltage than the first JFET. To increase the breakdown voltage still further, the combination of the first and second JFET may be further cascoded, without process changes, with a third JFET which has a channel of the conductivity type opposite to that of the first and second JFET.

Abstract: A zener diode having a semiconductor body (1) with a surface zone (1') doped with more than 10.sup.18 atoms/cc, in which at least two regions (2, 3) are provided through diffusion, which regions have substantially the same concentration of doping atoms and adjoin a surface (4) of the surface zone (1') and form p-n junctions (5,6) with the surface zone (1'), a first region (2) having a smaller lateral cross-section and a smaller depth than a second region (3). Both regions (2, 3) are connected to a first connection electrode (7, 8) provided on the surface (4), and a second connection electrode (9), which is spaced apart from the regions (2, 3), is provided on the semiconductor body (1). The first region has a side edge (10) which is formed through lateral diffusion and which is at least partly spaced apart from the second region (3). A higher electric field is created locally in the junction (5) during operation of the zener diode owing to the side edge (10).

Abstract: Semiconductor device and method of manufacturing same, display device and support plate for same provided with such a semiconductor device. A semiconductor device having an insulating substrate on which a Schottky diode is formed between a metal layer and a semiconductor layer of polycrystalline or amorphous silicon extending over the metal layer is used inter alia in matrix display devices, such as LCDs. The Schottky diode forms part of a switching element of such a device and must have a low reverse current up to a reverse voltage of, for example, approximately 10 V. The known semiconductor device having Schottky diodes, in which the semiconductor material extends over a lateral surface of the Schottky metal, is found not to comply with this requirement. To overcome this deficiency a low leakage current is realized over a wide reverse voltage range due to the presence of a dielectric on the lateral surface of the Schottky metal. The dielectric suppresses the leakage current issuing from the lateral surface.

Abstract: A semiconductor device with at least one programmable memory cell which includes a bipolar transistor (T.sub.1) with an emitter (11) and a collector (12) of a first conductivity type and a base (10) of a second, opposite conductivity type. The emitter (11) and collector (12) are coupled to a first supply line (100) and a second supply line (200), respectively. The base (10) is coupled to writing means (WRITE) through a control transistor (T.sub.2). Reading means (READ) are included in a current path (I) which extends between the first supply line (100) and the second supply line (200) and which includes a current path between the emitter (11) and collector (12). In a preferred embodiment, the collector (12) is in addition coupled to the second supply line (200) via a switchable load (T.sub.5).

Abstract: A positioning device includes a table (5, 69), which is displaceable in two coordinate directions (X, Y) by means of Lorentz forces of electric linear motors over a base (3) and is guided over the base (3) by means of a static gas bearing, which has an air gap thickness independent of the coil systems and magnet systems (15-21, 37-43) in the motors. The positioning device is particularly suitable for the manufacture of masks with patterns for integrated circuits.

Abstract: A semiconductor body (2) has adjacent a first major surface (3) a first region (5) of one conductivity type part of which defines an active device area (6) of a power semiconductor device (7) having at least two electrodes (8 and 9 or 8 and 10) and active device regions (11) each forming with the first region (5) a pn junction (11a) extending to the first major surface (3). A protection device (12) formed by a series-connected array of semiconductor rectifying elements (13) is provided on an insulating layer (14) on the first major surface (3). The protection device (12) is connected between at least two electrodes (8 and 9 or 10) of the power semiconductor device (7) so as to break down to cause conduction between the two electrodes when the voltage across the protection device (12) exceeds a predetermined limit.

Abstract: It is usual in high-voltage integrated circuits to provide one or several breakdown-voltage-raising rings at the edge of a high-voltage island in the form of surface zones of the conductivity type opposite to that of the island. According to the invention, the function of these rings is locally taken over by one or several zones forming part of a circuit element and also provided with a breakdown-voltage-raising edge. Since the breakdown-voltage-raising zones are locally omitted alongside the island insulation, a major space saving can be achieved.

Abstract: In CCD's, the major part of the dark current is caused by surface states. This dark current is disturbing, especially in image sensors, because the sensitivity of the camera is limited thereby. When according to the invention the integrating gates are varied periodically, the subjacent surface parts of the - buried - channel being brought periodically into inversion and into depletion, while maintaining the charge-containing capacity, a considerable reduction of the dark current can be obtained. In image sensors, voltage variation preferably occurs during the fly-back time.

Abstract: An integrated circuit includes a variable-gain amplifier having a first transistor with a load arranged as an inverted and controlled by a first signal of a first frequency, and also having a branch comprising a capacitance in series with a transistor which is arranged as a variable resistance and whose impedance is modulated by a second signal of a second frequency. In this circuit the variable-gain amplifier comprises a second transistor with a load arranged as an inverter and disposed in series with the first transistor and its load between this load and a d.c. supply, in such a manner that the two inverter transistors share the same current, the second inverter being controlled by the output of the first inverter, and the impedance modulated by the second signal is coupled to a node between the load of the first inverter transistor and the second inverter transistor in order to modulate the gain of the latter.

Abstract: A method and an arrangement are described by means of which a pitch in a signal (s(t)) can be determined. In fact the probability density function (pdf) of the pitch is determined as a function of frequency. A pitch can then be derived from this probability density function. First a frequency spectrum A(f) is derived from a signal portion situated in a specific time interval T. Then, the probability contribution (K.sub.1i, K.sub.1j, . . . . ) is determined for a number of frequency components (f.sub.i, f.sub.j, . . . ), stating the relative probability that a pitch at a frequency (f.sub.1) is the result of a frequency component (f.sub.i, f.sub.j, . . . ). The probability contributions (K.sub.1i, K.sub.1j, . . . ) are multiplied by one another to obtain a probability density (K.sub.f1). This procedure is iterated for successive frequencies (f.sub.2, . . . ) to obtain at least a second probability density. The probability densities K.sub.f1, K.sub.f2, . . .