Abstract: A logic processor-controlled data display apparatus having a display memory in which pixel data representing text for display is stored in bit-map form. The pixel data is produced for each display from character data stored in a background memory. When the character data is stored in bit-map form it can be read directly from the background memory bit-by-bit and written into the display memory as the pixel data. However, this process takes a large number of programme steps, so that the transfer of the data is relatively stow. The present invention provides for the storage in the background memory of character data in the form of machine code sub-routines. The sub-routine for a character contains instructions for identifying the shape-defining pixels (dots) of the character relative to a base dot position and the sub-routine is run to write these pixels into the display memory following location of the base dot position in the display memory.

Abstract: A method of manufacturing mask alignment marks on an active surface of a semiconductor substrate (12) is disclosed, in which first, at least one layer (13) of a material resistant to oxidation is formed on the active surface, after which by a local etching of this layer, zones (15') for isolation by a field oxide, are defined simultaneously with the alignment marks (17'). There are formed, after the local etching of the layer (13) of anti-oxidation material while using the remaining parts of the anti-oxidation layer as a mask, depressions (26) at the substrate surface of a given depth at least at locations containing the alignment marks, which locations are designated as alignment windows (18) and the surface of the substrate is then exposed within the windows, and finally a thermal oxidation step is effected to obtain the field oxide (19'), during which the alignment marks (18) are simultaneously covered by oxide (24).

Abstract: Integrated circuits are arranged in a regular pattern on a semiconductor wafer. The circuits are separated from one another by kerf areas. These kerf areas are used to accommodate test structures from which process parameters can be derived. Because the surface area of these kerf areas is comparatively small, it is necessary to minimize the number of bonding pads or connection terminals for these test structures. The test system is extended with a multiplex circuit whereby a test structure can be selected from the test system and which connects one of the various test structures to always the same connection terminals. Furthermore, using one stimulus which is applied to a connection terminal and which is also the stimulus for the test structure whose response is to be measured, the desired test structure is selected.

Abstract: A circuit arrangement compensates for changes of pulse-duration in a binary signal. These changes of pulse-duration are the consequence of parasitic reactances in the signal path of the binary signal. A compensating circuit, which owing to its simplicity is particularly suitable for integrated circuits, is characterized in that a signal is inverted by an input inverter (I1) after it has passed through the signal path, then passes through a copy (NA) of the signal path, and is inverted once again by an output inverter (I1). If the signal path and its copy are integrated on a single chip, an adjustment of the copy (NA) need not be performed. Particularly advantageous--because of its cost-effectiveness--is the implementation of the above circuit in switching networks which are realized as integrated circuits. For each output of the switching network only a single copy (NA) will then be necessary.

Abstract: For manufacturing an implantation mask on a semiconductor surface which is provided with grooves, a positive photoresist is provided on the surface. Portions of the photoresist which are to form the implantation mask are illuminated in a first step and rendered insoluble in the developer in an image reversal step. The photoresist is then illuminated without mask and developed, so that the portions not illuminated during the first step are removed. The implantation mask thus obtained has a receding profile, the openings at the area of the grooves becoming wider in the direction of the bottom of the grooves.

Abstract: A method of manufacturing a semiconductor device whereby a layer (12) containing Co or Ni is deposited on a surface (2) of a semiconductor body (1) bounded by silicon regions (3, 4, 5, 6) and regions of insulating material (8, 9), after which the semiconductor body (1) is heated during a heat treatment to a temperature at which the Co or Ni forms a metal silicide with the silicon (3, 4, 5, 6), but not with the insulating material (8, 9). On the surface (2) of the layer (12) containing the Co or Ni, according to the invention, a layer of an amorphous alloy of this metal with a metal from a group comprising Ti, Zr, Ta, Mo, Nb, Hf and W is deposited, while furthermore the temperature is so adjusted during the heat treatment that the layer (12) of the amorphous alloy remains amorphous during the heat treatment.

Abstract: An image detector includes a surface sensitive to photon radiation which is protected from the external environment by a transport window with an internal diopter and an external diopter which is integral with a housing and is placed in front of the sensitive surface. In order to eliminate the phenomenum known as "blooming" due to parasitic reflections causes by intense radiation, the window is formed by a transparent, nondiffusing medium which attenuates photon radiation, with the internal diopter of the window being at a distance from the sensitive surface which is smaller than or at most equal to several times the resolution distance of the detector. Additionally, the external diopter is sufficiently far removed from the sensitive surface such that the first reflection of the radiation coming from a source of maximum radiation will have a level, on the sensitive surface, which is lower than that of the direct radiation coming from a source of minimum radiation which is to be detected.

Abstract: A positioning device has two transport arms for alternately transferring plate-shaped objects from a storage position into an operational position. The transport arms are each displaceable by means of a separate manipulator, so that a quick exchange of the objects is possible. The manipulators each comprise two parallel Y-guides which are fastened to a frame, and an X-guide which is displaceable along the two Y-guides, while the transport arms are each displaceable along one of the X-guides. The positioning device is used in an optical lithographic device for alternately placing masks on a mask support. A machine frame of the optical lithographic device to which the mask support is fastened is coupled to the frame of the positioning device by spring members. To render an accurate positioning of the masks on the mask support possible, the optical lithographic device is provided with an optical sensor system which is coupled to an electronic control unit for controlling the positioning device.

Abstract: Radiation-emitting semiconductor diodes are used inter alia in information processing systems as diode lasers or LEDs. Such a radiation-emitting semiconductor diode including an active layer situated between two cladding layers, which layers each include a mixed crystal of III-V semiconductor materials, atoms of different elements, often having a certain degree of ordering, being present on at least one sublattice. An example is an InGaP/InAlGaP diode laser which emits at 670 nm and is highly suitable for various applications. There is a particular demand for diodes which have a high maximum operating temperature at a given wavelength. According to the invention, the composition of the semiconductor material of the active layer is so chosen that this layer has a compression strain, while the atoms of the different elements have a less orderly distribution at least in the semiconductor material of the active layer.

Abstract: The invention provides a signal processing device including sampling means (31, 41, 32) for sampling an input signal in the form of charge carrier packages and a shift register (4) having an input region (41) to which a signal sample is offered during operation, and provided with transport means (2) for transporting the signal sample to an output region (42) of the shift register. The device according to the invention is capable of adapting itself to the frequency with which the input signal is sampled in such a way that the storage of the increase in signal samples which accompanies an increase in the sampling frequency does not require additional space. For this purpose, according to the invention, the shift register comprises a transport channel (4) in which an electron-hole liquid can exist. The sampling means (31, 41, 32) are capable of sampling the input signal in the form of electron-hole droplets (71 . . .

Abstract: An IF amplifier/log detector with a modular architecture includes a plurality of voltage amplifiers, a plurality of rectifiers, a plurality of voltage-to-current converters and a current summing circuit. Each amplifier has a first differential transistor pair driven by a first current proportional to the temperature to fix the gain. Each converter includes a second differential transistor pair driven by a current proportional to the temperature and inversely proportional to a process parameter, and a third differential transistor pair driven by a third current inversely proportional to the process parameter. In this manner a circuit having improved performance with variations in temperature and process parameters is obtained.

Abstract: A semiconductor device includes a semiconductor structure (D3) of parallel semiconductor layers on a semiconductor substrate (1), in which layers a mesa (12) is formed which includes only a portion (D1) of the semiconductor layer structure (D3). Such devices as are useful in optoelectronic devices in which the mesa (12) forms part of a semiconductor diode laser or a radiation waveguide. During cleaving of such devices, for example for the formation of a mirror surface, damage often arises near the mesa (12), which is undesirable. The mesa (12), which projects from the device, is also easily damaged during further manipulation of the device. The semiconductor layer structure (D3) includes a sunken region (11) within which the semiconductor layer structure (D3) is at least partly recessed in the substrate (1), while the mesa (12) is positioned within the boundaries of the sunken region (11). As a result, the mesa (12) is also recessed at least partly, and thus is at least partly protected.

Abstract: A semiconductor device is provided with a polyimide film 21 between the encapsulating synthetic resin 16 and the passivating film 20. If a material having a high hardness (E-modulus.gtoreq.1.0.multidot.10.sup.10 Pa) is selected as the polyimide, the number of defects caused by variations in temperature is reduced.

Abstract: A method and group of masks for manufacturing a device whereby illumination of a photoresist layer (4) takes place by subsequent illumination through partial masks (1) and 2). During these separate illuminations, complementary scales of grey are obtained in the connection region (7, 8) of the images (5, 6), the total illumination in the connection region (7, 8) being nevertheless complete. According to the invention, good results are obtained when the partial masks (1) and (2) have complementary transparency gradients in the ends (9, 10) corresponding to the scales of grey.

Abstract: A method of manufacturing a semiconductor body (1), whereby a carrier wafer (2) with an optically smooth main surface (3) is provided with a semiconducting top layer (4) in that the main surface (3) is brought into contact with an optically smooth main surface (5) of a monocrystalline semiconductor wafer (6), a permanent bond being formed, after which the semiconductor wafer (6) is made thin by means of a grinding process and a polishing process in that order. The semiconductor wafer (6) is made thin in the polishing process in that the exposed main surface (9) of the carrier wafer (2) is made wear-resistant, and in that then the carrier wafer (2) bonded to the semiconductor wafer (6) is arranged between two plane polishing discs (10) and (11) provided with a polishing liquid, upon which these polishing discs (10, 11) and the exposed main surfaces (8, 9) are moved relative to one another.

Abstract: Integrated circuits sometimes include, in addition to the connection surfaces provided for normal operation, additional test pads through which test signals can be put in or read out during testing on the wafer. These connection pads require additional space on the semiconductor slice, so that fewer circuits can be accommodated on a semiconductor slice of a given size. It is proposed to provide the test pads in a row at one or two sides of the circuit and connect them with two adjoining circuits. The cut for separating the chips after manufacture and the test can then take place through these test pads, so that the latter require only little extra space. Advantageously, adjoining circuits will have layouts which are one another's mirrored images.

Abstract: A storage module which can be inserted into a data processing apparatus, such as a dictating apparatus, includes an at least partly random accessible storage device (5) for the storage of digital data signals and an access device for serially accessing storage locations in the storage device. The storage device requires refreshing and cooperates with a refresh device (6) for refreshing data signals stored in the storage device (5). The refresh device (6) includes additional storage devices (11) which store, upon writing in the storage locations of the storage device (5), start addresses and stop addresses from the access device (9), under the control of a control circuit (12). Only storage locations which are situated between a pair of start and stop addresses are timely refreshed via a refresh control device (20). Such a storage module is preferably used in conjunction with the dictating apparatus for the storage of speech signals.

Abstract: The invention relates to a microcircuit card having a card support with a cavity in which a cover foil (200) is fixed, which foil (200) includes a circuit support (20) and at least one circuit (210) arranged on an inner surface of the circuit support (20) facing towards the interior of the cavity, the circuit (210) being arranged opposite a first portion of a bottom of the cavity. The circuit support (20) includes on its lower surface at least one energy transfer element (220) arranged opposite a second portion of the bottom of the cavity at a distance from the first portion.

Abstract: A semiconductor device (1) includes a circuit having at least one transistor Tr1 and first and second electrodes (30) and (32). A protection element (20) having a device region (21) forming a pn junction (23) within the semiconductor body (10) and covered by an electrode layer (21c) is connected via an electrode (27) to one (30) of the first and second electrodes for providing a conductive path between the first and second electrodes (30) and (32) when a voltage above a threshold voltage is applied to the first electrode (30). The electrode layer (21c) forms with at least part (21a) of the device region (21) a potential barrier (B) for causing the conductive path provided by the protection element (20) to pass from the electrode (27) to the pn junction (23) at least partly via the device region (21) of the protection element (20) thereby increasing the resistance of the path to the pn junction (23).

Abstract: A semiconductor memory includes non-volatile memory cells which can be electrically programmed and erased by means of tunnel current (EEPROM) with a floating-gate transistor, the cell being arranged in memory cell groups of n lines and m columns each, n cells being connected in series, which serial connection forms the bit line for the columns of a cell block. The control gate is common to m memory cells of one line of the cell block situated next to one another and forms the word line for the line in the memory cell group. The floating gate does not extend over the entire width of the channel, so that in each memory cell a parallel transistor is formed which is connected in parallel to the floating-gate transistor and is controlled only by the control gate, which parallel transistor is conducting during reading for each non-selected cell. As a result, the problem of over-erasing is solved even in the case of short access times, without an additional access transistor being required.