Abstract: A method of manufacturing a semiconductor device with a semiconductor element which includes a semiconductor zone (19) situated below an electrode (18) and adjoining a surface (5) of a semiconductor body (1), which semiconductor zone substantially does not project outside the electrode (18) in lateral direction. The electrode (18) is here formed on the surface (5) of the semiconductor body (1), after which semiconductor material adjoining the surface (5) and not covered by the electrode (18) is removed by an etching treatment, whereby the position of the semiconductor zone (19) below the electrode (18) is defined.

Abstract: A single-to-differential converter for generating two balanced output signals from one single-ended input signal includes first (3) and second (6) output terminals for providing the balanced output signal, a first transistor (M1) having a control electrode coupled to an input terminal (4) for receiving the input signal, a first main electrode coupled to a supply voltage terminal (1) for receiving a supply voltage and a second main electrode coupled to the first output terminal (3). A second transistor (M2) is provided having a control electrode coupled to a bias voltage terminal (5), a first main electrode coupled to the control electrode of the first transistor (M1) and a second main electrode connected to the second output terminal (6). A diode-connected third transistor (M3) is provided having its main current path coupled to the first output terminal (3), and a diode-connected fourth transistor (M4) is provided having its main current path connected to the second output terminal (6).

Abstract: A multiple-input arbiter first mutually correlates groups of input signals for identifying a particular group, which includes at least one input signal that is a candidate for gaining the overall priority. Thereupon the priority winner is determined in that particular group. Such a hierarchical processing lends itself to an architecture wherein the processing in groups is implemented by cascaded levels of uniform logic blocks. The decomposition in uniform logic blocks considerably simplifies the design of arbiters that process large numbers of input signals.

Abstract: An analogue current memory arrangement includes an input (30) and an output (33). A first (coarse) current memory cell (T31,S31,C31) senses the input current during clock phase .phi.1a and reproduces the sensed current during clock phases .phi.1b and .phi.2. A second (fine) current memory cell (T32,C32,S32) acts as a current source during phase .phi.1a when a reference voltage (VR) is applied to the gate of transistor (T32). The second current memory cell senses the difference between the input current and the output of the first current memry cell during phase .phi.1b and reproduces the sensed current during phase .phi.2.During phase .phi.2 the input switch (S30) is opened and the output switch (S34) is closed causing the combined outputs of the first and second current memory cells to be fed to the output (33).(FIGS. 3 and 4).

Abstract: Optoelectronic semiconductor devices including a semiconductor body with a semiconductor substrate and a substantially plane semiconductor layer structure of III-V semiconductor materials situated thereon, a mesa being formed at a surface of the semiconductor body by means of selective deposition and forming part of an optoelectronic element, are important components in optical communication and optical disc systems or bar code readers. The optoelectronic element often is a semiconductor diode laser, but may alternatively be, for example, a radiation guide. A disadvantage of the known devices is that parasitic deposition takes place next to the mesa during the selective deposition. In addition, the device often contains so-called cleavage steps near the mesa. Another disadvantage is that the height and flatness of the upper side of the mesa are not accurately controllable.

Abstract: A method of manufacturing a semiconductor device whereby on a surface (1) of a semiconductor body (2) a layer comprising aluminum (3) is deposited, in which conductor tracks (4) are etched, between which then an insulating aluminum compound (6) is provided in that a layer of such a material (7) is deposited, which layer is then removed down to the conductor tracks (4) by a bulk reducing treatment, upon which an insulating layer (11) is deposited into which contact windows (13, 14) are etched down to the layer comprising aluminum (4) for local contacting of the conductor tracks (4). The conductor tracks (4) are provided with a top layer (8) before the deposition of the insulating aluminum compound, and the aluminum compound is removed again down to the top layer (8) after the deposition by means of a polishing treatment which is practically incapable of removing the top layer (8).

Abstract: A semiconductor device with a semiconductor body (1) is provided with a first and a second bipolar transistor (T1, T2, respectively) in a cascode configuration, in which the semiconductor body (1) comprises, in that order, a collector region (10) and a base region (11) of the first transistor (T1), a region (12) which forms both an emitter region of the first transistor (T1) and a collector region of the second transistor (T2), a space charge region (13), and a base region (14) and emitter region (15) of the second transistor (T2), while the regions form pn junctions with one another which extend parallel to a main surface (2) of the semiconductor body (1). The base region (14) and the emitter region (15) of the second transistor (T2) adjoin a main surface (3) of the semiconductor body (1).

Abstract: A semiconductor device in which a capacitor (2) is provided on a surface (10) of a semiconductor body (3) with a semiconductor element (1) in which a lower electrode (11), an oxidic ferroelectric dielectric (12) and an upper electrode (13) are provided in that order, the upper electrode not covering an edge of the dielectric, after which an insulating layer (14) with superimposed metal conductor tracks is provided. According to the invention, the edge of the dielectric (12) not covered by the upper electrode (13) is coated with a coating layer (14, 20, or 30) practically imperviable to hydrogen, after which the device is heated in a hydrogen-containing atmosphere. Heating in a hydrogen atmosphere neutralizes dangling bonds which arise during deposition of the conductor tracks on the insulating layer, while the coating layer protects the dielectric from attacks by hydrogen. The semiconductor device then has a shorter access time.

Abstract: If the process were to be changed for optimizing the injection of hot electrons into the channel of the memory transistor in the manufacture of an integrated circuit having an embedded EPROM, this could lead to degradation of the transistors in the logic, in particular in the case of channel lengths below 1 .mu.m. To prevent this, a process is presented by which the non-volatile memory is optimized without the properties of the logic being affected. For this purpose, a first series of steps is performed in which first the floating gate is defined, followed by the source/drain implantation and a side-wall oxidation for obtaining an oxide spacer on the sides of the floating gate. During these steps, the region of the logic to be formed is uniformly protected against implantation and oxidation by the same poly layer from which the floating gate is made.

Abstract: An integrated circuit has an interconnection pattern which is recessed in the insulating layer, for example, an oxide layer. A groove is etched in the insulating layer corresponding to the metal pattern by means of a mask which is the inverted image of the interconnection pattern during manufacture. Etching is continued until contact windows are fully opened. To prevent the oxide between the contact windows also being removed, an etching stopper layer is provided in the oxide layer. A layer already present in the process may be used for this etching stopper layer, for example, a polycrystalline silicon layer, so that extra process steps are made redundant.

Abstract: A semiconductor body (1) has a first region (2) of one conductivity type adjacent one major surface (3). Second and third regions (5 and 6) of the opposite conductivity type are provided within the first region (2) adjacent the one major surface (3) and an insulated gate structure (80) overlies a conduction channel region (9) between the second and third regions (5 and 6) for providing a gateable connection along the length (L) of the conduction channel region (9) between the second and third regions (5 and 6). The insulated gate structure (80) has a gate insulating region (81) and a gate conductive region (82) extending on the gate insulating region (81) and up onto a relatively thick insulating region (4) adjoining the gate insulating region (81).

Abstract: It is known to bring the surface into the inverted state in CCD imaging devices with buried channels during the integration period in order to keep the dark current low (All Gates Pinning). The desired potential profile, with wells in which the charge is integrated bounded by potential beers, is obtained through the use of a two-phase structure with a doping profile in the channel or with a gate oxide having thickness differences. Owing to limiting conditions which hold for the clock voltages used for charge transport, serious limitations are imposed on the depth of the potential wells and thus also on the charge storage capacity of the pixels. This disadvantage is counteracted by the operation of the device not as a two-phase but, for example, as a four-phase CCD according to the invention, whereby a d.c. shift is present between the clock voltages for compensating the built-in, comparatively great potential differences described above.

Abstract: A semiconductor body (3) has a first region (4) of one conductivity type adjacent one major surface (5). A first masking layer (6) comprising at least one first mask window (6a) spaced from a second mask window (6b) is defined on the surface (5). Opposite conductivity type impurities are then introduced through the first masking layer (6) and a second masking layer (8) which is selectively removable with respect to the first masking layer (6) is subsequently provided on the first masking layer and patterned to leave a mask area (8a) covering the first mask window (6a). The semiconductor body (3) is then etched through the second mask window (6b) to define a recess (9) extending into the first region (4) while leaving the introduced impurities beneath the masked first mask window (6a) to form a relatively highly doped second region (7).

Abstract: A method of manufacturing a semiconductor device having a field effect transistor and a device manufactured by this method in which a high packing density can be realized. The field effect transistor includes a gate electrode (31,41) which is separated from a channel region by a first insulating layer (8) and is entirely surrounded by insulating material. For this purpose, a conductive layer (9) which is to form a gate electrode (31,41) is covered with a second insulating layer (10) and both layers are subsequently given the same pattern at least at the area of the channel region. As a result, the gate electrode (31,41) is covered at the upper side with a portion of the second insulating layer (10). The gate electrode (31,41) is laterally insulated by the provision of a third insulating layer (13) which is subsequently etched back anisotropically, whereby a portion (14) thereof remains intact afterwards alongside the side wall of the gate electrode (31,41).

Abstract: A lateral Semiconductor-On-Insulator (SOI) device includes a substrate, a buried insulating layer on the substrate, and a lateral semiconductor device such as an LDMOS transistor, an LIGBT or a lateral thyristor on the insulating layer. The semiconductor device (in the case of an LDMOS transistor) includes a source region, a channel region, an insulated gate electrode over the channel region, a lateral drift region formed of a continuous layer of a lightly-doped semiconductor material on the buried insulating layer, and a drain contact region which is laterally spaced apart from the channel region and connected to the channel region by the drift region. A buried diode is formed in the substrate, and is electrically coupled to the drain contact region by a portion of the drift region which extends laterally in the region between the drain contact region and the buried diode.

Abstract: Radiation-emitting semiconductor diodes in the form of a laser diode or in the form of an LED form important components in data-processing systems. There is a particular need for diodes which emit in the visible part of the spectrum, which have a low starting current and which can be manufactured at low cost. A radiation-emitting semiconductor diode comprising above the active layer a cladding layer and a GaAs contact layer, into which a mesa-shaped strip is etched, and provided on the upper and the lower side with a conductive layer, which forms outside the mesa-shaped strip a junction forming a barrier with a subjacent semiconductor layer, partly satisfies the aforementioned requirements.

Abstract: A lateral Semiconductor-On-Insulator (SOI) device includes a substrate, a buried insulating layer on the substrate, and a lateral semiconductor device such as an LDMOS transistor, an LIGBT, a lateral thyristor, or a lateral high-voltage diode on the insulating layer. The semiconductor device (in the case of an LDMOS transistor) includes a source region, a channel region, an insulated gate electrode over the channel region, a lateral drift region on the buried insulating layer and having a substantially linearly graded lateral doping profile, and a drain region which is laterally spaced apart from the channel region and connected to the channel region by the drift region. In order to substantially improve the breakdown voltage of the device, typically a high-voltage power device, while reducing the "on" resistance, the lateral drift region is formed of a wide bandgap semiconductor material such as silicon carbide.

Abstract: An integrated circuit comprising a cascode current mirror and a bias stage for biassing the cascode current mirror, the cascode current mirror comprising, between an input terminal (11) and a supply voltage terminal (14), a first cascoded MOS transistor (21) and a first cascode MOS transistor (22) and, between an output terminal (12) and the supply voltage terminal (14), a second cascoded MOS transistor (23) and a second cascode MOS transistor (24).

Abstract: Very thin tunnel oxides are used in conventional non-volatile memories to obtain a sufficiently strong tunnelling current to or from the floating gate. Usual thicknesses of the tunnel oxide lie in the 8-10 nm range.The invention renders it possible to use tunnel oxides of a much greater thickness, for example of the order of 20 nm, for comparable tunnelling current values. According to the invention, the tunnelling effect is enhanced by implantation of a heavy, high-energy ion, for example As, into a comparatively thin poly layer of the oxide. During this, Si atoms are propelled from the polylayer into the oxide, so that the oxide is enriched with Si, which causes a major change in the tunnelling characteristics. The same oxide which functions as a gate oxide elsewhere may be used for the tunnel oxide.

Abstract: A charge-coupled device has a series register (A) having charge storage electrodes (3a) for defining charge storage wells and charge transfer electrodes (3b) for transporting charge between the charge storage wells and a parallel section (C) having channels (1a,1b) extending transversely of the series register (A). The parallel section (C) has charge storage electrodes (11a,12a,13a . . . Na) spaced apart along the channels, (1a,1b) to define a respective charge storage well with each channel to provide a respective row of charge storage wells extending transversely of the channels and has charge transfer electrodes (12b . . . Nb) for transferring charge between adjacent rows of charge storage wells, and a transfer gate (T1) for transferring charge between the series register (A) and an adjacent row of charge storage wells defined by the channels (1a,1b) and a first charge storage electrode (11a) of the parallel section.