Abstract: A semiconductor device with a monocrystalline silicon body (1) is provided with a dielectric layer (2) with contact holes (3) through which the silicon body (1) is contacted with an aluminum metallization. To avoid undesirable separation of silicon, a discontinuous nucleus layer (5) of a metal nobler than silicon is formed on the silicon body (1) in the contact holes (3) preceding the provision of the metallization (4). Metals such as palladium and copper may be used to form the discontinuous layer.

Abstract: The invention relates to a memory having a line decoder provided with a Darlington-type switching stage. When the deselection time T.sub.1 of a line is notably shorter than the intrinsic switching time T.sub.3 of a memory cell (M11 . . . Mnp), a discharge current I.sub.D is temporarily applied to the lower line conductor (1' . . . n') of the line (L1 . . . Ln) which is deselected. To achieve this, the current source I.sub.D is connected to said lower line conductors (1' . . . n') via delay circuits (RL1, DL1 . . . RLn, DLn) having a time constant T.sub.2 which is smaller than T.sub.3 and at least equal to T.sub.1.

Abstract: A circuit arrangement for adjusting the bit rates of two signals of which the higher bit rate signal is structured in frames, includes a buffer memory (2), a write counter and a read counter (6, 8) as well as a phase comparator (7) and a control circuit (10). With these modules the bits of the lower bit rate signal are arranged in the frames of the higher bit rate signal. In addition to these bits negative or positive stuff bits are also inserted in the frames. In order to avoid jitter when the lower bit rate signal is recovered at the receiver end, the phase different between the two signals is determined more accurately. This effected with a counter (55, 56) whose count is applied to the phase comparator (7) to determine the digits after the decimal point for the phase difference.

Abstract: A thin-film ROM device includes an array of open circuit and closed-circuit cells (5 to 8) formed from a stack of thin films (12,21,22,23,11) on a glass or other substrate (10). The semiconductor films (21,22,23) may be of hydrogenated amorphous silicon. At least one of the semiconductor films (21,22,23) is removed from some of the closed-circuit cell areas (5,7,8) before depositing the next film. In this way, at least a second type of thin-film diode (MIM, MIN, MIP) is formed having a different conduction characteristic to that of a first type (NIP), so increasing the information content of the ROM array. A lower semiconductor film (23) can be readily etched away from the lower electrode film (11) by a selective etching treatment in which the electrode film (11) acts as an etch stop. By monitoring emissions during plasma etching, an upper semiconductor film (21 or 22) can be removed from a lower semiconductor film (22 or 23).

Abstract: A method of manufacturing a semiconductor device whereby an spacer is formed from a second layer in a fully self-registering manner after a layer portion of a first layer has been formed. For this purpose, the second layer and a masking layer are provided in that order, which masking layer has a greater thickness next to the layer portion than above it. The portion of the second layer situated above the layer portion and the spacer to be formed is then exposed in that the masking layer is etched back over at least substantially its entire surface. A portion of the masking layer then remains next to the layer portion, which masking layer portion is sufficiently thick for adequately protecting the subjacent portion of the second layer against the treatment which is subsequently carried out and by which the etching resistance of at least the top layer of the exposed portion of the second layer is increased.

Abstract: A method of manufacturing a semiconductor device whereby a layer (3) containing aluminium is deposited by means of a sputter deposition process on a surface (1) of a semiconductor body (2) which is placed on a holder (21) in a reaction chamber (20). The semiconductor body (2) is cooled down to a temperature below 150 K. during the deposition process. A smooth, flat layer with a good step coverage is deposited in this way.

Abstract: A distributed threshold voltage TFT has a first FET and a second FET connected in series with the first point between the first and the second FET via a series circuit of a first capacitance and a second capacitance. The gate of the second FET is connected to the junction point between the first and the second capacitance and to the gate of the first FET via a non-linear resistance with a low R.sub.on and a high R.sup.off. Leakage currents can be kept very low in this DTV FET without an extra external voltage and/or without extra doping.

Abstract: Source (51) and drain (52) of a thin-film transistor (TFT) are formed from a conductive layer (5) using a photolithographic step (FIG. 3) in which the gate (4) serves as a photomask. In accordance with the invention the insulated gate structure (3,4) is formed at the upper face of the channel-forming semiconductor film (2), i.e. remote from the transparent substrate (1). The semiconductor film (2) may be annealed to high-mobility polycrystalline material before depositing the gate structure (3,4) and the overlying conductive layer (5). In this way, high speed TFTs can be formed due to a combination of low gate-to-drain and gate-to-source capacitances and the provision of the transistor channel in the high quality semiconductor material adjacent to the upper face of the film (2). Preferably ultra-violet radiation (20: FIG.

Abstract: The transfer gate between the master section and the slave section in a flip-flop circuit includes a circuit for reducing the sensitivity to slow clock edges and clock skew. This is accomplished by prolonging the transfer time for data from the master to the salve section of the flip-flop circuit.

Abstract: A circuit which responds to the application of a pulse to its input (6) by generating a pulse at its output (3), the output pulse having a minimum duration T and being extended by the remaining length of the input pulse should the input pulse be still present at the end of the time T, comprises a pair of semiconductor switches (1,2) connecting the output (3) to points (5,4) carrying respective logic levels. The input pulse closes the first switch (1) and also inhibits a gate circuit (9). The resulting logic level on the output (3) closes the second switch (2) after delay by T in a delay circuit (13) and transmission through the gate circuit (9), thereby restoring the original logic level. The instant when this occurs coincides with the presence of the delayed output pulse at the output (14) of the delay circuit and the absence of the pulse at the arrangement input (6). A hold circuit circuit (15) may be provided for holding the logic level currently present at the output (3).

Abstract: A transferred electron effect device has a semiconductor body with an active region (2) of n conductivity type formed of a semiconductor material having a relatively low mass, high mobility conduction band main minimum and at least one relatively high mass, low mobility conduction band satellite minimum, and an injection zone (3) adjoining the active region (2) for causing electrons to be emitted, under the influence of an applied electric field, from the injection zone (3) into the active region (2) with an energy comparable to that of the relatively high mass, low mobility, conduction band satellite minima of the active region.

Abstract: A semiconductor body (1) defines at least one active device. In the example shown in FIG. 1 complementary n channel and p channel IGFETs (10 and 20) are provided. An electrically conductive region, which may form the gate conductive region (101 and 102) of the insulated gates (11 and 21) of an IGFET, is provided on a first major surface (2) of the semiconductor body (1) and is encapsulated within a covering insulating region (300,400). An area (100a) of the electrically conductive region (101 and 102) contacts a relatively highly doped semiconductor region (50) provided adjacent the one major surface (2) and electrical contact is made to the electrically conductive region (101 and 102) via a conductive track (205) provided on the first major surface (2) and a conductive path provided by the relatively highly doped semiconductor region (50).

Abstract: A circuit arrangement for optionally amplifying one of two signals (from 2 or 6 respectively) in which at least one of the signals is supplied via a switchable signal path interruption which is inhibited when no signal is applied thereacross, and to which in this state a signal voltage is applied to both ends, which is associated with the signal to be amplified and which has already been amplified, respectively. When such a structure of a circuit arrangement is used, no damage to the circuit structure can occur, even when a signal path is interrupted in normal operation.

Abstract: A semiconductor device is formed by a semiconductor body (1) having a substrate (2) on which is provided a channel-defining region (10) extending between input and output regions (20) and (21). The channel-defining region (10) has a channel layer (11) forming a heterojunction (12) with at least one barrier layer (13) to form within the channel layer (11) a two-dimensional free charge carrier gas (14) of one conductivity type for providing a conduction channel (14) controllable by a gate electrode (25). A potential well region (30) is provided between the substrate (2) and the channel-defining region (10).

Abstract: A method of manufacturing a semiconductor device includes forming field oxide regions (17) in a surface (1) of a silicon body (2) through oxidation, which body is provided with an oxidation mask (15) formed in a layered structure provided on the surface with a lower layer (4) of silicon oxide, an intermediate layer (5) of polycrystalline silicon and an upper layer (6) of a material including silicon nitride in which windows (8) are etched into the upper layer. The intermediate layer is etched away inside the windows and below an edge (10) of the windows, a cavity (11) is formed below the edge, and a material including silicon nitride is provided in the cavity. The material including silicon nitride is provided in the cavity while the surface of the silicon body situated inside the windows is still covered by a layer of silicon oxide, preferably with the lower layer of the layered structure.

Abstract: An integrated circuit includes a sense amplifier which has an equalizing effect on voltages on the inputs of the sense amplifier, in particular during readout of the sense amplifier. The sense amplifier includes a parallel connection of a first and second current branch, each current branch including a control transistor, the source of which is connected to a relevant input, and the gate of which is connected to the drain of the control transistor in the other current branch, and a load transistor, whose gate receives a selection signal being connected in each said current branch in series with the control transistor. During readout, the gate of the load transistor is driven so as to make the channel of the load transistor conductive.

Abstract: A transferred electron effect device (1) has adjacent its cathode contact region (3) an injection zone (60) defining a potential barrier (P) for causing electrons to be emitted, under the influence of an electric field applied between the cathode and anode contact regions (3 and 4), into the active region (5) of the device with an energy comparable to that of a relatively high mass, low mobility satellite minimum (L) of the active region (5). The anode contact region (4), active region (5), injection zone (60) and cathode contact region (3) are grown sequentially, for example using molecular beam epitaxy, on a substrate which is then selectively removed to expose the anode contact region. A heat sink (70) is provided in thermal contact with the anode contact region (4). Providing the heat sink (70) in thermal contact with the anode contact region (4) rather than the cathode contact region (3) enables a significant increase in rf output power.

Abstract: A gate array circuit includes a row of consecutively arranged n-channel transistors and an adjacent row of p-channel transistors. Both rows are composed of at least three subrows with two subrows of narrow transistors and one subrow of wide transistors, of which the channel width is at least three times the width of the narrow transistors. The gate electrodes are common to the three subrows. Preferably, the wide subrow is arranged centrally between the narrow subrows. This construction affords the advantage of a very high density and a very high flexibility in designing the functions to be realized.

Abstract: The invention relates to an integrated circuit having a vertical transistor. According to the invention, a transistor having a current amplification .beta. considerably higher than a conventional transistor is obtained due to the fact that the emitter (5) of the transistor has a thickness and a doping level such that the diffusion length of the minority charge carriers injected vertically into the latter is greater than or equal to the thickness of the emitter (5) and the emitter contact region is so small that during operation the total current of minority charge carriers injected from the base into the emitter region is much smaller than the current density of minority carriers injected from the base into the emitter region under the emitter contact region multiplied by the total surface area of the emitter region.

Abstract: A circuit including an adjusting control (e.g. a potentiometer) which has two end connections and a slider which is adjustable for setting different resistance ratios. The two end connections of the potentiometer are each connected to one of two connections of a microprocessor and the slider is connected to one connection of a capacitor. The other capacitor connection is connected to a predetermined potential. To each of the two microprocessor connections at least one controllable switch is connected for optionally connecting a first potential (V1) or a second potential (V2) to the relevant microprocessor connection. The microprocessor executes a program run in which the capacitor, which has previously been brought into an initial charge state, is recharged first via one resistance section (R1) and then via the other resistance section (R2) of the potentiometer.