Abstract: The efficiency of semiconductor cathodes based on avalanche breakdown is enhanced by using ".delta.-doping" structures. The quantization effects introduced thereby decrease the effective work function. A typical cathode structure has an n-type semiconductor region and a first p-type semiconductor region, with the n-type region having a thickness of at most 4 nanometers.

Abstract: A power integrated circuit includes a substrate with an overlying epitaxial surface layer of opposite conductivity type. A semiconductor power device, such as a high-power diode or lateral MOS transistor, is located in the epitaxial layer and forms a p-n junction diode with the substrate. The power integrated circuit also includes a separate semiconductor well region in the epitaxial layer, in which one or more low-power semiconductor circuit elements are formed. In order to minimize the problem of latch up in the low-power circuit elements due to the injection of minority carriers from the substrate, the power integrated circuit is provided with a collector region and an isolation region between the power device and the well region having the low-power circuit elements.

Abstract: A semiconductor body has a surface structure (10) with an insulating layer (11) through which is formed an opening (12) defining a side wall (13) of insulating material bounding an exposed surface area (14a) of a region (14). An activating layer (15) is provided on the exposed surface area (14a) and the side wall (13) of the opening (12), and electrically conductive material deposited on the activating layer (15) to form an electrically conductive region (16) in the opening (12).

Abstract: An integrated memory includes a sense amplifier which has a parallel connection of a first and a second current branch, each current branch including channels of a control transistor and a load transistor which are coupled via a junction point, the junction points in each current branch being cross-wise coupled to the gates of the load transistors in the other current branch, and the junction points constituting outputs of the sense amplifier. The control and load transistors are of the same conductivity type, with each load transistor being connected in a source-follower configuration with its associated control transistor. As a result, the control transistors will be operative in the saturation region at all times and can be driven to full output, so that an integrated memory incorporating the invention is faster.

Abstract: A method of manufacturing a semiconductor device in which a thin buried silicide layer is formed by implantation includes the step of first forming an amorphous layer by implantation, which layer is then converted into the buried silicide layer by a heat treatment. A sufficiently thin buried silicide layer, of about 10 nm thickness, can be obtained in this manner, and the resulting structure is suitable, for example, for the manufacture of a metal-base transistor.

Abstract: The invention relates to a photocoupler comprising a light emitting element and a light receiving element, the light emitting element having a first and a second electrode in electrical contact with a first and a second contact pin, respectively, by means of which the light emitting element is fixed in position, the light receiving element having a third and a fourth electrode in electrical contact with a third and a fourth contact pin, respectively, by means of which the light receiving element is fixed in position. The light emitting element and the light receiving element are situated opposite one another and enveloped in a first solid and transparent layer, surrounded at least in part by a second solid layer provided in such a manner as to reflect the light.

Abstract: An integrated semiconductor device which forms an optoelectronic switch and includes: a directional coupler structure in which one of the guides receives the input light power and the other guide is formed by multiple quantum wells, which structure is so dimensioned that in the zero-bias state the switch is in the crossover state, and switching control means.The structure includes layers which form at least one PIN structure in which the waveguide consisting of multiple quantum wells constitutes an intrinsic region I, and the control means include means for reverse-biasing of the PIN structure which supplies the negative feedback so that switching from one state to the other is initiated by a change in the level of the luminous power injected into the input waveguide.

Abstract: An integrated circuit has an internal supply voltage with a positive temperature coefficient, as a result of which the switching rate and the degree of "hot carrier stress" are less sensitive to temperature. By using a reference voltage source having positive temperature coefficient, the normal effects of increasing temperature on switching rate and "hot carrier stress" are compensated for, thus stabilizing circuit operation as a function of temperature. The reference voltage source is incorporated within a voltage converter which is already present in the circuit, to achieve a compact and efficient configuration.

Abstract: A nonvolatile trench memory device such as an EEPROM is made by a method which permits an extremely compact and simple configuration due to the use of precise and efficient self-alignment techniques. Oxide-capped polysilicon mesas, formed integrally with the control gates, form the word lines of the memory device, while drain metallization lines contact drain regions of the device and extend over the oxide-capped word lines to form the bit lines. The resulting device is extremely compact, since the self-aligned process permits tighter tolerances and the unique polysilicon mesa/oxide cap construction permits a more compact configuration.

Abstract: A lateral trench-gate bipolar transistor device includes spaced-apart, surface-adjoining, laterally-oriented anode and cathode regions. A channel region at least partially surrounds the cathode region, and a gate region is provided adjacent to, but insulated from, the cathode region and the channel region. The gate region extends in a substantially vertical direction adjacent the cathode region and the channel region in order to induce a substantially vertical conduction channel in the channel region of the lateral device during operation. The gate region can advantageously be provided in a trench surrounding the transistor device, with a trench-shaped gate dielectric layer being provided on the trench sidewalls and floor to insulate the gate from the remainder of the device. Devices may be fabricated in an epitaxial surface layer, which may be provided either directly on a semiconductor substrate, or else on an intervening insulating layer.

Abstract: A semiconductor memory having non-volatile memory cells which can be electrically programmed and erased by means of tunnelling current (EEPROM) with a floating-gate transistor, the cells being arranged in memory cell groups of n lines and m columns each, n cells being connected in series, which serial connection forms the bit line for the columns of a cell block, while the control gate is common to m memory cells of one line of the cell block situated next to one another and forms the word line for the line in the memory cell group. The regions (injector regions) of the n cells of a column of a memory cell group situated below the gate oxide are interconnected and thus form a programming line which is separated from the source and drain zones of the floating-gate transistors. The result is a reduction in the programming voltage to be applied, since the programming voltage applied to each cell of a column is independent of the programming condition of the cells of a column.

Abstract: A photosensitive device includes a semiconductor body (1) having a first region (2) of one conductivity type adjacent a given surface (3) of the body with a second region (4) of the opposite conductivity type surrounding the first region (2) so as to form with the first region a main pn junction (5) terminating at the given surface (3), the main pn junction (5) being reverse-biassed in operation of the device. One or more further regions (6) of the one conductivity type surround the main pn junction (5) adjacent the given surface (3) so that each further region (6) forms a photosensitive pn junction (17) with the second region (4), the further region(s) (6) lying within the spread of the depletion region of the main pn junction (5) when the main pn junction (5) is reverse-biassed in operation of the device so as to increase the breakdown voltage of the main pn junction (5).

Abstract: A charge-coupled device includes a parallel section of parallel channels which are situated next to one another and are mutually separated by limitation zones, and a single readout register coupled thereto. The readout register is provided with clock electrodes in a multi-layer wiring system, the electrodes of the upper layer belonging to a common phase and being constructed as a continuous track which extends over the other electrodes. In the bottom wiring layer, electrodes are formed which are each associated with a limitation zone between the parallel channels and which have a length which is at most equal to the width of the limitation zones, and which also belong to a common phase, so that narrow-channel effects are avoided. The invention is of particular importance for CCD image sensors.

Abstract: A first device region (10) of one conductivity type adjacent one major surface (1a) of a semiconductor body (1) has a relatively highly doped subsidiary region (11) spaced from the one major surface (1a) by a relatively lowly doped subsidiary region (12). A second device region (20) of the opposite conductivity type within the subsidiary region (12) has an intrinsic subsidiary region (21) and an extrinsic subsidiary region (23,24) surrounding the intrinsic subsidiary region (21) forming respective first and second pn junctions (22,25) with the relatively lowly doped subsidiary region (12). A third device region (30) of the one conductivity type is formed within the intrinsic subsidiary region (21) surface (1a).

Abstract: A semiconductor body (100) has a first device region (20) of one conductivity type forming with a second device region (13) of the opposite conductivity type provided adjacent one major surface (11) of the semiconductor body (100) a first pn junction (40) which is reverse-biassed in at least one mode of operation. A floating further region (50) of the opposite conductivity type is provided within the first device region (20) remote from the major surfaces (11 and 12) of the semiconductor body (100) and spaced from the second device region (13) so that, in the one mode, the depletion region of the first pn junction (40) reaches the floating further region (50) before the first pn junction (40) breaks down.

Abstract: A buffer circuit for buffering an applied reference voltage at a low output impedance. The buffer circuit includes an input transistor which is coupled to an external reference voltage and to an external reference current, and a voltage-to-current converter for applying less or more current to an output terminal of the buffer circuit. This provides a substantially temperature-independent and stable buffer circuit which consumes very little quiescent current.

Abstract: Each memory cell of an electrically-programmable semiconductor memory has a field-effect transistor with a charge-storage region. Efficient and fast injection of hot carriers into the charge-storage region is achieved by vertical punch-through of a depletion layer to a buried injector region, by application of programming voltages to a control gate and to the surface of the punch-through region. Non-injected carriers are removed via at least the transistor drain during the programming. A well-defined punch-through region can be obtained with a higher-doped boundary region at at least one side of the punch-through region to restrict the lateral spread of the depletion layer(s) and prevent parasitic connections. This permits closer spacing of the injector region to other regions of the memory cell, e.g. source and drain regions, and the injector region may adjoin an inset insulating field pattern.

Abstract: A voltage-to-current converter in MOS technology includes a signal resistor formed by a channel of a MOS signal transistor (11, 12, 13, 14) with a source electrode and a drain electrode which form terminals of the channel. A gate electrode is provided for connecting a gate voltage (V.sub.g) for adjusting the resistance of the channel and a bulk electrode is provided for connecting a bulk voltage (V.sub.b), and a supply is provided for supplying source, drain, gate and bulk voltages to the electrodes, for non-saturated operation of the signal transistor. The supply includes control circuitry (30) for controlling the bulk voltage in response to the gate voltage. Consequently, the third-order distortion of the voltage-to-current converter is reduced.

Abstract: When using a laser programmable fuse, a circuit should be 100% stable both before and after the fuse is blown. So far no CMOS circuit can be 100% stable without drawing a constant current. With the "Master fuse Enable" scheme one fuse circuit (master fuse) draws current while disabling all other fuse circuits on-chip. Thus giving 100% stability and reducing power consumption on a chip where no fusing has been done. If, however, one wished to use the rest of the fuses, then the master fuse is blown and all fuse circuits now become active and draw current.

Abstract: In an integrated circuit in which the capacitances of a pair of capacitors are arranged to be in a ratio k by choosing the areas of corresponding plates of the two capacitors to be in this ratio, and the plates are shaped so that the total lengths of their boundaries are also in this ratio so as to reduce the sensitivity of k to manufacturing tolerances, this sensitivity is further reduced by arranging that the ratios between the numbers of 90.degree. corners exhibited by the respective plates, and the numbers of 270.degree. corners exhibited by the respective plates, are each also substantially equal to k. To make this possible an aperture is arranged to be present in each plate.