Abstract: A lithographic device with a lithographic irradiation system (1, 13) which is fastened near a lower side to a mounting member (5) of a frame (7). The device is provided with a unit (65) which is formed by a positioning device (37), with which an object table (21) arranged below the irradiation system (1, 13) is displaceable, and by a support member (35), over which the object table (21) is guided by means of an aerostatic foot (31). In an operational position, the unit (65) is coupled to a carrier (67) by means of coupling members (73), the carrier (67) being suspended from the mounting member (5) by means of suspension elements (79, 81, 83), so that the unit (65) is arranged between lower frame supports (25) of the frame (7) and a compact construction is obtained.The unit (65) can be rotated from the operational position to an end position, in which the unit (65) is entirely outside the frame (7) and is easily accessible for maintenance, by means of a rotation mechanism (87) and a swivel mechanism (89).

Abstract: A circuit arrangement (12, 13) for the electronic level control of a sound signal includes an amplifier circuit (14), the gain of which can be controlled in dependence on a variable direct control voltage, and a voltage-adjusting stage (15) for generating the variable direct control voltage. The amplifier circuit is formed by a CMOS inverter (14), of which the supply voltage connection (21), is supplied with the variable direct control voltage, generated by the voltage-adjusting stage (15), as supply voltage for the CMOS inverter (14). The CMOS inverter (14) is operated, in dependence on the direct control voltage, below the knee-point voltage in its starting region in which the gain of the CMOS inverter (14) decreases, and additionally the dynamic output impedance of the CMOS inverter (14) increases, with decreasing direct control voltage.

Abstract: An Erasable and Programmable Read Only Memory (EEPROM) cell is provided with an insulated control gate and an insulating floating gate formed in a trench in a semiconductor body. A surface-adjoining drain region is provided alongside an upper portion of a sidewall of the trench, while a source region is provided alongside a lower portion of the trench sidewall, with a channel region extending along the sidewall of the trench between the source and drain regions. The EEPROM cell is programmed by hot electron injection through the sidewall of the trench alongside the channel region, and is erased by Fowler Nordhiem tunneling through a corner region in the bottom of the trench by creating a localized high electric field density in the corner region. In this manner, a highly compact, efficient and durable EEPROM cell is obtained.

Abstract: An integrated semiconductor device, including an insulated-gate field effect transistor biased to a constant level, has a drain-source current characteristic as a function of the gate-source voltage which exhibits a negative transconductance zone beyond a maximum, the slopes of the characteristic on both sides thereof being substantially symmetrical so that two values of the gate-source voltage which are symmetrical with respect to said maximum correspond substantially to the same value of the drain source current, and in that the transistor comprises biasing means ensuring that its operating zone is situated in the region of said characteristic around said maximum.

Abstract: An element for use in an electrical circuit includes sub-region (11) and a second sub-region (12), which regions can contain a charge carrier gas (6) at least during operation and are separated from one another by an insulation zone (13). The insulaton zone (13) is locally interrupted by a barrier zone (15) which presents a potential barrier to the charge carriers. The first sub-region (11) is provided with a first connection (21) for deriving the potential from it. The second sub-region (12) is provided with two connections (22, 23) by means of which a current (I) can be passed through the second sub-region (12). The potential of the first sub-region (11) is found to be proportional to at least substantially the square of the current (I) passed through the second sub-region. This renders the element particularly suitable for an electrical circuit in which such a proportionality is desired.

Abstract: A semiconductor device and a circuit suitable for use in an intelligent power switch include an insulated gate field effect transistor (IGFET) (T2) and a power semiconductor switch (T1). The insulated gate field transistor IGFET (T2) is provided by a semiconductor body (6) which has a first region (7) of one conductivity type adjacent a given surface (6a) of the semiconductor body with the first region (7) forming at least part of a conductive path to a first main electrode of the power semiconductor switch. A second region (8) of the opposite conductivity type is provided within the first region adjacent the given surface (6a) and a third region (11) of the one conductivity type is provided adjacent the given surface (6a) within the second region (8), an area of the second region (8) underlying an insulated gate (14) provided on the given surface (6a) for defining a conduction channel (15) providing a gateable connection between the third region (11) and a fourth region (12) of the one conductivity type.

Abstract: Increasing the storage capacity of high-performance signal processors while maintaining the original RAM cell necessitates modification of the entire lay-out of the circuit. The invention relates to the once-only design of peripheral circuitry which provides control of blocks of 4 full CMOS RAM cells (easy to process) or 9 double-layer polysilicon cells (more difficult to process, but having smaller dimensions). It is defined in the RAM peripheral circuitry whether all 9 cells can be accessed (memory capacity from 2.sup.xx n to (2.sup.xx (n+1)+2.sup.xx (n-2)) or 8 cells can be accessed (memory capacity from 2.sup.x n to 2.sup.xx (n+1).

Abstract: A positioning device includes a table (101, 213) guided by a carriage (15, 199), the carriage (15, 199) being displaceable in two coordinate directions (X, Y) with respect to the base (3) and the table (101, 213) being displaceable with respect to the carriage (15, 199) in the same coordinate directions (X, Y) solely by Lorentz forces, while in a third coordinate direction (Z) the position of the table (101, 213) is determined by a static gas bearing. The two-step positioning device is particularly suitable for use in opto-lithographic devices.

Abstract: Circuit includes an (E)EPROM and a programming voltage generator. This generator has a charge pump, a programming voltage controller and an edge controller which limits the increase of the programming voltage per unit of time. In the memory circuit, the controllers are fed back to the charge pump in order to switch the charge pump on or off in dependence on the programming voltage variation.

Abstract: Semiconductor diode lasers of the so-called NAM (Non-Absorbing Mirror) type are used due to the high emanating power as writing (and reading) lasers in optical recording systems. The known lasers of this type include both in the active region (13') and in the mirror region (17, 19) a cladding layer (1), which fills a groove and is provided on an absorbing layer (9) (17, 19). The fundamental lateral mode is favored in both regions (13'), (17, 19) by absorption of part of the radiation produced. Due to the absorption in the mirror region (17, 19) mirror degradation occurs, which limits the maximum power and the life of the laser. A new semiconductor diode laser includes in the mirror region (17, 19) a first cladding layer (1'), a radiation-guiding layer (2') and a third cladding layer (6). In the radiation-guiding layer (2'), a radiation guide (15) is formed by an arrangement (12) in the radiation-guiding layer (2'), by which a step is formed in the effective refractive index.

Abstract: An amplifier arrangement includes a transistor differential pair (N1, N2) having an input terminal (3) and an output terminal (4). The transistor differential pair is coupled to a current mirror (P1, P2). A first level shifting circuit (6) and a second level shifting circuit (7) stabilize the d.c. voltage levels on the mutually coupled main electrodes of the differential pair (N1, N2) and the current mirror (P1, P2) respectively. Consequently, the influence of the Early-effect on the differential pair is suppressed and an improved linear signal transmission is obtained from the input terminal (3) to the output terminal (4). The level shifting circuit (6) also provides a base current compensation in order to produce a high input impedance and the second level shifting circuit (7) provides a base current compensation for equal adjusting currents through the differential pair to reduce any offset voltage.

Abstract: A first doped region (20) is grown on a semiconductor substrate (1) as a superlattice region having alternate layers (21, 22) of a first and second semiconductor material followed by a waveguide region (30) having at least a superlattice region with alternate layers (31, 32) of the first and second semiconductor materials. A second doped region (40) is then grown as a superlattice including alternate layers (41, 42) of the first and second semiconductor materials on the waveguide region (30). The first and second doped regions (20 and 40) are grown so that the layers (21, 22, 41, 42) of the first and second semiconductor materials are sufficiently thin and are sufficiently highly doped as to become disordered during growth so that the first and second doped regions (20 and 40) are formed by an alloy of the first and second semiconductor materials having a lower refractive index and larger bandgap than the waveguide superlattice region (30).

Abstract: An adaptive predistortion circuit for a digital transmission system includes a predistortion circuit (52.sub.1, 52.sub.2, 52.sub.3) for predistorting the input data before they pass through a modulator (56) and then through an amplifier (57), and an adaptation circuit (61.sub.1, 61.sub.2, 61.sub.3) for continuously adapting the predistortion circuit to the stream of input data in response to a demodulation of the stream of transmitted data. The predistortion circuit further includes an encoder (51) which, on a first path, in response to digital data a.sub.k, generates digital data b.sub.k which leave a first predistortion circuit (52.sub.1) in a predistorted manner in-phase with the symbol clock, on a second path, digital data c.sub.k which leave a second distortion circuit (52.sub.2) in a predistorted manner phase-shifted by T/3 relative to the symbol clock and on a third path, digital data d.sub.k which leave a third predistortion circuit (52.sub.

Abstract: The invention relates to a semiconductor device comprising a radiation-sensitive element (A . . . D). The radiation-sensitive element includes a transistor (T) having an emitter region (6), a base region (4) and a collector region (2), and further a radiation-sensitive region (7) having a rectifying junction (5). Due to the presence of the transistor (T), such an element (A . . . D) can supply a considerably larger output signal than a photodiode. On the contrary, however, the first-mentioned element (A . . . D) is comparatively slow as compared with a photodiode due to the parasitic capacitance of the rectifying junction (5). The invention obviates this disadvantage in that according to the invention the radiation-sensitive region (7) has at least a first subregion (71) and a second subregion (72) and the transistor (T) is subdivided into two subtransistors (T.sub.1, T.sub.2), whose base regions (4) are separately connected to the subregions (71, 72).

Abstract: A semiconductor device has a pn junction for producing electromagnetic radation in an active region and a monocrystalline semiconductor body having a first region of a first conductivity type and a second region of the second opposite conductivity type, which forms with each other the pn junction. On the second region is disposed a blocking layer of the first conductivity type, which has an interruption at the area of the active region, while on the blocking layer is disposed a highly doped contact layer of the second conductivity type, which adjoins a surface and in which a contact region is located at the area of said interruption, which also adjoins the surface and extends into the second region. The first region on the one hand and the contact region and the contact layer on the other hand are each provided with an electrode.

Abstract: A balanced filter circuit includes only one balanced amplifier (10) having an inverting input (6) and a non-inverting input (5) and an inverting output (7) and a non-inverting output (8) for realization of filter transfer functions Uout/Uin of the second or higher order from an input signal Uin at input terminals (1, 2) to an output signal Uout at output terminals (3, 4) having passive admittances which are composed of a parallel-combination of a resistor (R42, R44) and/or a capacitor (C41, C44) and/or a number of series-combinations of a resistor (R41, R43, R45) and a capacitor (C42, C43, C45).

Abstract: A radiation-sensitive semiconductor device, more particularly but not exclusively a photo detection arrangement for determining the postion of a luminous spot, including a semiconductor body having at least two radiation-sensitive diodes and amplifying circuitry for the photocurrent generated by the luminous spot. The amplifying circuitry includes transistors arranged outside the area of the semiconductor body occupied by the radiation-sensitive diodes. Each transistor is assigned to and connected to a radiation-sensitive diode, while at least the active parts of the transistors are arranged more closely to each other in the semiconductor body than the diodes to which they are assigned. A focusing arrangement may advantageously incorporate such as semiconductor photodetector.

Abstract: Additional logic is added to a sequential finite-state machine circuit having a self-initialing behavior so that the circuit can be simulated. From any state, a rest state is reached by way of a given sequence of values of an input signal. Transitions between states of the finite-state machine are realized by the additional logic, such that the simulated circuit realizes the transition from an unknown state to a known, absorbing state in steps.

Abstract: Dynamic accurate current divider which comprises current memory circuits (M2-C1-S3, M3-C2-S4) by means of which an input current (Iin) to be split up is divided into two almost equally large output currents (Iout1, Iout2). Under the control of a clock generator (9) having two-phase switching cycles, any inequalities in the output currents are equalized by means of the current memory circuits in a number of cycles of the clock generator.

Abstract: The invention relates to an integrated circuit including a vertical transistor having an emitter having at least one zone (12), a base (2) having a base contacting region (15) adjoining a major surface of the integrated circuit, and a collector (5). The base is less than or equal to the diffusion length of the minority charge carries in these regions. The ratio between the surface S.sub.x of a base contacting region (15) and the surface S.sub.M of a base contact window region is at least equal to 10, and when the base contacting region (15) has a surface smaller than 5 times that of the emitter region. The transistor exhibits improved inverse current amplification.