Abstract: An integrated circuit having logic circuits and a logic output buffer, which circuit includes the following sub-circuits: a memory circuit and a logic output circuit, in which no tri-state occurs at the output during a sequence of data signals at the input, wherein the drive of the circuit by means of control signals is not critical over time because the first data signal from the sequence switches off the tri-state mode, the tri-state mode again being introduced if a control signal is furnished, and in the absence of this control signal, the last data signal is retained.

Abstract: An integrated semiconductor active isolator circuit which includes a negative feedback amplifier having an active semiconductor amplifier element. The control terminal of the semiconductor amplifying element defines the output of the isolator circuit and a principal conduction electrode of the semiconductor amplifying element defines an input of the isolator circuit.

Abstract: The invention relates to an integrated circuit having a programmable cell, more particularly for use in an electronic card. The cell is provided with a programmable element (P) having two conductive layers (51, 52), which are separated from each other by a dielectric layer (53). The element can be programmed by applying between the layers 51, 52 a programming voltage such that an electric breakdown is produced in the dielectric layer (53), as a result of which the element passes permanently from an electrically non-conducting state to an electrically conducting state. According to the invention, the programmable cell comprises an asymmetric bistable trigger circuit (I,II). The trigger circuit (I,II) is loaded with the element (P) in such a manner that during operation it is in a first state if the element is electrically non-conducting and is in a second state if the element is electrically conducting.

Abstract: A semiconductor body (1) has a portion (2a) of one conductivity type adjacent one major surface (3). A first active device region (4) forms with the portion (2a) a first pn junction (5) which terminates at the one major surface (3) and is reverse-biassed in at least one mode of operation of the device. A second active device region (6) provided within the first active device region (4) forms with the first active device region (4) a second pn junction (7) terminating at the one major surface (3). One or more further regions (8) of the opposite conductivity type are provided with the portion (2a) adjacent the one major surface (3) surrounding and spaced from the first pn junction (5) to lie within the spread of the depletion region when the first pn junction (5) is reverse-biased in the at least one mode of operation.

Abstract: An integrated circuit with a memory, includes a matrix of memory cells and sense amplifiers which are coupled thereto, with the inputs of the sense amplifiers being connected to one another and the outputs of the sense amplifiers being connected to one another via a read bus. During the reading of information from a memory cell, the sense amplifiers are simultaneously activated. As a result, the access time for reading information from a a memory cell remains substantially constant when the number of memory columns to be connected in parallel is changed. The dimensioning of the sense amplifiers may remain the same when the number of memory columns is changed, so that dimensioning need be performed only once. This results in a saving as regards time and costs.

Abstract: An integrated charge pump circuit with back bias voltage reduction includes one or more diode type voltage-multiplier stages, with each stage having a diode-connected NMOS transistor in place of the conventionally-used p-n junction diode. The transistors are formed within a P-type well, which forms the back gate of each transistor within the well, and the transistor threshold voltages are dependent on the potential of the P-type well. Performance of the charge pump circuit using NMOS transistors is enhanced by the use of a bias circuit which generates a bias voltage as a function of the output voltage generated by the charge pump circuit, and applies this bias voltage to the P-type well to minimize the back-body effects of the NMOS transistors. The bias circuit thus permits the construction of an integrated charge pump circuit with significantly lower MOS diode voltage drops than would otherwise be possible.

Abstract: A variable bi-phase modulator circuit for microwave signals includes a quadrature power divider (1) having signal input and output ports (2 and 3) and two control ports (4 and 5), and two variable resistors each having an input port (11). Each of the two variable resistors includes first and second microwave field-effect transistors (F1 and F2), the drains of which are coupled together via an intermediate resistor (R). These resistors can be formed using microwave monolithic integrated circuit technology and can have very good impedance characteristics. The input port (11) of the variable resistor has a connection to the intermediate resistor (R) and to the drain of the first transistor (F2). Each transistor is connected with zero dc bias between its source and drain and has a channel resistance which changes with change in gate voltage (VG1, VG2).

Abstract: An addressable memory cell (10) which is composed of an interrupt transistor (20) of the field-effect type whose source (S) is connected to the input terminal (I) of the cell (10) and whose gate (G) is connected to a clock (H, H) and a loop (30) which includes a first inverter (31) which is connected in series with the drain (D) of the interrupt transistor (20) and whose output is connected to the output terminal (0) of the cell (10), and a second inverter (32) which is connected in series, in the loop (30), with the first inverter (31). In accordance with the invention; the cell (10) is made of gallium arsenide and the loop (30) also includes a diode (33) which is connected in the forward direction between the output of the first inventer (31) and the input of the second inverter (32), and a resistance (34) which is connected between the output of the second inverter (32) and the input of the first inverter (31).

Abstract: A coin counting apparatus for a vending machine includes a down counter which is loaded with an initial count representing the number of coins to be deposited in order to initiate a vend cycle which initial count is decremented in response to each sequential coin detection. A display responsive to the current count of the counter indicates the number of coins yet to be deposited and a gate detecting the target count of zero is coupled to actuate relay contacts to signal the vending machine to initiate a vend cycle. An initialization circuit causes the loading of the initial count in response to either the detection of power up or the expiration of a predetermined time period, in the range of 1 to 10 minutes, after the last coin detection.

Abstract: The invention relates to a semiconductor device having a semiconductor substrate, on which a semiconductor layer is provided, which includes sunken or buried strip-shaped conducting regions, which have strip-shaped subregions, in which doping elements are present. Semiconductor devices having such so-called quasi unidimensional conductors constitute potentially important parts of electronic circuits or components. According to the invention, the strip-shaped conducting regions and the strip-shaped subregions are located with a side facing the substrate substantially in one plane, which is a vicinal plane of a major crystal surface of the semiconductor body, of which the semiconductor device forms part. The subregions can also have a very small width and thickness of about 0.3 to 2 nm and can be manufactured in a comparatively simple manner.

Abstract: A technique for achieving read-time animation in bit-map data displays in apparatus having a display memory in which digital codes are stored to give the color and/or luminance of each pixel of the display and the display memory is accessed repeatedly in a recurrent display scan cycle to read-out the digital codes to produce the display. The time available for modifying the contents of the display memory to achieve animation of an object against a fixed background is very small and access to the display memory for the display scan and for writing-in new digital codes must not be in conflict. The present invention proposes a method of continually modifying the display memory content, to achieve object animation, in which the shape of an object is coded into a machine code program (e.g.

Abstract: A laser diode module includes a rectangular box-shaped metal casing having a bottom (B), an even number of guide pins (1-14) being led through the bottom (B) in a standardized DIL order. In addition to the laser diode itself (LD) the laser diode module further includes a metal base carrier (BC) on which the laser diode (LD), a photo diode (PD) and a support (S) for the glass fiber (F) are installed. The laser diode module further includes a guide pin (9) which is inserted in the bottom (B) by means of a feedthrough insulator for electrically connecting the laser diode module to an external transmission line (MT).

Abstract: An input signal (Vin) is applied to a first amplifier (A1) and a second amplifier (A2) via a circuit (M), which amplifiers are both coupled to an output terminal (U) to supply an output voltage (Vuit). For this purpose the circuit (M) generates two mutually complementary signals which are related to the output signal (Vuit) and the maximum signal values corresponding to the individual output signals of the first amplifier (A1) and the second amplifier (A2). The output signal to be supplied (Vuit) consequently dictates which amplifier (A1, A2) is driven into full conduction.

Abstract: A phase-locked loop includes an oscillator controlled by means of a switching network and a microprocessor which generates, in response to the output of a phase detector, two groups of output signals. A first group (Q1 . . . QN) is for adjusting the frequency of the oscillator in steps by selectively switching in frequency determining elements, and a second group (P1 . . . PM) for feeding a pulse duration modulator. The pulse duration modulator produces a control signal for a frequency determining minimum element of the switching network. The control signal has a duty cycle indicative of the frequency determination contribution by the minimum element.

Abstract: In order to boost the output power of a first amplifier (A1) a second amplifier (A2) can increase the supply voltage difference across the first amplifier (A1). However, variations of the supply voltage difference result in comparatively high distortion. In order to minimize this distortion while maintaining the output power, a signal-follower circuit generates a direct voltage lever which tracks a first output signal of the first amplifier, for which purpose the signal-follower circuit is driven by a third amplifier, which compares the first output signal with a reference signal.

Abstract: A direct conversion receiver for demodulating an FM signal converted frequency down converts the signal to quadrature related baseband signals (I,Q). These signals are applied by way of respective d.c. blocking capacitors (16, 18) and differentiating circuits (26, 28) to a differential arctan demodulator (20). The action of the differentiating circuits (26, 28) is to remove any d.c. component in the I and Q signals and to perform a frequency shaping which enables the demodulator (20) to recover correctly the modulating information. Measures are disclosed to overcome the effects of 180 degree phase jumps which will occur when the direction of rotation of the phasor reverses and of frequency dependent amplitude scaling introduced into the differentiated signals (I', Q').

Abstract: A circuit for detecting a variation in power supply voltage includes first transistor (PM1) arranged as a current source and connected to the input (K1) of a current mirror (NM1, NM2), whose output (K2) is connected to a second transistor (PM2) arranged as a current source and to the output of the circuit. In the event of a temporary decrease in supply voltage this circuit will produce a pulse-shaped signal on its output, which signal can be employed as a trigger signal such as a reset signal in bistable circuits.

Abstract: Phase shifter to which are applied two signals in a phase opposition (v, -v) is constituted by a first series circuit of a resistor and a capacitor (R.sub.1, C.sub.1), and a second series circuit of a resistor and a capacitor (R.sub.2, C.sub.2). So that neither the relative amplitudes nor the relative phases of all the signals used at the outputs (5, 6, 7, 8) are degraded by the impedance of the stages that follow, the phase shifter includes a first network of a resistor and a capacitor connected in parallel (C.sub.3, R.sub.3), and a second network of a resistor and a capacitor connected in parallel (C.sub.4, R.sub.4). Both the four resistors and the four capacitors of the phase shifter are each substantially equal in value.

Abstract: A static RAM memory is optimized for speed. The memory is divided into major memory matrices and each major memory matrix is divided into memory blocks. The memory blocks are divided in groups that per group have address bits in common, which however are per group coupled to separate pads or sets of pads. These pads are interconnected on the package to common package pins.

Abstract: A phase comparison circuit includes a double balanced mixer stage which receives a sine signal as well as this sine signal in anti-phase and a square-wave switching signal of the same nominal frequency, two active current mirror circuits are used which incorporate at least two common negative feedback circuit elements, the first of which is operative in the input-sided negative feedback of the first current mirror circuit and in the output-sided negative feedback of the second current mirror circuit and the second of which is operative in the reverse way. The two current mirror circuits are alternately connected to the two balanced mixer stages by means of a switching stage during the half cycle clock of the switching signal.