Abstract: By automatically estimating the focus status of individual substrates or lots on the basis of focus-specific tool information obtained from the exposure tool, such as tilt angle ranges used during the automatic focusing procedures, possible hot spot errors may be detected highly efficiently prior to releasing the substrates to a subsequent etch process. Consequently, yield losses may be reduced. Moreover, possible error sources for hot spot errors may be identified.

Abstract: A method, apparatus and a system, for provided for performing an automated process flow adjustment. A semiconductor wafer is processed based upon a routing plan and a predetermined schedule. A fault detection relating to the processing of the semiconductor wafer is performed. Dynamically modifying the predetermined routing plan or the predetermined schedule based upon the fault detection. A predetermined process material delivery plan is dynamically modified based upon the modifying of the routing plan or modifying of the predetermined schedule.

Abstract: A method that includes forming a gate of a semiconductor device on a substrate and forming a recess for an embedded silicon-straining material in source and drain regions for the gate. In this method, a proximity value, which is defined as a distance between the gate and a closest edge of the recess, is controlled by controlling formation of an oxide layer provided beneath the gate. The method can also include feedforward control of process steps in the formation of the recess based upon values measured during the formation of the recess. The method can also apply feedback control to adjust a subsequent recess formation process performed on a subsequent semiconductor device based on the comparison between a measured proximity value and a target proximity value to decrease a difference between a proximity value of the subsequent semiconductor device and the target proximity value.

Abstract: A first portion of a communication link is operated in a power savings mode at the same time that a second portion of the communication link is operated in a normal operational mode. For the first portion, a refresh mode is entered from the power savings mode in which one or more training patterns are transmitted over the first portion, while the second portion remains in the normal operational mode. An indication when to activate and deactivate the refresh mode may be sent over the second portion of the communication link. The refresh mode may be periodically entered from the power savings mode based on an interval register specifying the amount of time the communication link should remain in the power savings mode before a refresh occurs. In addition, the amount of time spent in the refresh mode may be programmable.

Abstract: An integrated circuit device includes a degradable test structure, a first external interface pin and a second external interface pin, a first conductive path coupling a first node of the degradable test structure and the first external interface pin, and a second conductive path coupling a second node of the degradable test structure and the second external interface pin. Another integrated circuit device includes a non-volatile memory device, a counter comprising an input configured to receive a first clock signal and an output to provide a count value, and control logic configured to store the count value of the counter in the non-volatile memory, whereby the non-volatile memory is externally accessible.

Abstract: The present invention is directed to methods and apparatuses for removing bubbles from a process liquid. The process liquid can comprise a plating solution used in a plating tool. The process liquid is supplied to a tank. A plurality of streams of the process liquid are directed towards a surface of the process liquid from below. This can be done by feeding the process liquid to a flow distributor comprising a plurality of openings providing flow communication between an inner volume of the flow distributor and a main volume of the tank. Before leaving the tank through an outlet, the process liquid flows through a flow barrier.

Abstract: A system and method to optimize processor performance and minimizing average thread latency by selectively loading a cache when a program state, resources required for execution of a program or the program itself change, is described. An embodiment of the invention supports a “cache priming program” that is selectively executed for a first thread/program/sub-routine of each process. Such a program is optimized for situations when instructions and other program data are not yet resident in cache(s), and/or whenever resources required for program execution or the program itself changes. By pre-loading the cache with two resources required for two instructions for only a first thread, average thread latency is reduced because the resources are already present in the cache.

Abstract: An InfiniBand™ network node includes a network interface, a system memory, a memory controller configured for controlling access to the system memory, and a processor. The network interface is configured for outputting data packets according to a prescribed flow control protocol that specifies flow control resources. The network interface also is configured for outputting a data flow interruption request to the memory controller based on a determined depletion of the flow control resources. The memory controller, in response to reception of the data flow interruption request, restricts access to the system memory. Hence, the processor, in response to detecting the restricted access to the system memory, reduces execution of a prescribed application resource based on the determined depletion of the flow control resources.

Abstract: A method of ensuring robust operation of a differential serial link is provided. The method provides a first integrated circuit having 1) a phase generator constructed and arranged to provide a programmable shift of a clock signal based on selective interpolating between first and second phases of the clock signal relative to a digital phase value, and 2) a transmit driver constructed and arranged to control, in a programmable manner, a differential voltage of digital data signals. A second integrated circuit is constructed and arranged to receive the clock and digital data signals sent by the first integrated circuit. The clock and digital data signals are sent substantially simultaneously through the link from the first integrated circuit to the second integrated circuit. It is determined whether the digital data signals can be sampled reliably by the second integrated circuit relative to the digital phase value.

Abstract: By providing dummy vias below electrically non-functional metal regions, the risk for metal delamination in subsequent processes may be significantly reduced. Moreover, in some embodiments, the mechanical strength of the resulting metallization layers may be even more enhanced by providing dummy metal regions, which may act as anchors for an overlying non-functional metal region. In addition, dummy vias may also be provided in combination with electrically functional metal lines and regions, thereby also enhancing the mechanical stability and the electrical performance thereof.

Abstract: Gate straining techniques as described herein can be utilized during the fabrication of NMOS transistor devices, PMOS transistor devices, or CMOS device structures. For an NMOS device, conductive vias are formed in TEOS oxide regions surrounding the sidewall spacers of a metal gate structure, where the metal gate structure includes compressive nitride material within the gate opening. After forming the conductive vias the remaining TEOS oxide is removed and tensile nitride material is deposited between the sidewall spacers and the conductive vias. The sidewall spacers serve as retaining walls for the tensile nitride material, which preserves the tensile characteristics of the material. A similar fabrication technique is utilized to form a PMOS device. For a PMOS device, however, the metal gate structure includes tensile nitride material within the gate opening, and compressive nitride material between the sidewall spacers and the conductive vias.

Abstract: A semiconductor fabrication architecture which includes a middleware component, a fabrication facility coupled to the middleware component, a real time dispatcher application program interface coupled between the fabrication facility and the middleware component, a work in progress application program interface coupled between the fabrication facility and the middleware component, an enterprise resource planning system coupled to the middleware component, and an order processing system coupled to the middleware component. The fabrication facility includes a manufacturing execution system and a real time dispatch system. The manufacturing execution system tracks overall processing of semiconductor wafers. The real time dispatch system provides near real time information regarding processing of semiconductor wafers. The real time dispatcher application program interfaces publishing information to the middleware component.

Abstract: A phase selection circuit having a selection circuit, binary weighted current sources, and an amplifier circuit. The phase selection circuit is configured for selecting adjacent phase signals from a number of equally-spaced phases of a clock signal, based on a phase selection value. The selection circuit outputs the adjacent phase signals to respective first and second binary weighted current sources, along with a digital interpolation value. The first current source outputs a contribution current onto a summing node based on the first adjacent phase signal and the digital interpolation control value, and the second current source outputs a second contribution current to the summing node based on the second adjacent phase signal and an inverse of the digital interpolation control value, resulting in an interpolated signal. An amplifier circuit outputs the interpolated signal as a phase-interpolated clock signal according to the phase selection value.

Abstract: A semiconductor device is disclosed having a conductive gate structure overlying a semiconductor layer having a major surface. An isolation material is recessed within a trench region below the major surface of the semiconductor layer. An epitaxial layer is formed overlying a portion of the major surface and on an active region forming a sidewall of the trench.

Abstract: A current-steering digital-to-analog converter (DAC) is tested using a test component having a relaxation oscillator with an oscillation frequency based on the output current of the DAC. A series of test values is provided in sequence to the DAC for conversion to an output current with a magnitude that varies with the test values. The test component counts the number of oscillations (“the oscillation count”) of the relaxation oscillator over a fixed duration that is substantially equal for each test value. As the number of oscillations over the fixed duration depends on the oscillation frequency of the relaxation oscillator, which in turn is based on the magnitude of the output current, the oscillation count can be used as a relative measure of the magnitude of the output current for the corresponding test value. Accordingly, the oscillation counts for the test values can be used to determine operational characteristics of the DAC.

Abstract: By partially removing an etch stop layer prior to the formation of a first contact etch stop layer, a superior stress transfer mechanism may be provided in an integration scheme for generating strain by means of contact etch stop layers. Thus, a semiconductor device having different types of transistors may be provided, in which a high degree of metal silicide integrity as well as a highly efficient stress transfer mechanism is achieved.

Abstract: Various embodiments of methods and systems for storing multiple groups of microcode operations and corresponding control sequences per row of microcode ROM are disclosed. In one embodiment, an integrated circuit may include a microcode ROM coupled to a control sequence logic unit. The microcode ROM may store multiple groups of microcode operations per row. For each group of microcode operations stored in a row, a corresponding control sequence may also be stored in the row. Each group of microcode operations may be included in a microcode routine. The groups of microcode operations stored in a row may be included in the same microcode routine, or some of the groups may be included in different microcode routines.

Abstract: The present invention provides a technique for reducing stress or stress gradients in highly sensitive device regions, such as cache areas, while still providing high transistor performance in logic areas by correspondingly providing contact etch stop layers with compressive and tensile stress for P-channel transistors and N-channel transistors in these logic areas. Consequently, a reduced failure rate may be obtained.

Abstract: A method of forming a semiconductor structure comprises providing a semiconductor substrate comprising a first transistor element and a second transistor element. Each of the first transistor element and the second transistor element comprises a gate electrode. A stressed material layer is deposited over the first transistor element and the second transistor element. The stressed material layer is processed to form from the stressed material layer sidewall spacers adjacent the gate electrode of the second transistor element and a hard mask covering the first transistor element. A pair of cavities is formed adjacent the gate electrode of the second transistor element. A pair of stress-creating elements is formed in the cavities and the hard mask is at least partially removed.

Abstract: Providing proactive synchronization in a computer system may include providing an augmented instruction set with additional synchronizing instructions. Therefore, a method includes a processor executing a set of instructions to request exclusive access to a plurality of memory resources. The set of instructions includes an ACQUIRE instruction. In addition, the method may include storing addresses referenced by the set of instructions within a buffer. Further, the method may include sending the addresses referenced by the set of instructions, as a set, to be compared to other addresses to which exclusive access to memory addresses has been granted in response to execution of the ACQUIRE instruction.