Abstract: A method and apparatus for shader data repair utilizing a Redundant Shader Switch (RSS). The RSS consists of an input and output section whereby when a defective shader pipe is detected, the RSS multiplexes shader pipe data destined to the defective shader pipe to a redundant shader pipe array for processing. Once processed, the shader pipe data is multiplexed back to the RSS where the processed shader pipe data is directed to the corresponding output column of the RSS. The RSS contains delay pipes used to re-align and synchronize the repaired shader pipe data with output export data.

Abstract: A Scalable and Unified Compute System performs scalable, repairable general purpose and graphics shading operations, memory load/store operations and texture filtering. A Scalable and Unified Compute Unit Module comprises a shader pipe array, a texture mapping unit, and a level one texture cache system. The Scalable and Unified Compute Unit Module accepts ALU instructions, input/output instructions, and texture or memory requests for a specified set of pixels, vertices, primitives, surfaces, or general compute work items from a shader program and performs associated operations to compute the programmed output data. The texture mapping unit accepts source data addresses and instruction constants in order to fetch, format, and perform instructed filtering interpolations to generate formatted results based on the specific corresponding data stored in a level one texture cache system.

Abstract: A method, computer program product, and system are provided for controlling a clock distribution network. For example, an embodiment of the method can include programming a predetermined delay time into a plurality of processing elements and controlling an activation and de-activation of these processing elements in a sequence based on the predetermined delay time. The processing elements are located in a system incorporating the clock distribution network, where the predetermined delay time can be programmed in a control register of a clock gate control circuit residing in the processing element. Further, when controlling the activation and de-activation of the processing elements, this activity can be controlled with a state machine based on the system's mode of operation.

Abstract: A graphics processing unit is disclosed, the graphics processing unit having a processor having one or more SIMD processing units, and a local data share corresponding to one of the one or more SIMD processing units, the local data share comprising one or more low latency accessible memory regions for each group of threads assigned to one or more execution wavefronts, and a global data share comprising one or more low latency memory regions for each group of threads.

Abstract: A system and method by which a memory device can adapt or retrain itself in response to changes in its inputs or operating environment. The memory device, such as a DRAM, includes in its interface an embedded programmable component. The programmable component can be, for example and without limitation, a microprocessor, a microcontroller, or a microsequencer. A programmable component is programmed to make changes to the operation of the interface of the memory device, in response to changes in the environment of the memory device.

Abstract: A system and method of allocating registers in a register array to multiple workloads is disclosed. The method identifies an incoming workload as belonging to a first process group or a second process group, and allocates one or more target registers from the register array to the incoming workload. The register array is logically divided to a first ring and a second ring such that the first ring and the second ring have at least one register in common. The first process group is allocated registers in the first ring and the second process group is allocated registers in the second ring. Target registers in the first ring are allocated in order of sequentially decreasing register addresses and target registers in the second ring are allocated in order of sequentially increasing register addresses.

Abstract: A method, computer program product, and system are provided for processing data in a graphics pipeline. An embodiment of the method includes processing one or more vertices of a geometric primitive with a vertex shader function and generating new primitive information for the one or more processed vertices with a geometry shader function. The geometry shader function receives one or more processed vertices from the vertex shader function and emits a single vertex associated with the new primitive information. Each emitted vertex from the geometry shader function can be stored in a memory device. Unlike conventional graphic pipelines that require a memory device for data storage during the vertex and geometry shading processes, the present invention increases efficiency in the graphics pipeline by eliminating the need to access memory when the vertex and geometry shaders process vertex information.

Abstract: A method of manufacturing an integrated circuit (IC) can utilize a shallow trench isolation (STI) technique. The shallow trench isolation technique can be used in an IC process. Separate liners for the trench are used for NMOS and PMOS regions. The liners can induce strain in the substrate.

Abstract: A method for denying probes during proactive synchronization includes a first processor operating in an advanced synchronization mode, which includes the first processor specifying and acquiring exclusive access to a given memory resource. During operation in the advanced synchronization mode, specifying comprises executing a code sequence including: one or more locked memory reference instructions having a LOCK prefix and one or more addresses associated with the given memory resource. Specifying also includes executing an ACQUIRE instruction that is subsequent to the one or more locked memory reference instructions. The method further includes a second processor requesting access to the given memory resource and issuing a probe message. In response to receiving the probe message, the first processor responding to the probe message with a failure message, thereby denying the second processor access to the given memory resource.

Abstract: A method of performing encrypted WLAN communication is provided that comprises the steps of performing a connection set-up for the encrypted WLAN communication and performing data frame encapsulation and/or decapsulation during the encrypted WLAN communication. The connection set-up is performed by executing software-implemented instructions, and the data frame encapsulation and/or decapsulation is performed by operating single-purpose hardware. In embodiments, corresponding single-purpose hardware devices, integrated circuit chips, computer program products and computer systems are provided. The embodiments may provide an improved hardware/software architecture for 802.11i security enhancement.

Abstract: A method of forming the halo structures of a field effect transistor is disclosed. The halo structures are formed by implanting ions of a dopant material into the substrate on which the transistor is to be formed, wherein the tilt angle of the ion beam with respect to the surface of the substrate is varied according to a predefined time schedule comprising a plurality of implanting periods.

Abstract: An integrated circuit includes an energy controller that generates a power supply voltage level for the integrated circuit based on a desired target frequency value for the integrated circuit. The energy controller configures a programmable hardware process sensor based on the power supply voltage level such that the programmable hardware process sensor is capable of mimicking the electrical characteristics of a predetermined critical path associated with the integrated circuit when operating at the power supply voltage level. By monitoring the frequency of the programmable hardware process sensor over a period of time, the energy controller can compare the monitored frequency to an expected value and determine whether the power supply voltage level can be adjusted or whether it should be maintained.

Abstract: A method for growing an epitaxial layer patterns a mask over a substrate. The mask protects first areas (N-type areas) of the substrate where N-type field effect transistors (NFETs) are to be formed and exposes second areas (P-type areas) of the substrate where P-type field effect transistors (PFETs) are to be formed. Using the mask, the method can then epitaxially grow the Silicon Germanium layer only on the P-type areas. The mask is then removed and shallow trench isolation (STI) trenches are patterned (using a different mask) in the N-type areas and in the P-type areas. This STI patterning process positions the STI trenches so as to remove edges of the epitaxial layer. The trenches are then filled with an isolation material. Finally, the NFETs are formed to have first metal gates and the PFETs are formed to have second metal gates that are different than the first metal gates. The first metal gates have a different work function than the second metal gates.

Abstract: Methods are provided for reducing the aspect ratio of contacts to bit lines in fabricating an IC including logic and memory. The method includes the steps of forming a first group of device regions to be contacted by a first level of metal and a second group of memory bit lines to be contacted by a second level of metal, the first level separated from the second level by at least one layer of dielectric material. Conductive material is plated by electroless plating on the device regions and bit lines and first and second conductive plugs are formed overlying the conductive material. The first conductive plugs are contacted by the first level of metal and the second conductive plugs are contacted by the second level of metal. The thickness of the plated conductive material provides a self aligned process for reducing the aspect ratio of the conductive plugs.

Abstract: A method for determining priority of a selected workpiece in a process flow including a plurality of operations includes providing an objective function relating manufacturing losses to workpiece priority for the operations in the process flow. The objective function is solved to generate priority metrics for at least a subset of the operations remaining for the selected workpiece to allow completion of the selected workpiece in the process flow by a target completion due time.

Abstract: A security association architecture system of the present invention facilitates network data transfer by providing an internal portion of a security association database that can be quickly accessed to obtain security associations as well as an external component that stores the complete security association database. As a result, at least some security associations for incoming received frames and outgoing transmitted frames can be obtained from the internal portion located on a network interface device without accessing system memory, a host computer, and the like in order to obtain the security associations to perform security processing.

Abstract: In inspecting for quality of underfill material dispensed in an IC package, a camera image is captured for the IC package having the underfill material dispensed between an IC die and a package substrate. A data processor analyzes the camera image to determine an occurrence of an unacceptable condition of the underfill material. Pre-heating and/or post-heating of the package substrate before and/or after dispensing the underfill material by a contact-less heater ensures uniform spreading of the underfill material.

Abstract: A method of forming a semiconductor structure comprises providing a semiconductor structure comprising a layer of a dielectric material provided over an electrically conductive feature. An opening is formed in the layer of dielectric material. The opening is located over the electrically conductive feature and has a first lateral dimension. A cavity is formed in the electrically conductive feature. The cavity has a second lateral dimension being greater than the first lateral dimension. The cavity and the opening are filled with an electrically conductive material.

Abstract: A secure memory access system includes a memory control module, at least one direct memory access module, and a plurality of input/output interface modules. The direct memory access module is operative to transfer information between all of the input/output interface modules and the memory control module in response to transfer configuration information.

Abstract: A method that includes forming a gate of a semiconductor device on a substrate, and etching sidewall spacers on sides of the gate to provide a proximity value, where the proximity value is defined as a distance between the gate and an edge of a performance-enhancing region. The sidewall spacers are used to define the edge of the region during formation of the region in the substrate. The method also includes pre-cleaning the gate and the substrate in preparation for formation of the region, where the etching and the pre-cleaning are performed in a continuous vacuum.