Abstract: Embodiments of a random access memory word line driver circuit that reduces consumption of standby power are described. The word line driver is based on NOR-gate logic in which, for memory array consisting of a plurality of memory cells and word line drivers, given two inputs selected one word line goes high and the rest remain zero. The decoder circuit comprises two PMOS transistors in series with an NMOS-based inverter circuit. This arrangement reduces the leakage current through the NMOS transistor when the word line is not selected. An array of word line drivers incorporating a NOR-based decoder includes a shared pull up PMOS transistor for one of two address lines. The shared pull-up PMOS transistor is manufactured to a size on the order of at least two times the width of the remaining transistors of each word line stage.

Abstract: A system and method for managing a memory system. A system includes a plurality of processing entities and a cache which is shared by the processing entities. Responsive to a replacement event, circuitry may identify data entries of the shared cache which are candidates for replacement. Data entries which have been identified as candidates for replacement may be removed as candidates for replacement in response to detecting the data entry corresponds to data which is shared by at least two of the plurality of processing entities. The circuitry may maintain an indication as to which of the processing entities caused an initial allocation of data into the shared cache. When the circuitry detects that a particular data item is accessed by a processing entity other than a processing entity which caused an allocation of the given data item, the data item may be deemed classified as shared data.

Abstract: Each row of a row based shader engine comprises a shader pipe array, a texture filter, and a level one texture cache system. The shader pipe array accepts texture requests for a specified pixel from a resource and performs associated rendering calculations, outputting texel data. The texture mapping unit receives texel data from a level one cache system and through formatting and bilinear filtering interpolations, generates a formatted bilinear result based on a specific pixel's corresponding four texels. Utilizing multiple rows of a row based shader engine within the shader engine allows for the parallel processing of multiple simultaneous resource requests. A method for texture filtering utilizing a row based shader engine is also presented.

Abstract: Pilot processing logic, depending upon which modulation scheme of wireless digital mobile television signals is being received, produces both fractional frequency offset and fractional timing offset for symbols for a respective modulation scheme whether the modulation scheme employs pilot or non-pilot information. As such, in operation, the pilot processing logic will produce both fractional frequency offset and fractional timing offset for symbols from different modulation schemes that employ pilot or non-pilot information so that multiple different modulation schemes of wireless digital mobile television signals can be received by a mobile device, for example, that employs the mobile television demodulating circuit. A dual operation circuit selects the mode of operation, namely the modulation scheme (e.g., T-DMB or DVB-T) of the digital mobile television signal that is being received.

Abstract: A method for providing proactive synchronization in a computer system includes a processor requesting exclusive access to a given memory resource. The request may include one or more addresses associated with the given memory resource. The method also includes comparing each of the addresses in the request to each address in a plurality of sets of addresses. Each address in the sets of addresses may correspond to a respective memory resource to which a requestor has exclusive access. In addition, in response to any address of the one or more addresses matching any address in the plurality of sets of addresses, the method includes returning a count value associated with the set including the matching address. The count value may be indicative of the number of requestors contending for the matching address. Software may utilize this count value to proactively choose an item with lower contention probabilities in subsequent attempts.

Abstract: The present invention provides a method and apparatus for enhancing the performance of video display devices by improving the utilization of memory resources used to process video data. In the system of the present invention, a display is configured to generate a visual image as a plurality of horizontal rows of pixels. In the present invention, the source data frame for said image is divided into row segments comprising a predetermined number of pixels from the entire horizontal row. A plurality of columns are constructed using individual pixel segments from the horizontal rows. The columns are further divided into a plurality of row segment blocks that are rotated and stored in destination memory to generate a rotated visual image.

Abstract: A method and apparatus of the present invention provides a verified computing environment for a personal Internet communicator. In various embodiments of the invention, the functionality of software files on a personal Internet communicator can be modified based on the Pay-State of the user. Upon a request to load a particular software package, the verification module uses a verification file list containing approved software packages and also uses the pay status of the user to determine which software packages can be executed. The personal Internet communicator is operable to provide limited functionality of certain software packages based on a first pay state and to offer no functionality based on a second pay state, such as the situation where a user has discontinued the use of internet service.

Abstract: A device and method for transferring data is disclosed that facilitates data transfers between devices having different clock domains. The data transfer from one device to another occurs through a First In First Out memory (FIFO). The relative number of FIFO access cycles to the FIFO is controlled to maintain a desired FIFO fullness. Setting the desired FIFO fullness to a desired value allows control of data transfer latency between devices.

Abstract: A system and method for controlling communications between a plurality of clients and a central component. An embodiment of the invention includes one or more buses that connect the clients and the central component. This embodiment also includes a control module that is configured to receive ASK messages from the clients and issue GO commands to the clients. Each ASK message represents a request from a client to access the central component. Each GO command to the client represents permission for that client to access the central component. The control module comprises delay stages that delay the GO command. The delays may be different from client to client. The number of delay stages is chosen so that for all clients, the delay between the issuance of a GO command and the receipt at the central component of communications from the clients is the same.

Abstract: An apparatus, method, and system are provided for optimizing computer performance while a first processor is in a sleep mode of operation. For example, an embodiment of the apparatus includes a first processor, a second processor (also referred herein as a “sleep” processor), and one or more peripheral devices. The peripheral devices are coupled to the first processor and the sleep processor through a computer bus architecture. During an active mode of operation, the first processor interacts with and controls the functions of the peripheral devices. In an embodiment, the sleep processor also interacts with and controls the functions of the peripheral devices during the active mode of operation. However, when the first processor is in a sleep mode of operation, the sleep processor is configured to control one or more functions of the computer system incorporating the first processor and the sleep processor.

Abstract: Methods and systems for processing memory lookup requests are provided. In an embodiment, an integrated circuit includes an input configured to receive a first control signal and an output module configured to generate an output signal based at least on the first control signal and a second control signal generated based at least on a measured temperature of the IC. The output signal is configured to control a cooling device.

Abstract: Apparatus and systems utilizing multiple shader engines where each shader engine comprises multiple rows of shader engine filters combined with level one and level two cache systems. Each unified shader engine filter comprises a shader pipe array, and a texture mapping unit with access to a level one cache system and a level two cache. The shader pipe array accepts texture requests for a specified pixel from a resource and performs associated rendering calculations, outputting texel data. The texture mapping unit retrieves texel data stored in a level one cache system, with the ability to read and write to and from a level two cache system, and through formatting and bilinear filtering interpolations generates a formatted bilinear result based on the specific pixel's neighboring texels. Utilizing multiple rows of shader engine filters within a shader engine allows for the parallel processing of multiple simultaneous resource requests.

Abstract: In a personal Internet communication device, an optimized operating system image (NK.bin) is constructed from the operating system component files required to provide a minimum threshold of operating system functionality. By reducing the size of the operating system image, the time required to load the operating system is reduced.

Abstract: A method and system for fault isolation in semiconductor with devices thereon includes determining test data from a plurality of semiconductor devices and creating a failure bitmap of locations of the plurality of semiconductor devices and test data in a vector graphic CAD format. The vector graphic CAD format allows storage of test data on multiple layers.

Abstract: Various integrated circuit packages, lids therefor and methods of making the same are provided. In one aspect, a method of manufacturing is provided that includes providing an integrated circuit package lid that has a surface adapted to face towards an integrated circuit, and forming a wetting film on the surface. The wetting film has at least one void where the surface of the lid is exposed. The void inhibits bonding so that a stress reduction site is produced.

Abstract: The present invention provides a method and apparatus for securing portions of a memory. The method includes identifying information for protection and indicating at least one physical address of a memory that houses the information as at least one of read and write disabled. The method includes receiving a request from a program to access the information. The method further includes accessing the information in response to determining that the program has the authority to access the information. The apparatus includes a memory comprising a privileged code. The privileged code is capable of receiving a request to protect selected information and indicating at least one physical address of a memory housing the information as at least one of read and write disabled. The privileged code is capable of receiving a request from a program to access the information.

Abstract: A method of forming a field effect transistor comprises providing a semiconductor substrate, a gate electrode being formed over the semiconductor substrate. At least one cavity is formed adjacent the gate electrode. A strain-creating element is formed in the at least one cavity. The strain-creating element comprises a compound material comprising a first chemical element and a second chemical element. A first concentration ratio between a concentration of the first chemical element in a first portion of the strain-creating element and a concentration of the second chemical element in the first portion of the strain-creating element is different from a second concentration ratio between a concentration of the first chemical element in a second portion of the strain-creating element and a concentration of the second chemical element in the second strain-creating element.

Abstract: A method for operating an integrated circuit tester information processing system includes: measuring current information from test structures for an integrated circuit having a stress liner; forming a transfer curve by simulating based on the current information with a first range of first mobility multipliers; forming an inverse transfer curve by applying an inverse transfer function to the transfer curve; forming a stress curve with second mobility multipliers from the inverse curve; and validating the second mobility multipliers by comparing a measured curve and a simulated curve with the measured curve based on the current information and the simulated curve based on stress curve.

Abstract: A method, system, and computer program product are disclosed for providing tessellated primitive data to a geometry shader. The method comprises computing a set of tessellated vertices and a computed set of connectivity data based on an original set of vertices and an original set of connectivity data, generating computed vertex data based on the original set of vertices and the set of tessellated vertices, receiving the computed set of connectivity data, requesting a subset of the computed vertex data based on the computed set of connectivity data, and processing primitives defined by the subset of the computed vertex data. The system and computer program product are further disclosed for accomplishing a similar result as the aforementioned method.

Abstract: Methods and systems for dynamically partitioning a cache and maintaining cache coherency are provided. In an embodiment, a system for processing memory requests includes a cache and a cache controller configured to compare a memory address and a type of a received memory request to a memory address and a type, respectively, corresponding to a cache line of the cache to determine whether the memory request hits on the cache line. In another embodiment, a method for processing fetch memory requests includes receiving a memory request and determining if the memory request hits on a cache line of a cache by determining if a memory address and a type of the memory request match a memory address and a type, respectively, corresponding to a cache line of the cache.