Abstract: The present disclosure provides an electronic module including a circuit including a transmitting part and a receiving part physically separated from the transmitting part. The electronic module also includes an element isolated from the circuit and configured to block electrical interference between the transmitting part and the receiving part.
Type:
Application
Filed:
January 16, 2024
Publication date:
May 9, 2024
Applicant:
Advanced Semiconductor Engineering, Inc.
Abstract: An electronic device is provided. The electronic device includes a first dielectric layer, an electronic element, an encapsulant, and a second dielectric layer. The first dielectric layer has a first coefficient of thermal expansion (CTE). The electronic element is disposed over the first dielectric layer. The encapsulant encapsulates the electronic element and has a second CTE. The second dielectric layer is disposed over the encapsulant and having a third CTE. The second CTE ranges between the first CTE and the third CTE.
Type:
Application
Filed:
November 4, 2022
Publication date:
May 9, 2024
Applicant:
Advanced Semiconductor Engineering, Inc.
Inventors:
Chien Lin CHANG CHIEN, Yuan-Chun TAI, Yu Hsin CHANG CHIEN, Chiu-Wen LEE, Chang Chi LEE
Abstract: An electronic device is disclosed. The electronic device includes a first conductive plate and a first electronic component. The first conductive plate includes a first connecting portion. The first electronic component supports the first conductive plate through the first connecting portion. The first connecting portion is electrically connected to the first electronic component and configured to buffer stress from the first conductive plate to the first electronic component.
Abstract: An electronic package structure, an electronic substrate, and a method of manufacturing an electronic package structure are provided. The electronic package structure includes a substrate. The substrate includes a bonding region and an alignment structure. The bonding region is located at a side of the substrate and configured to bond with an electronic component. The alignment structure is located at the side of the substrate and out of the bonding region and configured to providing a fiducial mark for position-aligning, wherein the alignment structure comprises a first region and a second region visually distinct from the first region.
Type:
Grant
Filed:
August 27, 2021
Date of Patent:
May 7, 2024
Assignee:
ADVANCED SEMICONDUCTOR ENGINEERING, INC.
Abstract: The present disclosure provides an electronic assembly including a semiconductor device package. The semiconductor device package includes a first package and a conductive element. The first package includes an electronic component and a protection layer covering the electronic component. The conductive element is supported by the protection layer and electrically connected with the electronic component through an electrical contact. A method for manufacturing a semiconductor device package is also provided in the present disclosure.
Type:
Application
Filed:
January 2, 2024
Publication date:
May 2, 2024
Applicant:
Advanced Semiconductor Engineering, Inc.
Abstract: The present disclosure relates to an electronic device that includes a first radiating element configured to radiate a first electromagnetic wave and a second radiating element configured to radiate a second electromagnetic wave. A first radiation pattern of the first electromagnetic wave is configured to be adjusted, and a second radiation pattern of the second electromagnetic wave is configured to be fixed.
Type:
Application
Filed:
January 9, 2024
Publication date:
May 2, 2024
Applicant:
Advanced Semiconductor Engineering, Inc.
Abstract: A method of attaching a film is provided. The method includes providing a carrier tape. The carrier tape supports a film over a surface of the carrier tape. The method further includes moving the film to a position over an electronic device. The method further includes attaching the film to the electronic device.
Type:
Application
Filed:
October 26, 2022
Publication date:
May 2, 2024
Applicant:
Advanced Semiconductor Engineering, Inc.
Abstract: An optoelectronic device includes a photonic component. The photonic component includes an active side, a second side different from the active side, and an optical channel extending from the active side to the second side of the photonic component. The optical channel includes a non-gaseous material configured to transmit light.
Type:
Application
Filed:
January 9, 2024
Publication date:
May 2, 2024
Applicant:
Advanced Semiconductor Engineering, Inc.
Abstract: A semiconductor device package includes a supporting element, a transparent plate disposed on the supporting element, a semiconductor device disposed under the transparent plate, and a lid surrounding the transparent plate. The supporting element and the transparent plate define a channel.
Type:
Application
Filed:
January 2, 2024
Publication date:
May 2, 2024
Applicant:
Advanced Semiconductor Engineering, Inc.
Abstract: A semiconductor device package includes a semiconductor die, a first conductive element, a second conductive element, a metal layer, and a first redistribution layer (RDL). The semiconductor die includes a first surface and a second surface opposite to the first surface. The first conductive element is disposed on the second surface of the semiconductor die. The second conductive element is disposed next to the semiconductor die. The metal layer is disposed on the second conductive element and electrically connected to the second conductive element. The first RDL is disposed on the metal layer and electrically connected to the metal layer.
Type:
Grant
Filed:
June 1, 2021
Date of Patent:
April 30, 2024
Assignee:
ADVANCED SEMICONDUCTOR ENGINEERING, INC.
Inventors:
Chia-Hao Sung, Hsuan-Yu Chen, Yu-Kai Lin
Abstract: An electronic package is provided. The electronic package includes a power regulating component, an electronic component, and a circuit structure. The circuit structure separates the power regulating component and the electronic component. The circuit structure is configured to provide a first power to the power regulating component. The power regulating component is configured to provide a second power to the electronic component through the circuit structure.
Type:
Grant
Filed:
February 9, 2022
Date of Patent:
April 30, 2024
Assignee:
ADVANCED SEMICONDUCTOR ENGINEERING, INC.
Abstract: A method of manufacturing a semiconductor package structure is provided. The method includes providing a first carrier, forming a patterned buffer layer over the first carrier, forming a first redistribution structure that includes forming a first dielectric layer on the patterned buffer layer, after an electrical testing by applying an electric signal towards the first redistribution structure, removing the first carrier, removing portions of the first dielectric layer, resulting in a patterned first dielectric layer, the patterned first dielectric layer exposing portions of the first circuit layer, removing the exposed portions of the first circuit layer, using the patterned first dielectric layer as a mask, resulting in a patterned first circuit layer, and forming an electric conductor in a recess defined by the patterned first dielectric layer and the patterned first circuit layer.
Type:
Grant
Filed:
September 13, 2021
Date of Patent:
April 30, 2024
Assignee:
ADVANCED SEMICONDUCTOR ENGINEERING, INC.
Abstract: A semiconductor package includes a first die having a first surface, a first conductive bump over the first surface and having first height and a first width, a second conductive bump over the first surface and having a second height and a second width. The first width is greater than the second width and the first height is substantially identical to the second height. A method for manufacturing the semiconductor package is also provided.
Type:
Grant
Filed:
November 8, 2021
Date of Patent:
April 30, 2024
Assignee:
ADVANCED SEMICONDUCTOR ENGINEERING, INC.
Abstract: An electronic package is provided. The electronic package includes a semiconductor substrate. The semiconductor substrate includes a first active region and a first passive region separated from the first active region. The first active region is configured to regulate a power signal. The first passive region is configured to transmit a data signal.
Type:
Grant
Filed:
November 24, 2021
Date of Patent:
April 23, 2024
Assignee:
ADVANCED SEMICONDUCTOR ENGINEERING, INC.
Inventors:
Chang Chi Lee, Chiu-Wen Lee, Jung Jui Kang
Abstract: An electronic module is provided. The electronic module includes a carrier, a movable component and an optical component. The movable component is on the carrier and configured to be movable with respect to the carrier. The optical component is configured to detect a movement of the movable component by an optical coupling between the optical component and the movable component.
Type:
Grant
Filed:
December 22, 2021
Date of Patent:
April 23, 2024
Assignee:
ADVANCED SEMICONDUCTOR ENGINEERING, INC.
Abstract: The present disclosure provides an electronic wearable device. The electronic wearable device includes a first module having a first contact and a second module having a second contact. The first contact is configured to keep electrical connection with the second contact in moving with respect to each other during a wearing period.
Type:
Application
Filed:
October 14, 2022
Publication date:
April 18, 2024
Applicant:
Advanced Semiconductor Engineering, Inc.
Abstract: A semiconductor device package comprises a semiconductor device, a first encapsulant surrounding the semiconductor device, a second encapsulant covering the semiconductor device and the first encapsulant, and a redistribution layer extending through the second encapsulant and electrically connected to the semiconductor device.
Type:
Application
Filed:
December 5, 2023
Publication date:
April 18, 2024
Applicant:
Advanced Semiconductor Engineering, Inc.
Abstract: An electronic device is disclosed. The electronic device includes a system board and a first set of electronic devices disposed over the system board. Each of the first set of electronic devices comprises a processing unit and a carrier carrying the processing unit. The electronic device also includes a first interconnection structure electrically connected with the processing unit through the carrier and configured to receive a first power from a first power supply unit and to transmit the first power to the processing unit.
Type:
Application
Filed:
October 14, 2022
Publication date:
April 18, 2024
Applicant:
Advanced Semiconductor Engineering, Inc.
Inventors:
Chun-Yen TING, Pao-Nan LEE, Hung-Chun KUO, Jung Jui KANG, Chang Chi LEE
Abstract: An electronic module is disclosed. The electronic module includes an electronic component and an interconnection structure disposed over the electronic component. The interconnection structure comprises a first region and a second region different from the first region. The first region is configured to transmit a power from outside of the electronic module to the electronic component. The second region is configured to dissipate heat from the electronic component.
Type:
Application
Filed:
October 14, 2022
Publication date:
April 18, 2024
Applicant:
Advanced Semiconductor Engineering, Inc.
Inventors:
Pao-Nan LEE, Chang Chi LEE, Jung Jui KANG
Abstract: An electronic package, a semiconductor package structure and a method for manufacturing the same are provided. The electronic package includes a carrier, a first electronic component, an electrical extension structure, and an encapsulant. The carrier has a first face and a second face opposite to the first face. The first electronic component is adjacent to the first face of the carrier. The electrical extension structure is adjacent to the first face of the carrier and defines a space with the carrier for accommodating the first electronic component, the electrical extension structure is configured to connect the carrier with an external electronic component. The encapsulant encapsulates the first electronic component and at least a portion of the electrical extension structure.
Type:
Grant
Filed:
August 20, 2021
Date of Patent:
April 16, 2024
Assignee:
ADVANCED SEMICONDUCTOR ENGINEERING, INC.