Patents Assigned to Advanced Semiconductor Engineering
  • Electronic package structure and method for manufacturing the same
    Patent number: 11935855
    Abstract: An electronic package structure and a method for manufacturing the same are provided. The electronic package structure includes a first electronic component, a second electronic component, an interconnection element, an insulation layer, and an encapsulant. The second electronic component is disposed adjacent to the first electronic component. The interconnection element is disposed between the first electronic component and the second electronic component. The insulation layer is disposed between the first electronic component and the second electronic component and has a side surface and a top surface connecting to the side surface. The encapsulant surrounds the interconnection element and at least partially covers the top surface of the insulation layer and has an extended portion in contact with the side surface of the insulation layer.
    Type: Grant
    Filed: November 24, 2021
    Date of Patent: March 19, 2024
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventors: Wei-Jen Wang, Yi Dao Wang, Tung Yao Lin
  • SEMICONDUCTOR DEVICE PACKAGE, ELECTRONIC ASSEMBLY AND METHOD FOR MANUFACTURING THE SAME
    Publication number: 20240088001
    Abstract: A semiconductor device package includes a carrier, an electronic component, a connection element and an encapsulant. The electronic component is disposed on a surface of the carrier. The connection element is disposed on the surface and adjacent to an edge of the carrier. The encapsulant is disposed on the surface of the carrier. A portion of the connection element is exposed from an upper surface and an edge of the encapsulant.
    Type: Application
    Filed: September 19, 2023
    Publication date: March 14, 2024
    Applicant: Advanced Semiconductor Engineering, Inc.
    Inventors: Cheng-Lin HO, Chih-Cheng LEE, Chun Chen CHEN, Cheng Yuan CHEN
  • METHOD FOR MANUFACTURING A PACKAGE STRUCTURE
    Publication number: 20240088091
    Abstract: A method for manufacturing a package structure includes: providing a first electrical element and a second electrical element on a surface of a first carrier, wherein the second electrical element is shifted with respect to the first electrical element; and moving the first electrical element along at least one direction substantially parallel with the surface of the first carrier until a first surface of the first electrical element is substantially aligned with a first surface of the second electrical element from a top view.
    Type: Application
    Filed: September 8, 2022
    Publication date: March 14, 2024
    Applicant: Advanced Semiconductor Engineering, Inc.
    Inventors: Yu-Lin SHIH, Chih-Cheng LEE
  • Optoelectronic package structure and method of manufacturing the same
    Patent number: 11929357
    Abstract: An optoelectronic package structure is provided. The optoelectronic package includes a carrier, an electronic component, a photonic component and a first power supply path in the carrier. The carrier includes a first region and the electronic component is disposed over the first region of the carrier. A first power supply path is electrically connects the electronic component.
    Type: Grant
    Filed: October 20, 2021
    Date of Patent: March 12, 2024
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventors: Jr-Wei Lin, Mei-Ju Lu
  • Electronic device package and method of manufacturing the same
    Patent number: 11923285
    Abstract: An electronic device package and a method for manufacturing the same are provided. The electronic device package includes a circuit layer and an electronic component. The circuit layer includes a dielectric layer having an opening, and an electrical contact. A width of an aperture of the opening increases from a first surface toward a second surface. The electrical contact is at least partially disposed in the opening and exposed through the opening. The electronic component is disposed on the second surface and electrically connected to the circuit layer.
    Type: Grant
    Filed: January 5, 2021
    Date of Patent: March 5, 2024
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventors: Po-Jen Cheng, Chien-Fan Chen
  • Semiconductor device and method for manufacturing the same
    Patent number: 11923825
    Abstract: A semiconductor device and a method of manufacturing a semiconductor device are provided. The semiconductor device includes a carrier, an element, and a first electronic component. The element is disposed on the carrier. The first electronic component is disposed above the element. The element is configured to adjust a first bandwidth of a first signal transmitted from the first electronic component.
    Type: Grant
    Filed: July 22, 2021
    Date of Patent: March 5, 2024
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventors: Cheng-Yuan Kung, Meng-Wei Hsieh
  • Semiconductor device package including promoters and method of manufacturing the same
    Patent number: 11923274
    Abstract: The subject application discloses a substrate. The substrate includes a first conductive layer, a first bonding layer, a first dielectric layer, and a conductive via. The first bonding layer is disposed on the first conductive layer. The first dielectric layer is disposed on the first bonding layer. The conductive via penetrates the first dielectric layer and is electrically connected with the first conductive layer.
    Type: Grant
    Filed: November 29, 2022
    Date of Patent: March 5, 2024
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventor: Wen Hung Huang
  • Semiconductor device and semiconductor package
    Patent number: 11923328
    Abstract: A semiconductor device includes a semiconductor die having a first surface and a second surface opposite to the first surface, a plurality of first real conductive pillars in a first region on the first surface, and a plurality of supporters in a second region adjacent to the first region. An area density of the plurality of supporters in the second region is in a range of from about 50% to about 100% to an area density of the plurality of first real conductive pillars in the first region. A method for manufacturing a semiconductor package including the semiconductor device is also disclosed in the present disclosure.
    Type: Grant
    Filed: November 9, 2021
    Date of Patent: March 5, 2024
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventor: Hsin He Huang
  • ELECTRONIC DEVICE
    Publication number: 20240072413
    Abstract: An electronic device is provided. The electronic device includes an antenna array including a plurality of antenna patterns collectively configured to provide a scan-angle coverage. Each of the antenna patterns includes a curved surface.
    Type: Application
    Filed: August 24, 2022
    Publication date: February 29, 2024
    Applicant: Advanced Semiconductor Engineering, Inc.
    Inventors: Cheng-Yu HO, Meng-Wei HSIEH, Chih-Pin HUNG
  • ELECTRONIC DEVICE AND METHOD FOR MANUFACTURING THE SAME
    Publication number: 20240071945
    Abstract: An electronic device and a method for manufacturing the same are provided. The electronic device includes a first electronic component, a second electronic component and a conductive element. The conductive element includes a first portion and a second portion. The first portion is configured to block an electromagnetic interference between the first electronic component and the second electronic component. The second portion protrudes from the first portion and contacts a shielding layer.
    Type: Application
    Filed: August 31, 2022
    Publication date: February 29, 2024
    Applicant: Advanced Semiconductor Engineering, Inc.
    Inventor: Zhi-Yuan LIN
  • Electronic device
    Patent number: 11916004
    Abstract: An electronic device is provided. The electronic device includes a first carrier having a first surface, an interposer disposed over the first surface of the first carrier, wherein the interposer has a first thickness and a second thickness in a direction substantially perpendicular to the first surface of the first carrier; and a plurality of electrical connections between the first carrier and the interposer and configured to compensate a difference between the first thickness and the second thickness of the interposer.
    Type: Grant
    Filed: September 3, 2021
    Date of Patent: February 27, 2024
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventor: Ching-Feng Cheng
  • Method for manufacturing a package
    Patent number: 11913132
    Abstract: A method for manufacturing a package includes generating an electric field between an anode and a cathode in an electroplating solution to electroplate a substrate electrically connected to the cathode; depositing metal on a central region of the substrate with a first deposition rate; depositing metal on an outer region of the substrate with a second deposition rate lower than the first deposition rate; and reducing the first deposition rate.
    Type: Grant
    Filed: May 18, 2022
    Date of Patent: February 27, 2024
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventors: Chia Chun Hsu, Chin-Feng Wang
  • SEMICONDUCTOR PACKAGE STRUCTURE AND METHOD OF MANUFACTURING THE SAME
    Publication number: 20240063163
    Abstract: A semiconductor package structure includes a semiconductor device with an active surface, a conductive pillar on the conductive pad, an adhesion strengthening layer, and an encapsulant in contact with the adhesion strengthening layer. The conductive pillar has a side surface and a top surface. The adhesion strengthening layer is conformally disposed on the side surface of the conductive pillar and the active surface of the semiconductor device.
    Type: Application
    Filed: October 31, 2023
    Publication date: February 22, 2024
    Applicant: Advanced Semiconductor Engineering, Inc.
    Inventors: Yu-Pin TSAI, Ming-Chi LIU, Yu-Ting LU, Kai-Chiang HSU, Che-Ting LIU
  • PACKAGE STRUCTURES AND METHODS OF MANUFACTURING THE SAME
    Publication number: 20240063159
    Abstract: A package structure is disclosed. The package structure includes a substrate including a conductive element and a plurality of wires having a surface area through which heat of the conductive element can be dissipated, lowering a bonding temperature of the conductive element. The package structure also includes a conductive layer disposed between the conductive element of the substrate and the plurality of wires. The conductive contact layer attaches the plurality of wires over the conductive element.
    Type: Application
    Filed: August 19, 2022
    Publication date: February 22, 2024
    Applicant: Advanced Semiconductor Engineering, Inc.
    Inventors: An-Hsuan HSU, Chin-Li KAO
  • Semiconductor device package and a method of manufacturing the same
    Patent number: 11908781
    Abstract: At least some embodiments of the present disclosure relate to a semiconductor package structure. The semiconductor package structure includes a substrate with a first surface, an encapsulant, an electronic component, and a patterned conductive layer. The encapsulant is disposed on the first surface of the substrate. The encapsulant includes a first surface and a second surface. The patterned conductive layer extends on the first surface and the second surface of the encapsulant and protrudes from the first surface and the second surface of the encapsulant. The electronic component is disposed on the patterned conductive layer.
    Type: Grant
    Filed: March 22, 2021
    Date of Patent: February 20, 2024
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventors: Wei-Chih Cho, Chun-Hung Yeh, Tsung-Wei Lu
  • Semiconductor device package
    Patent number: 11908815
    Abstract: The present disclosure provides a semiconductor device package. The semiconductor device package includes an antenna layer, a first circuit layer and a second circuit layer. The antenna layer has a first coefficient of thermal expansion (CTE). The first circuit layer is disposed over the antenna layer. The first circuit layer has a second CTE. The second circuit layer is disposed over the antenna layer. The second circuit layer has a third CTE. A difference between the first CTE and the second CTE is less than a difference between the first CTE and the third CTE.
    Type: Grant
    Filed: April 19, 2022
    Date of Patent: February 20, 2024
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventor: Wen Hung Huang
  • Wiring structure
    Patent number: 11908786
    Abstract: A wiring structure includes a test pattern layer. The test pattern layer includes a test circuit pattern and a heat dissipating structure. The heat dissipating structure is disposed adjacent to the test circuit pattern, and is configured to reduce temperature rise of the test circuit pattern when a power is applied to the test circuit pattern.
    Type: Grant
    Filed: February 18, 2022
    Date of Patent: February 20, 2024
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventor: Ting Wei Hsu
  • ELECTRONIC DEVICE
    Publication number: 20240055365
    Abstract: An electronic device is disclosed. The electronic device includes a first interconnection structure, and a first electronic component disposed over the first interconnection structure and having an active surface and a lateral surface. The electronic device also includes a power connection disposed between the first interconnection structure and the active surface of the first electronic component, and a first non-power connection extending along the lateral surface of the first electronic component and electrically connected to the first interconnection structure. The electronic device also includes a second non-power connection disposed between the first interconnection structure and the active surface of the first electronic component. The second non-power connection is configured to block an electromagnetic interference (EMI) between the power connection and the first non-power connection.
    Type: Application
    Filed: August 11, 2022
    Publication date: February 15, 2024
    Applicant: Advanced Semiconductor Engineering, Inc.
    Inventors: Po-I WU, Jung Jui KANG, Chang Chi LEE, Pao-Nan LEE, Ming-Fong JHONG
  • Semiconductor device package
    Patent number: 11901275
    Abstract: A semiconductor device package includes a substrate, a first insulation layer and an electrical contact. The first insulation layer is disposed on the first surface of the substrate. The electrical contact is disposed on the substrate and has a first portion surrounded by the first insulation layer and a second portion exposed from the first insulation layer, and a neck portion between the first portion and the second portion of the electrical contact. Further, the second portion tapers from the neck portion.
    Type: Grant
    Filed: March 15, 2021
    Date of Patent: February 13, 2024
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING KOREA, INC.
    Inventors: Soonheung Bae, Hyunjoung Kim
  • Semiconductor device package
    Patent number: 11901270
    Abstract: A semiconductor device package includes a substrate and a conductive lid. The conductive lid is disposed within the substrate. The conductive lid defines a waveguide having a cavity. The waveguide is configured to transmit a signal from a first electronic component to a second electronic component through the cavity.
    Type: Grant
    Filed: September 2, 2020
    Date of Patent: February 13, 2024
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventor: Shih-Wen Lu