Abstract: A wafer supporting mechanism and a method for wafer dicing are provided. The wafer supporting mechanism includes a base portion and a support portion. The base portion includes a first gas channel and a first outlet connected to the first gas channel. The support portion is connected to the base portion and including a second gas channel connected to the first gas channel. An accommodation space is defined by the base portion and the support portion.
Type:
Application
Filed:
February 21, 2023
Publication date:
June 22, 2023
Applicant:
Advanced Semiconductor Engineering, Inc.
Inventors:
Bo Hua CHEN, Yan Ting SHEN, Fu Tang CHU, Wen-Pin HUANG
Abstract: A package structure is provided. The package structure includes an encapsulant and an interposer. The encapsulant has a top surface and a bottom surface opposite to the top surface. The interposer is encapsulated by the encapsulant. The interposer includes a main body, an interconnector, and a stop layer. The main body has a first surface and a second surface opposite to the first surface. The interconnector is disposed on the first surface and exposed from the top surface of the encapsulant. The stop layer is on the second surface, wherein a bottom surface of the stop layer is lower than the second surface.
Type:
Application
Filed:
December 17, 2021
Publication date:
June 22, 2023
Applicant:
Advanced Semiconductor Engineering, Inc.
Abstract: An electronic module is provided. The electronic module includes a carrier, a movable component and an optical component. The movable component is on the carrier and configured to be movable with respect to the carrier. The optical component is configured to detect a movement of the movable component by an optical coupling between the optical component and the movable component.
Type:
Application
Filed:
December 22, 2021
Publication date:
June 22, 2023
Applicant:
Advanced Semiconductor Engineering, Inc.
Abstract: The present disclosure provides a wearable component. The wearable component includes a first carrier and a first electronic component at least partially embedded within the first carrier. The first carrier and the first electronic component define a space configured for audio transmission. An ear tip and a method of manufacturing a wearable component are also provided.
Type:
Application
Filed:
December 22, 2021
Publication date:
June 22, 2023
Applicant:
Advanced Semiconductor Engineering, Inc.
Abstract: An electronic device is disclosed. The electronic device includes a carrier having a first surface and a first lateral surface, an antenna adjacent to the first surface of the carrier, and a shielding layer covering a portion of the first lateral surface of the carrier. The shielding layer is configured to allow a gain of the antenna to be greater than 20 dB.
Type:
Application
Filed:
December 10, 2021
Publication date:
June 15, 2023
Applicant:
Advanced Semiconductor Engineering, Inc.
Inventors:
Hui-Ping JIAN, Ming-Hung CHEN, Jia-Feng HO
Abstract: A semiconductor device package includes a substrate and a shielding layer. The substrate has a first surface, a second surface opposite to the first surface and a first lateral surface extending between the first surface and the second surface. The substrate has an antenna pattern disposed closer to the second surface than the first surface. The shielding layer extends from the first surface toward the second surface of the substrate. The shielding layer covers a first portion of the first lateral surface adjacent to the first surface of the substrate. The shielding layer exposes a second portion of the first lateral surface adjacent to the second surface of the substrate.
Type:
Application
Filed:
February 14, 2023
Publication date:
June 15, 2023
Applicant:
Advanced Semiconductor Engineering, Inc.
Abstract: An electronic package structure includes a lower circuit pattern structure, an upper circuit pattern structure, a reflowable material and at least one core element. The upper circuit pattern structure is disposed above the lower circuit pattern structure. The reflowable material is disposed between the upper circuit pattern structure and the lower circuit pattern structure. The core element attaches to the reflowable material and is configured to inhibit displacement of the at least one core element during a reflow process.
Type:
Application
Filed:
December 10, 2021
Publication date:
June 15, 2023
Applicant:
Advanced Semiconductor Engineering, Inc.
Inventors:
Wei-Jen WANG, Po-Jen CHENG, Fu-Yuan CHEN, Kao Hsin CHEN
Abstract: A semiconductor package structure includes a circuit pattern structure, an encapsulant and an anchoring structure. The encapsulant is disposed on the circuit pattern structure. The anchoring structure is disposed adjacent to an interface between the encapsulant and the circuit pattern structure, and is configured to reduce a difference between a variation of expansion of the encapsulant and a variation of expansion of the circuit pattern structure in an environment of temperature variation.
Type:
Application
Filed:
December 3, 2021
Publication date:
June 8, 2023
Applicant:
Advanced Semiconductor Engineering, Inc.
Abstract: A semiconductor device package and a method for manufacturing the semiconductor device package are provided. The semiconductor device package includes a first substrate, a second substrate disposed over the first substrate and having a first surface facing away from the first substrate and a second surface facing the first substrate, a first component disposed on the first surface of the second substrate, a second component disposed on the second surface of the second substrate; and a support member covering the first component.
Type:
Application
Filed:
November 12, 2021
Publication date:
May 18, 2023
Applicant:
Advanced Semiconductor Engineering, Inc.
Abstract: A semiconductor package includes a substrate, a preformed feeding element, a preformed shielding element, and an encapsulant. The preformed feeding element is disposed on the substrate and the preformed feeding element is disposed on the substrate and adjacent to the preformed feeding element. The encapsulant encapsulates the preformed feeding element and the preformed shielding element.
Type:
Application
Filed:
January 10, 2023
Publication date:
May 11, 2023
Applicant:
Advanced Semiconductor Engineering, Inc.
Abstract: An electronic package is provided. The electronic package includes a carrier, a first electronic component, a bonding element, and a barrier. The carrier has a conductive layer. The first electronic component is disposed adjacent to the carrier and has a first terminal and a second terminal. The bonding element is configured to electrically connect the conductive layer to the first terminal. The barrier is configured to avoid electrically bypassing an electrical path in the first electronic component and between the first terminal and the second terminal.
Type:
Application
Filed:
November 9, 2021
Publication date:
May 11, 2023
Applicant:
Advanced Semiconductor Engineering, Inc.
Abstract: The present disclosure provides a semiconductor device package including a first substrate and an adhesive layer. The first substrate has a first surface and a conductive pad adjacent to the first surface. The conductive pad has a first surface exposed from the first substrate. The adhesive layer is disposed on the first surface of the first substrate. The adhesive layer has a first surface facing the first substrate. The first surface of the adhesive layer is spaced apart from the first surface of the conductive pad in a first direction substantially perpendicular to the first surface of the first substrate. The conductive pad and the adhesive layer are partially overlapping in the first direction.
Type:
Application
Filed:
January 3, 2023
Publication date:
May 4, 2023
Applicant:
Advanced Semiconductor Engineering, Inc.
Abstract: An optoelectronic package structure is provided. The optoelectronic package structure includes a carrier and a photonic component. The carrier includes an upper surface and a first lateral surface. The photonic component is disposed over an upper surface of the carrier and includes an optical portion. The carrier includes a recessed portion recessed from the first lateral surface of the carrier, and the optical portion of the photonic component is located within the recessed portion of the carrier from a top view perspective.
Type:
Application
Filed:
October 28, 2021
Publication date:
May 4, 2023
Applicant:
Advanced Semiconductor Engineering, Inc.
Abstract: A method and a system for manufacturing a semiconductor package structure are provided. The method includes: (a) providing a package body including at least one semiconductor device encapsulated in an encapsulant; (b) providing a flattening force to the package body; (c) thinning the package body after (b); (d) attaching a film to the package body; and (e) releasing the flattening force after (d).
Type:
Application
Filed:
December 27, 2022
Publication date:
May 4, 2023
Applicant:
Advanced Semiconductor Engineering, Inc.
Abstract: At least some embodiments of the present disclosure relate to an electronic package structure. The electronic package structure includes an electronic structure, a wiring structure disposed over the electronic structure, a bonding element connecting the wiring structure and the electronic structure, and a reinforcement element attached to the wiring structure. An elevation difference between a highest point and a lowest point of a surface of the wiring structure facing the electronic structure is less than a height of the bonding element.
Type:
Application
Filed:
October 14, 2021
Publication date:
April 20, 2023
Applicant:
Advanced Semiconductor Engineering, Inc.
Abstract: An optoelectronic package includes an input/output (I/O) component, a photonic component, and an electronic component configured to modulate optical signals in the photonic component. The I/O component is electrically connected to the photonic component via the electronic component.
Type:
Application
Filed:
October 20, 2021
Publication date:
April 20, 2023
Applicant:
Advanced Semiconductor Engineering, Inc.
Abstract: The present disclosure provides an antenna device. The antenna device includes a dielectric element including a first region and a second region, a first antenna disposed on the first region, and a second antenna disposed on the second region. The first antenna and the second antenna are configured to operate in different frequencies. The first antenna and the second antenna are misaligned in directions perpendicular and parallel to a surface of the dielectric element on which the first antenna or the second antenna is disposed.
Type:
Application
Filed:
October 15, 2021
Publication date:
April 20, 2023
Applicant:
Advanced Semiconductor Engineering, Inc.
Abstract: An optoelectronic package structure is provided. The optoelectronic package includes a carrier, an electronic component, a photonic component and a first power supply path in the carrier. The carrier includes a first region and the electronic component is disposed over the first region of the carrier. A first power supply path is electrically connects the electronic component.
Type:
Application
Filed:
October 20, 2021
Publication date:
April 20, 2023
Applicant:
Advanced Semiconductor Engineering, Inc.
Abstract: An optoelectronic package structure is provided. The optoelectronic package structure includes a heat source, a thermal conductive element, and a first optoelectronic component and a second optoelectronic component. The thermal conductive element is disposed over the heat source. The thermal conductive element defines a thermal conduction path P2 by which heat is transferred from the heat source to the thermal conductive element. The first optoelectronic component and the second optoelectronic component are arranged along an axis different from a thermal conduction path P2.
Type:
Application
Filed:
October 15, 2021
Publication date:
April 20, 2023
Applicant:
Advanced Semiconductor Engineering, Inc.
Abstract: An electronic package structure includes an electronic structure, a wiring structure, an electrical contact and a support layer. The wiring structure is located over the electronic structure. The electrical contact connects the wiring structure and the electronic structure. The support layer is disposed around the electrical contact and has a surface facing the electrical contact. The surface includes at least one inflection point in a cross-sectional view.
Type:
Application
Filed:
October 14, 2021
Publication date:
April 20, 2023
Applicant:
Advanced Semiconductor Engineering, Inc.