Patents Assigned to Advanced Semiconductor Engineering
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Patent number: 11862525Abstract: A semiconductor device package includes a supporting element, a transparent plate disposed on the supporting element, a semiconductor device disposed under the transparent plate, and a lid surrounding the transparent plate. The supporting element and the transparent plate define a channel.Type: GrantFiled: March 15, 2022Date of Patent: January 2, 2024Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.Inventors: Tsung-Yu Lin, Pei-Yu Wang, Chung-Wei Hsu
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Patent number: 11862585Abstract: A semiconductor package structure includes a first substrate, a second substrate, a pad layer and a conductive bonding layer. The first substrate has a first surface and a second surface opposite to the first surface. The second substrate has a first surface and a second surface opposite to the first surface. The second substrate is disposed side-by-side with the first substrate. The pad layer is disposed on the second surface of the first substrate and the second surface of the second substrate. The conductive bonding layer is disposed between the pad layer and the second surfaces of the first substrate and the second substrate.Type: GrantFiled: February 21, 2020Date of Patent: January 2, 2024Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.Inventors: Syu-Tang Liu, Huang-Hsien Chang, Shu-Han Yang
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Publication number: 20230420416Abstract: A semiconductor package structure is provided. The semiconductor package structure includes a carrier, a first electronic component, a second electronic component, a third electronic component, a fourth electronic component, and a connection element. The first electronic component is disposed over a surface of the carrier. The second electronic component is disposed over the first electronic component. The third electronic component is spaced apart from the first electronic component and disposed over the surface of the carrier. The fourth electronic component is disposed over the third electronic component. The connection element is electrically connecting the second electronic component to the fourth electronic component.Type: ApplicationFiled: September 12, 2023Publication date: December 28, 2023Applicant: Advanced Semiconductor Engineering, Inc.Inventors: Chien-Chi LEE, Jyan-Ann HSIA
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Publication number: 20230420395Abstract: The present disclosure provides an electronic device. The electronic device includes a first electronic component and a second electronic component. The first electronic component is configured to receive a radio frequency (RF) signal and amplify a power of the RF signal. The second electronic component is disposed under the first electronic component. The second electronic component includes an interconnection structure passing through the second electronic component. The interconnection structure is configured to provide a path for a transmission of the RF signal.Type: ApplicationFiled: June 22, 2022Publication date: December 28, 2023Applicant: Advanced Semiconductor Engineering, Inc.Inventors: Wei-Cheng LIN, Hung-Yi LIN, Cheng-Yuan KUNG, Hsu-Chiang SHIH, Cheng-Yu HO
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Publication number: 20230420418Abstract: An electronic device is provided. The electronic device includes a first die and a second die. The second die is disposed over the first die. A backside surface of the second die faces a backside surface of the first die. An active surface of the second die is configured to receive a first power. The second die is configured to provide the first die with a second power through the backside surface of the second die and the backside surface of the first die.Type: ApplicationFiled: June 22, 2022Publication date: December 28, 2023Applicant: Advanced Semiconductor Engineering, Inc.Inventors: Chun-Yen TING, Pao-Nan LEE, Jung Jui KANG, Chang Chi LEE
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Patent number: 11856856Abstract: A thermal conduction unit includes a conductive via, a periphery conductor and an isolation material. The conductive via includes a first thermoelectric material. The periphery conductor encloses the conductive via and includes a second thermoelectric material. An end of the periphery conductor is electrically connected to an end of the conductive via. The isolation material is interposed between the conductive via and the periphery conductor.Type: GrantFiled: September 30, 2019Date of Patent: December 26, 2023Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.Inventor: Wen-Long Lu
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Patent number: 11855034Abstract: An electronic device package is provided. The electronic device package includes a redistribution layer (RDL), a first electronic component and an interconnector. The RDL includes a topmost circuit layer, and the topmost circuit layer includes a conductive trace. The first electronic component is disposed over the RDL. The interconnector is disposed between the RDL and the first electronic component. A direction is defined by extending from a center of the first electronic component toward an edge of the first electronic component, and the direction penetrates a first sidewall and a second sidewall of the interconnector, the second sidewall is farther from the center of the first electronic component than the first sidewall is, and the conductive trace is outside a projection region of the second sidewall.Type: GrantFiled: May 28, 2021Date of Patent: December 26, 2023Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.Inventors: Chung-Hung Lai, Chin-Li Kao, Chih-Yi Huang, Teck-Chong Lee
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Publication number: 20230413454Abstract: A semiconductor device package includes a display device, an encapsulation layer disposed in direct contact with the display device, and a reinforced structure surrounded by the encapsulation layer. The reinforced structure is spaced apart from a surface of the display device. A method of manufacturing a semiconductor device package is also disclosed.Type: ApplicationFiled: August 29, 2023Publication date: December 21, 2023Applicant: Advanced Semiconductor Engineering, Inc.Inventors: Ming-Hung CHEN, Yung I YEH, Chang-Lin YEH, Sheng-Yu CHEN
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Publication number: 20230411349Abstract: A semiconductor device package includes a first conductive layer, a second conductive layer and a third conductive layer. The first conductive layer has a first pitch. The second conductive layer has a second pitch and is arranged at two different sides of the first conductive layer. The third conductive layer has a third pitch and is disposed above the first conductive layer and the second conductive layer. The third conductive layer is electrically connected to the first conductive layer. The first pitch is smaller than the third pitch, and the third pitch is smaller than the second pitch.Type: ApplicationFiled: August 29, 2023Publication date: December 21, 2023Applicant: Advanced Semiconductor Engineering, Inc.Inventors: Tang-Yuan CHEN, Meng-Kai SHIH, Teck-Chong LEE, Shin-Luh TARNG, Chih-Pin HUNG
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Patent number: 11848296Abstract: A semiconductor device package is provided. The semiconductor device package includes providing a first substrate, a computing unit and a power module. The first substrate has a first surface and a second surface opposite to the first surface. The computing unit is adjacent to the first surface. The computing unit includes a semiconductor die. The power module is adjacent to the second surface. The power module includes a power element and a passive element. Each of the semiconductor die, the power element, and the passive element is vertically arranged with respect to each other, and the passive elements are assembled between the semiconductor die and the power element.Type: GrantFiled: October 26, 2021Date of Patent: December 19, 2023Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.Inventors: Han-Chee Yen, Ying-Nan Liu, Min-Yao Cheng
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Patent number: 11848480Abstract: An electronic device and a method for manufacturing the same are provided. The electronic device includes a carrier, an antenna element and a cladding element. The carrier defines a first area and a second area adjacent to the first area. The antenna element is in the first area. The cladding element covers the antenna element and is configured for enhancing antenna gain of the antenna element. The second area is exposed from the cladding element and is distant from the antenna element.Type: GrantFiled: August 27, 2021Date of Patent: December 19, 2023Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.Inventors: Jenchun Chen, Ya-Wen Liao
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Patent number: 11848143Abstract: An electronic device and a method for manufacturing an electronic device are provided. The electronic device includes an inductor. The inductor includes a plurality of line portions and a plurality of plate portions connected to the plurality of line portions. The line portions and the plate portions form a coil concentric to a horizontal axis.Type: GrantFiled: October 7, 2020Date of Patent: December 19, 2023Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.Inventors: Yunghsun Chen, Huang-Hsien Chang, Shao Hsuan Chuang
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Publication number: 20230400648Abstract: The present disclosure provides an electronic package. The electronic package includes a photonic component including a first input/output (I/O) port and a second I/O port both at a side of the photonic component. The electronic package also includes a connector disposed adjacent to the side of the photonic component and configured to guide a first light carrying medium to be optically coupled with at least one of the first I/O port and second I/O port of the photonic component.Type: ApplicationFiled: June 10, 2022Publication date: December 14, 2023Applicant: Advanced Semiconductor Engineering, Inc.Inventors: Han-Chee YEN, Min-Yao CHENG, Hung-Yi LIN
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Publication number: 20230402738Abstract: A semiconductor device package is provided that includes a substrate, a first support structure disposed on the substrate and a first antenna. The first support structure includes a first surface spaced apart from the substrate by a first distance. The first antenna is disposed above the first surface of the first support structure. The first antenna has a first surface, a second surface opposite the first surface and a third surface extending from the first surface to the second surface, wherein the first surface and the second surface of the first antenna are exposed.Type: ApplicationFiled: August 8, 2023Publication date: December 14, 2023Applicant: Advanced Semiconductor Engineering, Inc.Inventors: Guo-Cheng LIAO, Yi Chuan DING
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Publication number: 20230403078Abstract: A system including optical devices is provided. The system includes a first substrate and a first device for optical communication. The first device has a first surface, a second surface opposite to the first surface, and a first side contiguous with the first surface and the second surface. Moreover, the first side is smaller than one of the first surface and the second surface in terms of area. The first device is attached at the first side thereof to the first substrate.Type: ApplicationFiled: August 8, 2023Publication date: December 14, 2023Applicant: Advanced Semiconductor Engineering, Inc.Inventors: Chang-Yu LIN, Cheng-Yuan KUNG, Hung-Yi LIN
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Patent number: 11844199Abstract: An electronic device is disclosed. The electronic device includes a first electronic component, a first power regulator disposed above the first electronic component. The first power regulator is configured to receive a first power along a lateral surface of the first electronic component without passing the first electronic component and to provide a second power to the first electronic component. The electronic device also includes a passive component disposed in an electrical path between the first electronic component and the first power regulator.Type: GrantFiled: January 26, 2022Date of Patent: December 12, 2023Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.Inventors: Li-Chieh Hung, Chen-Chao Wang
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Publication number: 20230393194Abstract: A package structure and a testing method are provided. The package structure includes a wiring structure, a first electronic device and a second electronic device. The wiring structure includes at least one dielectric layer, at least one conductive circuit layer in contact with the dielectric layer, and at least one test circuit structure in contact with the dielectric layer. The test circuit structure is disposed adjacent to the interconnection portion of the conductive circuit layer. The first electronic device is electrically connected to the wiring structure. The second electronic device is electrically connected to the wiring structure. The second electronic device is electrically connected to the first electronic device through the interconnection portion of the conductive circuit layer.Type: ApplicationFiled: August 22, 2023Publication date: December 7, 2023Applicant: Advanced Semiconductor Engineering, Inc.Inventors: Chen-Chao WANG, Tsung-Tang TSAI, Chih-Yi HUANG
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Patent number: 11837557Abstract: A semiconductor device package comprises a semiconductor device, a first encapsulant surrounding the semiconductor device, a second encapsulant covering the semiconductor device and the first encapsulant, and a redistribution layer extending through the second encapsulant and electrically connected to the semiconductor device.Type: GrantFiled: November 29, 2021Date of Patent: December 5, 2023Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.Inventors: Peng Yang, Yuan-Feng Chiang, Po-Wei Lu
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Patent number: 11837572Abstract: An apparatus and method for manufacturing a semiconductor package structure are provided. The method includes: providing a process line comprising a first semiconductor manufacturing portion configured to provide a first operation including a first process step, and a second semiconductor manufacturing portion configured to provide a second operation including a second process step; passing a packaging structure through the second semiconductor manufacturing portion, wherein the second semiconductor manufacturing portion applies the second process step to the packaging structure; passing the packaging structure through the first semiconductor manufacturing portion, wherein the first semiconductor manufacturing portion applies the first process step to the packaging structure; and passing the packaging structure through the second semiconductor manufacturing portion again without applying the second process step thereon.Type: GrantFiled: June 2, 2021Date of Patent: December 5, 2023Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.Inventors: Chun-Min Wu, Cheng-Lin Li
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Patent number: 11837566Abstract: An electronic device package includes a circuit layer, a first semiconductor die, a second semiconductor die, a plurality of first conductive structures and a second conductive structure. The first semiconductor die is disposed on the circuit layer. The second semiconductor die is disposed on the first semiconductor die, and has an active surface toward the circuit layer. The first conductive structures are disposed between a first region of the second semiconductor die and the first semiconductor die, and electrically connecting the first semiconductor die to the second semiconductor die. The second conductive structure is disposed between a second region of the second semiconductor die and the circuit layer, and electrically connecting the circuit layer to the second semiconductor die.Type: GrantFiled: November 23, 2021Date of Patent: December 5, 2023Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.Inventors: Mei-Ju Lu, Chi-Han Chen, Chang-Yu Lin, Jr-Wei Lin, Chih-Pin Hung