Abstract: A semiconductor device package includes a number of interposers mounted to the carrier, wherein the number of interposers may be arranged in an irregular pattern.
Type:
Application
Filed:
September 6, 2022
Publication date:
December 29, 2022
Applicant:
Advanced Semiconductor Engineering, Inc.
Abstract: A package structure and a circuit layer structure are provided in the present disclosure. The package structure includes a wiring structure, a first electronic device, a second electronic device and at least one dummy trace. The wiring structure includes a plurality of interconnection traces. The first electronic device and the second electronic device are disposed on the wiring structure, and electrically connected to each other through the interconnection traces. The dummy trace is adjacent to the interconnection traces. A mechanical strength of the at least one dummy trace is less than a mechanical strength of one of the interconnection traces.
Type:
Application
Filed:
August 29, 2022
Publication date:
December 29, 2022
Applicant:
Advanced Semiconductor Engineering, Inc.
Abstract: A semiconductor package structure and a method of manufacturing the same are provided. The semiconductor package structure includes an electronic component having a first surface, a second surface opposite to the first surface and a circuit structure closer to the first surface than to the second surface. The semiconductor package structure also includes a passive component connected to the second surface of the electronic component. The semiconductor package structure further includes a conductive element extending into the electronic component and configured to electrically connect the circuit structure with the passive component.
Type:
Application
Filed:
June 23, 2021
Publication date:
December 29, 2022
Applicant:
Advanced Semiconductor Engineering, Inc.
Abstract: A semiconductor package structure is provided. The semiconductor package structure includes a carrier, a first electronic component, a second electronic component, a third electronic component, a fourth electronic component, and a connection element. The first electronic component is disposed over a surface of the carrier. The second electronic component is disposed over the first electronic component. The third electronic component is spaced apart from the first electronic component and disposed over the surface of the carrier. The fourth electronic component is disposed over the third electronic component. The connection element is electrically connecting the second electronic component to the fourth electronic component.
Type:
Application
Filed:
June 24, 2021
Publication date:
December 29, 2022
Applicant:
Advanced Semiconductor Engineering, Inc.
Abstract: An optical device includes a substrate, an electronic component and a lid. The electronic component is disposed on the substrate. The lid is disposed on the substrate. The lid has a first cavity over the electronic component and a second cavity over the first cavity. The sidewall of the second cavity is inclined.
Type:
Application
Filed:
August 30, 2022
Publication date:
December 29, 2022
Applicant:
Advanced Semiconductor Engineering, Inc.
Abstract: A semiconductor package device, a wearable device, and a temperature detection method are provided. The semiconductor package includes a substrate, an optical module, and a temperature module. The optical module is disposed on the substrate. The temperature module is disposed on the substrate and adjacent to the optical module. The temperature module comprises a semiconductor element and a temperature sensor stacked on the semiconductor element. The optical module is configured to detect a distance between the optical module and an object.
Type:
Application
Filed:
June 16, 2021
Publication date:
December 22, 2022
Applicant:
Advanced Semiconductor Engineering, Inc.
Abstract: The present disclosure provides a body-part tracking device and a body-part tracking method. The body-part tracking device includes a first electronic component and a first antenna element. The first antenna element is electrically connected to the first electronic component and configured to receive a first wave. The first electronic component is configured to, in response to the first wave, transmit a second wave.
Type:
Application
Filed:
June 18, 2021
Publication date:
December 22, 2022
Applicant:
Advanced Semiconductor Engineering, Inc.
Inventors:
Chi Sheng TSENG, Lu-Ming LAI, Hui-Chung LIU, I Hung WU, Kai-Sheng PAI
Abstract: The present disclosure provides a semiconductor device package including a substrate, a waveguide component, and an antenna pattern. The substrate includes a feeding element. The waveguide component is disposed over the substrate. The antenna pattern is disposed over the substrate. The waveguide component is substantially aligned with the feeding element and the antenna pattern.
Type:
Application
Filed:
June 17, 2021
Publication date:
December 22, 2022
Applicant:
Advanced Semiconductor Engineering, Inc.
Abstract: A semiconductor package structure and a method for manufacturing the same are provided. The method includes: providing a package body includes a first semiconductor device, wherein the first semiconductor device includes a plurality of first electrical contacts disposed adjacent to an active surface of the first semiconductor device; measuring the actual positions of the first electrical contacts of the first semiconductor device; providing a plurality of second electrical contacts outside the first semiconductor device; and forming an interconnection structure based on the actual positions of the first electrical contacts of the first semiconductor device and the positions of the second electrical contacts satisfying a predetermined electrical performance criterion by a mask-less process, so as to connect the first electrical contacts and the second electrical contacts and maintain signal integrity during transmission.
Type:
Application
Filed:
August 22, 2022
Publication date:
December 15, 2022
Applicant:
Advanced Semiconductor Engineering, Inc.
Abstract: A semiconductor package structure includes a conductive structure, at least one semiconductor element, an encapsulant, a redistribution structure and a plurality of bonding wires. The semiconductor element is disposed on and electrically connected to the conductive structure. The encapsulant is disposed on the conductive structure to cover the semiconductor element. The redistribution structure is disposed on the encapsulant, and includes a redistribution layer. The bonding wires electrically connect the redistribution structure and the conductive structure.
Type:
Application
Filed:
August 22, 2022
Publication date:
December 15, 2022
Applicant:
Advanced Semiconductor Engineering, Inc.
Inventors:
Chien-Wei CHANG, Shang-Wei YEH, Chung-Hsi WU, Min Lung HUANG
Abstract: A method for manufacturing a semiconductor package structure is provided. The method includes: (a) providing a substrate, wherein an upper surface of the substrate includes a predetermined region and an energy-absorbing region adjacent to the predetermined region; (b) disposing a first device in the predetermined region of the upper surface of the substrate; and (c) bonding the first device to the substrate by irradiating an upper surface of the first device with an energy-beam, wherein a center of the energy-beam is moved toward the energy-absorbing region from a first position before bonding.
Type:
Application
Filed:
June 10, 2021
Publication date:
December 15, 2022
Applicant:
Advanced Semiconductor Engineering, Inc.
Abstract: A semiconductor package includes a first die. The first die includes a semiconductor substrate. The semiconductor substrate has a first surface, a second surface opposite to the first surface, and a through hole between the first surface and the second surface and having an inner wall. The inner wall has a first lever arm. A length of the first lever arm is less than a thickness of the semiconductor substrate.
Type:
Application
Filed:
June 10, 2021
Publication date:
December 15, 2022
Applicant:
Advanced Semiconductor Engineering, Inc.
Abstract: The present disclosure provides a semiconductor device package including a substrate having a first surface and a second surface opposite to the first surface, a first package body disposed on the first surface, and a conductive layer covering the first package body and the substrate. The conductive layer includes a first portion on the top surface of the first package body and a second portion on the lateral surface of the first package body and a sidewall of the substrate. The second portion of the conductive layer has a tapered shape. A method for manufacturing a semiconductor device package is also provided.
Type:
Application
Filed:
June 11, 2021
Publication date:
December 15, 2022
Applicant:
Advanced Semiconductor Engineering, Inc.
Abstract: An apparatus and method for manufacturing a semiconductor package structure are provided. The method includes: providing a process line comprising a first semiconductor manufacturing portion configured to provide a first operation including a first process step, and a second semiconductor manufacturing portion configured to provide a second operation including a second process step; passing a packaging structure through the second semiconductor manufacturing portion, wherein the second semiconductor manufacturing portion applies the second process step to the packaging structure; passing the packaging structure through the first semiconductor manufacturing portion, wherein the first semiconductor manufacturing portion applies the first process step to the packaging structure; and passing the packaging structure through the second semiconductor manufacturing portion again without applying the second process step thereon.
Type:
Application
Filed:
June 2, 2021
Publication date:
December 8, 2022
Applicant:
Advanced Semiconductor Engineering, Inc.
Abstract: A semiconductor package and a method for manufacturing a semiconductor package are provided. The semiconductor package includes a first processing element, a first I/O element, a second processing element, and a second I/O element. The first processing element is on a substrate. The first I/O element is on the substrate and electrically connected to the first processing element. The second processing element is on the substrate. The second I/O element is on the substrate and electrically connected to the second processing element. The first I/O element is electrically connected to and physically separated from the second I/O element.
Type:
Application
Filed:
June 3, 2021
Publication date:
December 8, 2022
Applicant:
Advanced Semiconductor Engineering, Inc.
Inventors:
Chang Chi LEE, Jung Jui KANG, Chiu-Wen LEE, Li Chieh CHEN
Abstract: A semiconductor package structure includes a first electronic component, a conductive element and a first redistribution structure. The first electronic component has a first surface and a second surface opposite to the first surface, and includes a first conductive via. The first conductive via has a first surface exposed from the first surface of the first electronic component. The conductive element is disposed adjacent to the first electronic component. The conductive element has a first surface substantially coplanar with the first surface of the first conductive via of the first electronic component. The first redistribution structure is configured to electrically connect the first conductive via of the first electronic component and the conductive element.
Type:
Application
Filed:
May 28, 2021
Publication date:
December 1, 2022
Applicant:
Advanced Semiconductor Engineering, Inc.
Abstract: A semiconductor device and a method for manufacturing the same are provided. The semiconductor device includes a semiconductor substrate, at least one conductive via, a second insulation layer and a conductive layer. The conductive via is disposed in the semiconductor substrate and includes an interconnection metal and a first insulation layer around the interconnection metal. A portion of the first insulation layer defines an opening to expose the interconnection metal. The second insulation layer is disposed on a surface of the semiconductor substrate and in the opening. The conductive layer is electrically disconnected with the semiconductor substrate by the second insulation layer and electrically connected to the interconnection metal of the at least one conductive via.
Type:
Application
Filed:
May 28, 2021
Publication date:
December 1, 2022
Applicant:
Advanced Semiconductor Engineering, Inc.
Abstract: A semiconductor package device includes a first substrate, a second substrate and a first spacer. The first substrate includes a first divided pad. The second substrate includes a second divided pad disposed above the first divided pad. The first spacer is disposed between the first divided pad and the second divided pad. The first spacer is in contact with the first divided pad and the second divided pad.
Type:
Application
Filed:
August 9, 2022
Publication date:
December 1, 2022
Applicant:
Advanced Semiconductor Engineering, Inc.
Abstract: A manufacturing method for manufacturing a package structure is provided. The manufacturing method includes: (a) providing a carrier having a top surface and a lateral side surface, wherein the top surface includes a main portion and a flat portion connecting the lateral side surface, and a first included angle between the main portion and the flat portion is less than a second included angle between the main portion and the lateral side surface; (b) forming an under layer on the carrier to at least partially expose the flat portion; and (c) forming a dielectric layer on the under layer and covering the exposed flat portion.
Type:
Application
Filed:
May 27, 2021
Publication date:
December 1, 2022
Applicant:
Advanced Semiconductor Engineering, Inc.
Inventors:
Chia-Pin CHEN, Chia Sheng TIEN, Wan-Ting CHIU, Chi Long TSAI, Cyuan-Hong SHIH, Yen Liang CHEN
Abstract: A semiconductor device and a method for manufacturing the same are provided. The semiconductor device includes a semiconductor substrate, a conductive structure and at least one via structure. The conductive structure is disposed on an upper surface of the semiconductor substrate. The at least one via structure is disposed in the semiconductor substrate. A portion of the at least one via structure extends beyond the conductive structure.
Type:
Application
Filed:
May 28, 2021
Publication date:
December 1, 2022
Applicant:
Advanced Semiconductor Engineering, Inc.