Patents Assigned to Advanced Semiconductor Engineering
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Patent number: 11791227Abstract: An electronic device package and a method for manufacturing an electronic device package are provided. The electronic device package includes electronic device structure which includes a first electronic device and a first encapsulant, a second electronic device, and a second encapsulant. The first encapsulant encapsulates the first electronic device. The second electronic device is adjacent to the electronic device structure. The second encapsulant encapsulates the electronic device structure and the second electronic device. A first extension line along a lateral surface of the first electronic device and a second extension line along a lateral surface of the first encapsulant define a first angle, the second extension line along the lateral surface of the first encapsulant and a third extension line along a lateral surface of the second electronic device define a second angle, and the first angle is different from the second angle.Type: GrantFiled: May 11, 2021Date of Patent: October 17, 2023Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.Inventors: Kuoching Cheng, Yuan-Feng Chiang, Ya Fang Chan, Wen-Long Lu, Shih-Yu Wang
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Patent number: 11791281Abstract: A package substrate and method of manufacturing a package substrate and a semiconductor device package are provided. The package substrate includes a circuit layer, a molding layer and a sacrificial layer. The circuit layer includes conductive traces and conductive pads. The molding layer has an upper surface and a lower surface opposite to the upper surface, wherein the molding layer partially covers the conductive traces and the conductive pads, and first surfaces of the conductive traces and first surfaces of the conductive pads are exposed from the upper surface of the molding layer. The sacrificial layer covers the lower surface of the molding layer, second surfaces of the conductive pads.Type: GrantFiled: March 19, 2020Date of Patent: October 17, 2023Assignees: ADVANCED SEMICONDUCTOR ENGINEERING, INC., PHOENIX PIONEER TECHNOLOGY CO., LTD.Inventors: You-Lung Yen, Pao-Hung Chou, Chun-Hsien Yu
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Patent number: 11792565Abstract: An electronic module is provided. The electronic module includes a first transducer and a second transducer. The first transducer is configured to radiate a first ultrasonic wave. The second transducer is configured to radiate a second ultrasonic wave. A location of the first transducer is configured to be adjustable with respect to the second transducer.Type: GrantFiled: April 27, 2021Date of Patent: October 17, 2023Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.Inventors: Chih Lung Lin, Kuei-Hao Tseng, Kai Hung Wang
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Patent number: 11791280Abstract: A semiconductor device package includes a substrate, a first electronic component, a second electronic component, a package body and a shield. The substrate has a first surface and a second surface opposite to the first surface. The substrate defines a cavity from the second surface extending into the substrate. The first electronic component is disposed on the first surface of the substrate. The second electronic component is disposed within the cavity of the substrate. The package body is disposed on a portion of the first surface of the substrate and covers the first electronic component. The shield is disposed on external surfaces of the package body.Type: GrantFiled: August 30, 2021Date of Patent: October 17, 2023Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.Inventors: Li-Hua Tai, Pai-Chou Liu, Yun-Chih Fei, Wen-Pin Huang, Sheng-Hong Zheng
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Patent number: 11791245Abstract: An electronic package includes a patterned conductive layer and at least one conductive protrusion on the patterned conductive layer. The at least one conductive protrusion has a first top surface. The patterned conductive layer and the at least one conductive protrusion define a space. The electronic package further includes a first electronic component disposed in the space and a plurality of conductive pillars on the first electronic component. The conductive pillars have a second top surface. The first top surface is substantially level with the second top surface.Type: GrantFiled: August 5, 2021Date of Patent: October 17, 2023Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.Inventors: You-Lung Yen, Bernd Karl Appelt, Kay Stefan Essig
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Publication number: 20230326861Abstract: An electronic package is provided. The electronic package includes a first processing component, a second processing component, and a first memory unit. The first memory unit is over the first processing component and the second processing component. The first processing component and the second processing component are configured to access data stored in the first memory unit.Type: ApplicationFiled: April 7, 2022Publication date: October 12, 2023Applicant: Advanced Semiconductor Engineering, Inc.Inventors: Hung-Yi LIN, Cheng-Yuan KUNG
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Publication number: 20230326889Abstract: An electronic package is provided. The electronic package includes a processing component and a memory unit. The processing component has a side including a first region and a second region distinct from the first region. The memory unit is disposed over the first region. The first region is configured to provide interconnection between the processing component and the memory unit, and the second region is configured to provide external connection.Type: ApplicationFiled: April 7, 2022Publication date: October 12, 2023Applicant: Advanced Semiconductor Engineering, Inc.Inventors: Hung-Yi Lin, Cheng-Yuan Kung
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Publication number: 20230324308Abstract: An electronic device is disclosed. The electronic device includes a carrier, an optical component disposed on the carrier and a humidity indicator within the electronic package. A position of the humidity indicator within the electronic package is arranged such that at least a part of the humidity indicator is visible from a viewpoint outside of the electronic package.Type: ApplicationFiled: April 8, 2022Publication date: October 12, 2023Applicant: Advanced Semiconductor Engineering, Inc.Inventors: Shu Ting MAI, Tzu Hsing CHIANG
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Publication number: 20230326878Abstract: A semiconductor device package and a method for manufacturing a semiconductor device package are provided. The semiconductor device package includes a substrate, a clip, and a support structure. The clip is disposed on the substrate. The clip includes a first portion and a second portion separated from each other by a slit. The support structure is above the substrate and supports the clip. The support structure has a first surface and a second surface facing the first surface, and the first surface and the second surface define a gap.Type: ApplicationFiled: June 13, 2023Publication date: October 12, 2023Applicant: Advanced Semiconductor Engineering, Inc.Inventors: Chia Hsiu HUANG, Chun Chen CHEN, Wei Chih CHO, Shao-Lun YANG
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Publication number: 20230327333Abstract: A semiconductor device package includes a substrate, a first antenna pattern and a second antenna pattern. The substrate has a first surface and a second surface opposite to the first surface. The first antenna pattern is disposed over the first surface of the substrate. The first antenna pattern has a first bandwidth. The second antenna pattern is disposed over the first antenna pattern. The second antenna pattern has a second bandwidth different from the first bandwidth. The first antenna pattern and the second antenna pattern are at least partially overlapping in a direction perpendicular to the first surface of the substrate.Type: ApplicationFiled: June 6, 2023Publication date: October 12, 2023Applicant: Advanced Semiconductor Engineering, Inc.Inventors: Shao-En HSU, Huei-Shyong CHO, Shih-Wen LU
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Publication number: 20230327336Abstract: An electronic device is disclosed. The electronic device includes a carrier and a first interposer disposed on the carrier. The first interposer has a first region configured for providing an external electrical connection to outside the electronic device and a second region distinct from the first region. The electronic device also includes a first antenna component disposed on the second region of the first interposer.Type: ApplicationFiled: April 8, 2022Publication date: October 12, 2023Applicant: Advanced Semiconductor Engineering, Inc.Inventors: Jenchun CHEN, Shyue-Long LOUH
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Patent number: 11784111Abstract: A semiconductor device and a method for manufacturing the same are provided. The semiconductor device includes a semiconductor substrate, at least one conductive via, a second insulation layer and a conductive layer. The conductive via is disposed in the semiconductor substrate and includes an interconnection metal and a first insulation layer around the interconnection metal. A portion of the first insulation layer defines an opening to expose the interconnection metal. The second insulation layer is disposed on a surface of the semiconductor substrate and in the opening. The conductive layer is electrically disconnected with the semiconductor substrate by the second insulation layer and electrically connected to the interconnection metal of the at least one conductive via.Type: GrantFiled: May 28, 2021Date of Patent: October 10, 2023Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.Inventors: Cheng-Yuan Kung, Hung-Yi Lin, Chin-Cheng Kuo, Wu Chou Hsu
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Patent number: 11784296Abstract: A semiconductor device package includes a carrier, a semiconductor device, a lid, a conductive post, a first patterned conductive layer, a conductive element disposed between the first conductive post and the first patterned conductive layer, and an adhesive layer disposed between the lid and the carrier. The conductive post is electrically connected to the first patterned conductive layer. The semiconductor device is electrically connected to the first patterned conductive layer. The lid is disposed on the carrier, and the lid includes a second patterned conductive layer electrically connected to the first conductive post.Type: GrantFiled: December 28, 2021Date of Patent: October 10, 2023Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.Inventors: Mei-Yi Wu, Lu-Ming Lai, Yu-Ying Lee, Yung-Yi Chang
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Patent number: 11784110Abstract: A semiconductor package may include a substrate; a microelectromechanical device disposed on the substrate; an interconnection structure connecting the substrate to the microelectromechanical device; and a metallic sealing structure surrounding the interconnection structure.Type: GrantFiled: November 30, 2020Date of Patent: October 10, 2023Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.Inventors: Chung Hao Chen, Chin-Cheng Kuo
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Patent number: 11784174Abstract: An optical package structure and a method for manufacturing an optical package structure are provided. The optical package structure includes a first die, a bumping structure, and a second die. The first die is on a carrier. The bumping structure is over the first die. The bumping structure includes a light-transmitting portion and a light-blocking portion embedded in the light-transmitting portion. The second die is electrically connected to the carrier. The light-blocking portion of the bumping structure is free from covering the second die.Type: GrantFiled: February 4, 2021Date of Patent: October 10, 2023Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.Inventor: Ying-Chung Chen
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Patent number: 11784152Abstract: A semiconductor device package includes a first electronic device and a second electronic device. The first electronic device includes a first redistribution layer (RDL) including a circuit layer. The second electronic device is disposed on the first RDL of the first electronic device. The second electronic device includes an encapsulant and a patterned conductive layer. The encapsulant has a first surface facing the first RDL of the first electronic device, and a second surface opposite to the first surface. The patterned conductive layer is disposed at the second surface of the encapsulant, and is configured to be electrically coupled to the circuit layer of the first RDL of the first electronic device.Type: GrantFiled: June 14, 2021Date of Patent: October 10, 2023Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.Inventors: Ming Hsien Chu, Chi-Yu Wang
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Publication number: 20230317502Abstract: A method for manufacturing an electronic package and a suction device are provided. The method includes: providing an electronic component having a first surface and including at least one conductive stud on the first surface; providing a suction device having at least one recess; and moving the electronic component with the suction device, wherein an edge of the at least one recess does not overlap the at least one conductive stud from a top view while moving the electronic component with the suction device.Type: ApplicationFiled: April 1, 2022Publication date: October 5, 2023Applicant: Advanced Semiconductor Engineering, Inc.Inventors: Chun Hung TSAI, Chenghan SHE, Kuo-Chih HUANG, Kuan-Lin YEH
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Publication number: 20230317589Abstract: A package structure includes a first die, a second die, an encapsulant and at least one electrical contact. The first die has an active surface. The second die is disposed on the first die, and has an active surface and a backside surface opposite to the active surface. The active surface of the second die is closer to the active surface of the first die than the backside surface of the second die is. The encapsulant encapsulates the first die and the second die, and has a top surface far away from the active surface of the first die. The electrical contact is exposed from the top surface of the encapsulant and is configured for connecting at least one conductive wire.Type: ApplicationFiled: March 31, 2022Publication date: October 5, 2023Applicant: Advanced Semiconductor Engineering, Inc.Inventor: Yu-Ying Lee
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Patent number: 11776917Abstract: The present disclosure provides an electronic package and method of manufacturing the same. The electronic package includes an electronic device including a first carrier and a first electronic component disposed on the first carrier, a second carrier adjacent to the first carrier of the electronic device, and a conductive layer at least partially covering the electronic device, and separating the electronic device from the second carrier.Type: GrantFiled: July 16, 2020Date of Patent: October 3, 2023Assignee: ADVANCED SEMICONDUCTOR ENGINEERING KOREA, INC.Inventors: Seokbong Kim, Eunshim Lee
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Patent number: 11776862Abstract: The present disclosure relates to a semiconductor device package, which includes a carrier, a lid, a first adhesive layer and a constraint structure. The carrier includes a surface and a first conductive pad on the surface of the carrier. The lid includes a first portion and a second portion separated from the first portion on the surface of the carrier. The first conductive pad is disposed between the first portion of the lid and the surface of the carrier. The first adhesive layer includes a first portion between the first portion of the lid and the first conductive pad. The constraint structure surrounds the first adhesive layer.Type: GrantFiled: September 21, 2020Date of Patent: October 3, 2023Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.Inventors: Chun-Han Chen, Hsun-Wei Chan, Mei-Yi Wu