Abstract: A semiconductor device package includes a carrier provided with a first conductive element, a second conductive element arranged on a semiconductor disposed on the carrier, and a second semiconductor device disposed on and across the first conductive element and the first semiconductor device, wherein the first conductive element having a surface that is substantially coplanar with a surface of the second conductive element.
Type:
Grant
Filed:
June 1, 2021
Date of Patent:
October 3, 2023
Assignee:
ADVANCED SEMICONDUCTOR ENGINEERING, INC.
Abstract: The present disclosure relates to a wireless communication module. The wireless communication module includes a first antenna layer and a second antenna layer non-coplanar with the second antenna layer. An electromagnetic wave of the first antenna and the second antenna are configured to have far-field interference to each other.
Type:
Grant
Filed:
December 23, 2020
Date of Patent:
October 3, 2023
Assignee:
ADVANCED SEMICONDUCTOR ENGINEERING, INC.
Abstract: A substrate includes a first dielectric layer having a first surface and a second dielectric layer having a first surface disposed adjacent to the first surface of the first dielectric layer. The substrate further includes a first conductive via disposed in the first dielectric layer and having a first end adjacent to the first surface of the first dielectric layer and a second end opposite the first end. The substrate further includes a second conductive via disposed in the second dielectric layer and having a first end adjacent to the first surface of the second dielectric layer. A width of the first end of the first conductive via is smaller than a width of the second end of the first conductive via, and a width of the first end of the second conductive via is smaller than the width of the first end of the first conductive via.
Type:
Grant
Filed:
August 9, 2021
Date of Patent:
October 3, 2023
Assignee:
ADVANCED SEMICONDUCTOR ENGINEERING, INC.
Abstract: An optical communication package structure includes a wiring structure, at least one via structure, a redistribution structure, at least one optical device and at least one electrical device. The wiring structure includes a main portion and a conductive structure disposed on an upper surface of the main portion. The main portion defines at least one through hole extending through the main portion. The via structure is disposed in the at least one through hole of the main portion and electrically connected to the conductive structure. The redistribution structure is disposed on a lower surface of the main portion and electrically connected to the via structure. The optical device is disposed adjacent to the upper surface of the main portion and electrically connected to the conductive structure. The electrical device is disposed on and electrically connected to the conductive structure.
Type:
Grant
Filed:
April 12, 2022
Date of Patent:
October 3, 2023
Assignee:
ADVANCED SEMICONDUCTOR ENGINEERING, INC.
Abstract: A semiconductor device package includes a carrier, a first interposer disposed and a second interposer. The second interposer is stacked on the first interposer, and the first interposer is mounted to the carrier. The combination of the first interposer and the second interposer is substantially T-shaped.
Type:
Grant
Filed:
August 17, 2021
Date of Patent:
October 3, 2023
Assignee:
ADVANCED SEMICONDUCTOR ENGINEERING, INC.
Abstract: The present disclosure provides a semiconductor package structure and a method of manufacturing the same. The semiconductor package structure includes a semiconductor structure, a conductive trace and a tenting structure. The semiconductor structure has a first surface, a second surface and a third surface extending between the first surface and the second surface, and the first surface, the second surface and the third surface define a through-silicon via recessed from the first surface. The conductive trace is disposed adjacent to the first surface, the second surface and the third surface of the semiconductor structure. The tenting structure covering the TSV of the semiconductor structure. A cavity is defined by the tenting structure and the TSV.
Type:
Grant
Filed:
May 7, 2021
Date of Patent:
October 3, 2023
Assignee:
ADVANCED SEMICONDUCTOR ENGINEERING, INC.
Abstract: A semiconductor device package is disclosed. The semiconductor device package includes a carrier, a first electronic component disposed on the carrier and a support component disposed on the carrier. The semiconductor device package also includes a second electronic component disposed on the first electronic component and supported by the support component.
Type:
Application
Filed:
March 25, 2022
Publication date:
September 28, 2023
Applicant:
Advanced Semiconductor Engineering, Inc.
Abstract: An electronic device is disclosed. The electronic device includes a first part, a second part adjacent to the first part and a rotational shaft. The rotational shaft includes an antenna and configured to allow the first part and the second part to rotate about a rotation axis defined by the rotational shaft.
Type:
Application
Filed:
March 24, 2022
Publication date:
September 28, 2023
Applicant:
Advanced Semiconductor Engineering, Inc.
Abstract: An electronic device is provided. The electronic device includes a flexible body having a first portion and a second portion, an electronic component in the first portion and the second portion of the flexible body, a first magnetic element in the first portion of the flexible body and a second magnetic element in the second portion of the flexible body. The first magnetic and the second magnetic generate a repulsive force with each other when the flexible body is bent and the first portion and the second portion of the flexible body are moved toward each other.
Type:
Application
Filed:
March 25, 2022
Publication date:
September 28, 2023
Applicant:
Advanced Semiconductor Engineering, Inc.
Abstract: A semiconductor package structure includes a first electronic component, a conductive element and a first redistribution structure. The first electronic component has a first surface and a second surface opposite to the first surface, and includes a first conductive via. The first conductive via has a first surface exposed from the first surface of the first electronic component. The conductive element is disposed adjacent to the first electronic component. The conductive element has a first surface substantially coplanar with the first surface of the first conductive via of the first electronic component. The first redistribution structure is configured to electrically connect the first conductive via of the first electronic component and the conductive element.
Type:
Grant
Filed:
May 28, 2021
Date of Patent:
September 26, 2023
Assignee:
ADVANCED SEMICONDUCTOR ENGINEERING, INC.
Abstract: A semiconductor device package includes a carrier, an electronic component and a connector. The electronic component is disposed on the carrier. The connector is disposed on the carrier and electrically connected to the electronic component. A S 11 parameter of the connector is less than ?20 dB.
Type:
Application
Filed:
May 23, 2023
Publication date:
September 21, 2023
Applicant:
Advanced Semiconductor Engineering, Inc.
Inventors:
Yuanhao YU, Cheng Yuan CHEN, Chun Chen CHEN, Jiming LI, Chien-Wen TU
Abstract: A semiconductor package includes: (1) a package substrate including an upper surface; (2) a semiconductor device disposed adjacent to the upper surface of the package substrate, the semiconductor device including an inactive surface; and (3) an antenna substrate disposed on the inactive surface of the semiconductor device.
Type:
Application
Filed:
May 30, 2023
Publication date:
September 21, 2023
Applicant:
Advanced Semiconductor Engineering, Inc.
Abstract: An optical device includes a first circuit layer, a light detector, a first conductive pillar and an encapsulant. The first circuit layer has an interconnection layer and a dielectric layer. The light detector is disposed on the first circuit layer. The light detector has a light detecting area facing away from the first circuit layer and a backside surface facing the first circuit layer. The first conductive pillar is disposed on the first circuit layer and spaced apart from the light detector. The first conductive pillar is electrically connected to the interconnection layer of the first circuit layer. The encapsulant is disposed on the first circuit layer and covers the light detector and the first conductive pillar. The light detector is electrically connected to the interconnection layer of the first circuit layer through the first conductive pillar. The backside surface of the light detector is exposed from the encapsulant.
Type:
Grant
Filed:
September 28, 2021
Date of Patent:
September 19, 2023
Assignee:
ADVANCED SEMICONDUCTOR ENGINEERING, INC.
Inventors:
Yu-Pin Tsai, Tsung-Yueh Tsai, Teck-Chong Lee
Abstract: The present disclosure provides a semiconductor device package. The semiconductor device package includes a conductive pillar having a first surface, a second surface, and a lateral surface extending between the first surface and the second surface. The lateral surface has a first part and a second part connected to the first part. The semiconductor device package also includes a barrier layer in contact with the first part of the lateral surface of the conductive pillar and an encapsulant in contact with the second part of the lateral surface of the conductive pillar. The semiconductor device package also includes a first flowable conductive material disposed on the first surface of the conductive pillar. A method of manufacturing a semiconductor device package is also disclosed.
Type:
Grant
Filed:
August 14, 2020
Date of Patent:
September 19, 2023
Assignee:
ADVANCED SEMICONDUCTOR ENGINEERING, INC.
Abstract: A semiconductor device package includes a substrate, a reflector, a radiator and a first director. The reflector is disposed on a surface of the substrate. The radiator is disposed over the reflector. The first director is disposed over the radiator. The reflector, the radiator and the first director have different elevations with respect to the surface of the substrate. The radiator and the first director define an antenna.
Type:
Grant
Filed:
June 8, 2020
Date of Patent:
September 12, 2023
Assignee:
ADVANCED SEMICONDUCTOR ENGINEERING, INC.
Inventors:
Yuanhao Yu, Cheng-Lin Ho, Yu-Lin Shih, Shih-Chun Li
Abstract: A semiconductor package structure and a method for manufacturing a semiconductor package structure are provided. The semiconductor package structure includes an electronic component, a conductive contact, and a first shielding layer. The electronic component has a first surface, a lateral surface angled with the first surface, and a second surface opposite to the first surface. The conductive contact is connected to the first surface of the electronic component. The first shielding layer is disposed on the lateral surface of the electronic component and a portion of the first surface of the electronic component. The first shielding layer contacts the conductive contact.
Type:
Grant
Filed:
December 3, 2020
Date of Patent:
September 12, 2023
Assignee:
ADVANCED SEMICONDUCTOR ENGINEERING, INC.
Abstract: A semiconductor package structure is provided. The semiconductor package structure includes a carrier, a first electronic component, a second electronic component, a third electronic component, a fourth electronic component, and a connection element. The first electronic component is disposed over a surface of the carrier. The second electronic component is disposed over the first electronic component. The third electronic component is spaced apart from the first electronic component and disposed over the surface of the carrier. The fourth electronic component is disposed over the third electronic component. The connection element is electrically connecting the second electronic component to the fourth electronic component.
Type:
Grant
Filed:
June 24, 2021
Date of Patent:
September 12, 2023
Assignee:
ADVANCED SEMICONDUCTOR ENGINEERING, INC.
Abstract: A method for manufacturing a semiconductor package includes: (a) providing a substrate structure, wherein the substrate structure includes a chip attach area, a bottom area opposite to the chip attach area, a lower side rail surrounding the bottom area, a first lower structure and a second lower structure, wherein the first lower structure is disposed in a first lower region of the lower side rail, and a second lower occupancy ratio is greater than a first lower occupancy ratio; (b) attaching at least one semiconductor chip to the chip attach area; and (c) forming an encapsulant to cover the at least one semiconductor chip.
Type:
Grant
Filed:
May 24, 2022
Date of Patent:
September 12, 2023
Assignee:
ADVANCED SEMICONDUCTOR ENGINEERING, INC.
Abstract: A package substrate and method of manufacturing a package substrate and a semiconductor device package are provided. The package substrate includes a circuit layer, a molding layer and a sacrificial layer. The circuit layer includes conductive traces and conductive pads. The molding layer has an upper surface and a lower surface opposite to the upper surface, wherein the molding layer partially covers the conductive traces and the conductive pads, and first surfaces of the conductive traces and first surfaces of the conductive pads are exposed from the upper surface of the molding layer. The sacrificial layer covers the lower surface of the molding layer, second surfaces of the conductive pads.
Abstract: An electronic structure, an electronic package structure and method of manufacturing an electronic device are provided. The electronic structure includes a carrier and a protection layer. The carrier includes a first pad, a second pad and a first dielectric layer. The first pad is at a side of the carrier and configured to bond with a conductive pad. The second pad is at the side of carrier and configured to electrically connect an exterior circuit. The first dielectric layer includes a first portion around the first pad and a second portion around the second pad, wherein a top surface of the first portion and a top surface of the second portion are substantially coplanar. The protection layer is on the second pad and covers the second pad.
Type:
Grant
Filed:
July 16, 2021
Date of Patent:
September 5, 2023
Assignee:
ADVANCED SEMICONDUCTOR ENGINEERING, INC.