Patents Assigned to Advanced Semiconductor Engineering
  • Publication number: 20220384381
    Abstract: An electronic device package is provided. The electronic device package includes a redistribution layer (RDL), a first electronic component and an interconnector. The RDL includes a topmost circuit layer, and the topmost circuit layer includes a conductive trace. The first electronic component is disposed over the RDL. The interconnector is disposed between the RDL and the first electronic component. A direction is defined by extending from a center of the first electronic component toward an edge of the first electronic component, and the direction penetrates a first sidewall and a second sidewall of the interconnector, the second sidewall is farther from the center of the first electronic component than the first sidewall is, and the conductive trace is outside a projection region of the second sidewall.
    Type: Application
    Filed: May 28, 2021
    Publication date: December 1, 2022
    Applicant: Advanced Semiconductor Engineering, Inc.
    Inventors: Chung-Hung LAI, Chin-Li KAO, Chih-Yi HUANG, Teck-Chong LEE
  • Publication number: 20220377161
    Abstract: At least some embodiments of the present disclosure relate to a semiconductor device package. The semiconductor device package comprises a substrate, an antenna, and an active component. The antenna is disposed at least partially within the substrate. The active component is disposed on the substrate and electrically connected to the antenna. A location of the antenna is configured to be adjustable with respect to a location of the active component.
    Type: Application
    Filed: May 19, 2021
    Publication date: November 24, 2022
    Applicant: Advanced Semiconductor Engineering, Inc.
    Inventors: Yuanhao YU, Chung Ju YU, Jui-Hsien WANG, Chai-Chi LIN, Hong Jie CHEN
  • Publication number: 20220373670
    Abstract: At least some embodiments of the present disclosure relate to a wearable device. The wearable device comprises a substrate, a detecting module disposed on the substrate, and a control module disposed on the substrate. The control module is electrically connected to the detecting module. The control module is configured to receive a signal from the detecting module and to control the wearable device in response to the signal.
    Type: Application
    Filed: May 19, 2021
    Publication date: November 24, 2022
    Applicant: Advanced Semiconductor Engineering, Inc.
    Inventors: Yuanhao YU, Chung Ju YU, Wei-Fan WU, Chai-Chi LIN, Hong Jie CHEN
  • Publication number: 20220375809
    Abstract: A semiconductor device package includes a first substrate, a second substrate, and a first electronic component between the first substrate and the second substrate. The first electronic component has a first surface facing the first substrate and a second surface facing the second substrate. The semiconductor device package also includes a first electrical contact disposed on the first surface of the first electronic component and electrically connecting the first surface of the first electronic component with the first substrate. The semiconductor device package also includes a second electrical contact disposed on the second surface of the first electronic component and electrically connecting the second surface of the first electronic component with the second substrate. A method of manufacturing a semiconductor device package is also disclosed.
    Type: Application
    Filed: August 8, 2022
    Publication date: November 24, 2022
    Applicant: Advanced Semiconductor Engineering, Inc.
    Inventors: Ming-Han WANG, Ian HU
  • Publication number: 20220367369
    Abstract: A semiconductor package structure includes at least one first semiconductor die, at least one second semiconductor die and an encapsulant. The first semiconductor die has a first surface and includes a plurality of first pillar structures disposed adjacent to the first surface. The second semiconductor die is electrically connected to the first semiconductor die. The encapsulant covers the first semiconductor die and the second semiconductor die. A lower surface of the encapsulant is substantially coplanar with an end surface of each of the first pillar structures and a surface of the second semiconductor die.
    Type: Application
    Filed: August 2, 2022
    Publication date: November 17, 2022
    Applicant: Advanced Semiconductor Engineering, Inc.
    Inventors: Hsu-Nan FANG, Chun-Jun ZHUANG
  • Publication number: 20220367308
    Abstract: A semiconductor device package includes a carrier and an encapsulant disposed on the carrier. At least one portion of the encapsulant is spaced from the carrier by a space.
    Type: Application
    Filed: July 28, 2022
    Publication date: November 17, 2022
    Applicant: Advanced Semiconductor Engineering, Inc.
    Inventors: Tun-Ching PI, Yen-Chi HUANG, Hao-Chih HSIEH, Jin Han SHIH
  • Publication number: 20220367306
    Abstract: An electronic device package includes an encapsulated electronic component, a substrate, a conductor and a buffer layer. The encapsulated electronic component includes a redistribution layer (RDL) and an encapsulation layer. The first surface is closer to the RDL than the second surface is. The encapsulation layer includes a first surface, and a second surface opposite to the first surface. The substrate is disposed on the second surface of the encapsulation layer. The conductor is disposed between the substrate and the encapsulated electronic component, and electrically connecting the substrate to the encapsulated electronic component. The buffer layer is disposed between the substrate and the encapsulated electronic component and around the conductor.
    Type: Application
    Filed: May 11, 2021
    Publication date: November 17, 2022
    Applicant: Advanced Semiconductor Engineering, Inc.
    Inventors: Chia-Pin CHEN, Chia-Sheng TIEN, Wan-Ting CHIU, Chi Long TSAI
  • Publication number: 20220367304
    Abstract: An electronic device package and a method for manufacturing an electronic device package are provided. The electronic device package includes electronic device structure which includes a first electronic device and a first encapsulant, a second electronic device, and a second encapsulant. The first encapsulant encapsulates the first electronic device. The second electronic device is adjacent to the electronic device structure. The second encapsulant encapsulates the electronic device structure and the second electronic device. A first extension line along a lateral surface of the first electronic device and a second extension line along a lateral surface of the first encapsulant define a first angle, the second extension line along the lateral surface of the first encapsulant and a third extension line along a lateral surface of the second electronic device define a second angle, and the first angle is different from the second angle.
    Type: Application
    Filed: May 11, 2021
    Publication date: November 17, 2022
    Applicant: Advanced Semiconductor Engineering, Inc.
    Inventors: Kuoching CHENG, Yuan-Feng CHIANG, Ya Fang CHAN, Wen-Long LU, Shih-Yu WANG
  • Publication number: 20220367384
    Abstract: A semiconductor package structure and a method for manufacturing a semiconductor package structure are provided. The semiconductor package structure includes a substrate, a semiconductor device, an encapsulant, a balance structure, and a warpage-resistant layer. The semiconductor device is disposed on the substrate. The encapsulant encapsulates the semiconductor device. The balance structure is on the semiconductor device and contacting the encapsulant. The warpage-resistant layer is between the semiconductor device and the balance structure. The encapsulant contacts a lateral surface of the warpage-resistant layer.
    Type: Application
    Filed: May 14, 2021
    Publication date: November 17, 2022
    Applicant: Advanced Semiconductor Engineering, Inc.
    Inventors: You-Lung YEN, Bernd Karl APPELT, Kay Stefan ESSIG
  • Publication number: 20220367431
    Abstract: An optoelectronic device package includes a first redistribution layer (RDL), a first electronic die disposed over the first RDL, wherein an active surface of the first electronic die faces the first RDL. The optoelectronic device package further includes a second electronic die disposed over the first RDL, and a photonic die disposed over and electrically connected to the second electronic die. An active surface of the second electronic die is opposite to the first RDL.
    Type: Application
    Filed: May 13, 2021
    Publication date: November 17, 2022
    Applicant: Advanced Semiconductor Engineering, Inc.
    Inventor: Chi-Han CHEN
  • Publication number: 20220359362
    Abstract: The present disclosure provides a semiconductor package structure and a method of manufacturing the same. The semiconductor package structure includes a semiconductor structure, a conductive trace and a tenting structure. The semiconductor structure has a first surface, a second surface and a third surface extending between the first surface and the second surface, and the first surface, the second surface and the third surface define a through-silicon via recessed from the first surface. The conductive trace is disposed adjacent to the first surface, the second surface and the third surface of the semiconductor structure. The tenting structure covering the TSV of the semiconductor structure. A cavity is defined by the tenting structure and the TSV.
    Type: Application
    Filed: May 7, 2021
    Publication date: November 10, 2022
    Applicant: Advanced Semiconductor Engineering, Inc.
    Inventors: Wei-Wei LIU, Huei-Siang WONG
  • Publication number: 20220359363
    Abstract: A semiconductor package structure and a method for manufacturing a semiconductor package structure are provided. The semiconductor package structure includes a first package and a second package. The first package includes a first substrate, an electronic component, a trace layer, and a first conductive structure. The first substrate has a first surface and a second surface opposite to the first surface. The electronic component is embedded in the first substrate. The trace layer has an uppermost conductive layer embedded in the first substrate and exposed from the first surface of the first substrate. The first conductive structure electrically connects the trace layer to the second surface of the first substrate. The second package is disposed on the first surface of the first substrate of the first package.
    Type: Application
    Filed: May 7, 2021
    Publication date: November 10, 2022
    Applicant: Advanced Semiconductor Engineering, Inc.
    Inventors: You-Lung YEN, Bernd Karl APPELT, Kay Stefan ESSIG
  • Publication number: 20220359361
    Abstract: A semiconductor substrate and a manufacturing method thereof are provided. The semiconductor substrate includes a dielectric layer, a circuit layer, a first protection layer and a plurality of conductive posts. The dielectric layer has a first surface and a second surface that are opposite to each other. The circuit layer is embedded in the dielectric layer and is exposed from the first surface. The first protection layer covers a portion of the first circuit layer and defines a plurality of holes that expose a remaining portion of the first circuit layer. The conductive posts are formed in the holes.
    Type: Application
    Filed: July 25, 2022
    Publication date: November 10, 2022
    Applicant: Advanced Semiconductor Engineering, Inc.
    Inventors: Chun-Che LEE, Ming-Chiang LEE, Yuan-Chang SU, Tien-Szu CHEN, Chih-Cheng LEE, You-Lung YEN
  • Publication number: 20220361326
    Abstract: A semiconductor package device includes a first dielectric layer, a first interconnection layer, a second interconnection layer, and a second dielectric layer. The first dielectric layer has a first surface, a second surface opposite to the first surface and a lateral surface extending between the first surface and the second surface. The first interconnection layer is within the first dielectric layer. The second interconnection layer is on the second surface of the first dielectric layer and extends from the second surface of the first dielectric layer into the first dielectric layer to electrically connect to the first interconnection layer. The second dielectric layer covers the second surface and the lateral surface of the first dielectric layer and the second interconnection layer.
    Type: Application
    Filed: July 25, 2022
    Publication date: November 10, 2022
    Applicant: Advanced Semiconductor Engineering, Inc.
    Inventors: Ming-Ze LIN, Chia Ching CHEN, Yi Chuan DING
  • Publication number: 20220359425
    Abstract: A semiconductor device package includes an electronic component, an electrical contact and a reinforcement layer. The electronic component has a first conductive layer on a first surface of the electronic component. The electronic component has a through-silicon-via (TSV) penetrating the electronic component and electrically connected to the first conductive layer. The electrical contact is disposed on the first surface of the electronic component and electrically connected to the first conductive layer. The reinforcement layer is disposed on the first surface of the electronic component.
    Type: Application
    Filed: May 24, 2022
    Publication date: November 10, 2022
    Applicant: Advanced Semiconductor Engineering, Inc.
    Inventors: Hsu-Chiang SHIH, Hung-Yi LIN, Meng-Wei HSIEH, Yu Sheng CHANG, Hsiu-Chi LIU, Mark GERBER
  • Publication number: 20220352066
    Abstract: An electronic device package includes an encapsulated electronic component, a redistribution layer (RDL) and a conductive via. The RDL is disposed above the encapsulated electronic component. The RDL includes a circuit layer comprising a conductive pad including a pad portion having a curved edge and a center of curvature, and an extension portion protruding from the pad portion and having a curved edge and a center of curvature. The circuit layer further includes a dielectric layer above the RDL. The conductive via is disposed in the dielectric layer and connected to the conductive pad of the RDL. A center of the conductive via is closer to the center of curvature of the edge of the extension portion than to the center of curvature of the edge of the pad portion.
    Type: Application
    Filed: April 28, 2021
    Publication date: November 3, 2022
    Applicant: Advanced Semiconductor Engineering, Inc.
    Inventors: Shao-An CHEN, Chih-Yi HUANG, Ping Cing SHEN
  • Publication number: 20220346715
    Abstract: The present disclosure provides an electronic device. The electronic device includes a flexible element, and a sensing element adjacent to the flexible element and configured to detect a biosignal. The electronic device also includes an active component in the flexible element and electrically connected with the sensing element. A method of manufacturing an electronic device is also disclosed.
    Type: Application
    Filed: April 29, 2021
    Publication date: November 3, 2022
    Applicant: Advanced Semiconductor Engineering, Inc.
    Inventors: Chih Lung LIN, Kuei-Hao TSENG, Te Kao TSUI, Kai Hung WANG, Hung-I LIN
  • Publication number: 20220353619
    Abstract: A semiconductor package device and a method of manufacturing a semiconductor package device are provided. The semiconductor package device includes a substrate, a first electronic component, and an encapsulation layer. The substrate has a first surface, a second surface opposite to the first surface, and a first opening extending from the first surface to the second surface. The first electronic component is disposed on the first surface of the substrate. The encapsulation layer is formed on the second surface of the substrate. The encapsulation layer includes a chamber connected to the first opening, and a width of the first opening is smaller than a width of the chamber.
    Type: Application
    Filed: April 29, 2021
    Publication date: November 3, 2022
    Applicant: Advanced Semiconductor Engineering, Inc.
    Inventor: Chang-Lin YEH
  • Publication number: 20220344230
    Abstract: The present disclosure provides a semiconductor device package including a first device, a second device, and a spacer. The first device includes a substrate having a first dielectric constant. The second device includes a dielectric element, an antenna, and a reinforcing element. The dielectric element has a second dielectric constant less than the first dielectric constant. The antenna is at least partially within the dielectric element. The reinforcing element is disposed on the dielectric element, and the reinforcing element has a third dielectric constant greater than the first dielectric constant.
    Type: Application
    Filed: April 23, 2021
    Publication date: October 27, 2022
    Applicant: Advanced Semiconductor Engineering, Inc.
    Inventor: Wei-Tung CHANG
  • Publication number: 20220345812
    Abstract: An electronic module is provided. The electronic module includes a first transducer and a second transducer. The first transducer is configured to radiate a first ultrasonic wave. The second transducer is configured to radiate a second ultrasonic wave. The first transducer and the second transducer are disposed on noncoplanar surfaces.
    Type: Application
    Filed: April 27, 2021
    Publication date: October 27, 2022
    Applicant: Advanced Semiconductor Engineering, Inc.
    Inventors: Chih Lung LIN, Kuei-Hao TSENG, Kai Hung WANG