Patents Assigned to Advanced Semiconductor Engineering
  • Method for manufacturing semiconductor package structure
    Patent number: 11817421
    Abstract: A method for manufacturing a semiconductor package structure is provided. The method includes: (a) providing a substrate, wherein an upper surface of the substrate includes a predetermined region and an energy-absorbing region adjacent to the predetermined region; (b) disposing a first device in the predetermined region of the upper surface of the substrate; and (c) bonding the first device to the substrate by irradiating an upper surface of the first device with an energy-beam, wherein a center of the energy-beam is moved toward the energy-absorbing region from a first position before bonding.
    Type: Grant
    Filed: June 10, 2021
    Date of Patent: November 14, 2023
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventors: Yi Dao Wang, Tung Yao Lin, Rong He Guo
  • ELECTRONIC PACKAGE
    Publication number: 20230361014
    Abstract: An electronic package includes an electronic structure, a first circuit pattern structure, a plurality of first solders and an encapsulant. The electronic structure includes an electronic device, and has a top surface and a bottom surface opposite to the top surface. The first circuit pattern structure is disposed over the top surface of the electronic structure. The first solders are disposed on the bottom surface of the electronic structure. The encapsulant encapsulates the electronic structure. At least a portion of the encapsulant is disposed between at least two of the plurality of first solders.
    Type: Application
    Filed: May 6, 2022
    Publication date: November 9, 2023
    Applicant: Advanced Semiconductor Engineering, Inc.
    Inventor: Cheng-Lin HO
  • DEVICE PACKAGE
    Publication number: 20230361060
    Abstract: An electronic device package includes a first substrate, a second substrate and a conductive layer. The first substrate includes a first bonding pad, and a cavity exposing the first bonding pad. The second substrate is laminated on the first substrate. The second substrate includes a second bonding pad at least partially inserting into the cavity of the first substrate. The conductive layer is disposed in the cavity and at least between the first bonding pad and the second bonding pad to connect the first bonding pad and the second bonding pad.
    Type: Application
    Filed: July 18, 2023
    Publication date: November 9, 2023
    Applicant: Advanced Semiconductor Engineering, Inc.
    Inventors: Cheng-Nan LIN, Wei-Tung CHANG, Jen-Chieh KAO, Huei-Shyong CHO
  • Semiconductor device package and method of manufacturing the same
    Patent number: 11811957
    Abstract: At least some embodiments of the present disclosure relate to a semiconductor device package. The semiconductor device package comprises a substrate, an antenna, and an active component. The antenna is disposed at least partially within the substrate. The active component is disposed on the substrate and electrically connected to the antenna. A location of the antenna is configured to be adjustable with respect to a location of the active component.
    Type: Grant
    Filed: May 19, 2021
    Date of Patent: November 7, 2023
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventors: Yuanhao Yu, Chung Ju Yu, Jui-Hsien Wang, Chai-Chi Lin, Hong Jie Chen
  • Antenna module
    Patent number: 11811131
    Abstract: The present disclosure provides an antenna module. The antenna module includes an antenna layer, a ground layer, and an electronic component. The ground layer is disposed over the antenna layer. The electronic component is disposed between the antenna layer and the ground layer.
    Type: Grant
    Filed: December 23, 2020
    Date of Patent: November 7, 2023
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventors: Cheng-Yu Ho, Meng-Wei Hsieh
  • Semiconductor package structures and methods of manufacturing the same
    Patent number: 11806710
    Abstract: A semiconductor package structure includes a substrate, a die and a conductive structure. The die is disposed on or within the substrate. The die has a first surface facing away from the substrate and includes a sensing region and a pad at the first surface of the die. The first surface of the die has a first edge and a second edge opposite to the first edge. The sensing region is disposed adjacent to the first edge. The pad is disposed away from the first edge. The conductive structure electrically connects the pad and the substrate. The sensing region has a first end distal to the first edge of the first surface of the die. A distance from the first end of the sensing region to a center of the pad is equal to or greater than a distance from the first end of the sensing region to the first edge of the first surface of the die.
    Type: Grant
    Filed: June 4, 2020
    Date of Patent: November 7, 2023
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventors: Hsiao-Yen Lee, Ying-Te Ou, Chin-Cheng Kuo, Chung Hao Chen
  • POWER MODULE PACKAGING STRUCTURE
    Publication number: 20230352368
    Abstract: A power module is disclosed. The power module includes a first conductive plate, a first power component, and a second power component. The first conductive plate has a first side and a second side opposite to the first side; The first power component is disposed at the first side. The second power component is disposed at a first location of the second side distinct from a second location of the second side. The second location is configured to transfer most heat from the first power component to the second power component if the second power component is disposed at the second location.
    Type: Application
    Filed: April 27, 2022
    Publication date: November 2, 2023
    Applicants: Advanced Semiconductor Engineering, Inc., Universal Scientific Industrial (Shanghai) Co., Ltd.
    Inventors: Chih-Ming LIU, Yung-Fa CHEN, Hung Cheng CHANG
  • Semiconductor package structure and method of manufacturing the same
    Patent number: 11804461
    Abstract: A semiconductor package structure includes a semiconductor device with an active surface, a conductive pillar on the conductive pad, an adhesion strengthening layer, and an encapsulant in contact with the adhesion strengthening layer. The conductive pillar has a side surface and a top surface. The adhesion strengthening layer is conformally disposed on the side surface of the conductive pillar and the active surface of the semiconductor device.
    Type: Grant
    Filed: September 13, 2021
    Date of Patent: October 31, 2023
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventors: Yu-Ping Tsai, Ming-Chi Liu, Yu-Ting Lu, Kai-Chiang Hsu, Che-Ting Liu
  • SENSING PACKAGE, OPTICAL MODULE AND METHOD FOR DETECTING LIGHT
    Publication number: 20230341317
    Abstract: The present disclosure provides a sensing package. The sensing package includes a carrier configured to face an object to be inspected and an emitter disposed adjacent to the carrier. The emitter is configured to emit a first light propagating in a first direction. The sensing package further includes a component configured to change the first light into a second light propagating in a second direction different from the first direction. An optical module and a method for detecting light are also provided.
    Type: Application
    Filed: April 26, 2022
    Publication date: October 26, 2023
    Applicant: Advanced Semiconductor Engineering, Inc.
    Inventor: Wei-Hao CHANG
  • SEMICONDUCTOR DEVICE PACKAGE AND ACOUSTIC DEVICE INCLUDING THE SAME
    Publication number: 20230345165
    Abstract: A wireless earphone comprises a battery, a speaker and a chamber/space. The battery has a first surface, a second surface opposite the first surface, and a third surface extended between the first surface and the second surface. The battery is disconnected from any protecting circuits. The speaker is disposed adjacent to the first surface of the battery. The chamber/space is defined by the battery and the speaker. The chamber/space is devoid of any electronic component.
    Type: Application
    Filed: June 27, 2023
    Publication date: October 26, 2023
    Applicant: Advanced Semiconductor Engineering, Inc.
    Inventor: Ming-Tau HUANG
  • Semiconductor packages
    Patent number: 11798907
    Abstract: A semiconductor package includes a first substrate, a first flow channel and a second flow channel. The first flow channel is on the first substrate. The second flow channel is on the first substrate and in fluid communication with the first flow channel. The second flow channel is spaced from an inlet and an outlet of the first flow channel. The first flow channel and the second flow channel constitute a bonding region of the first substrate.
    Type: Grant
    Filed: November 6, 2020
    Date of Patent: October 24, 2023
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventors: Yung-Sheng Lin, Yun-Ching Hung, An-Hsuan Hsu, Chung-Hung Lai
  • Semiconductor package structure including reinforcement component and method for manufacturing the same
    Patent number: 11798858
    Abstract: A semiconductor package structure and a method of manufacturing the same are provided. The semiconductor package structure includes a first electronic component, a second electronic component, and a reinforcement component. The reinforcement component is disposed above the first electronic component and the second electronic component. The reinforcement component is configured to reduce warpage.
    Type: Grant
    Filed: July 15, 2021
    Date of Patent: October 24, 2023
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventors: Meng-Wei Hsieh, Hsiu-Chi Liu
  • Assembly structure and package structure
    Patent number: 11798890
    Abstract: An assembly structure includes a core-computing section and a sub-computing section. The core-computing section has a first surface and a second surface opposite to the first surface. The core-computing section includes at least one conductive via electrically connecting the first surface and the second surface. The sub-computing section has a first surface stacked on the first surface of the core-computing section and a second surface opposite to the first surface. The sub-computing section includes at least one conductive via electrically connecting the first surface and the second surface. The assembly structure includes a first signal transmission path and a second signal transmission path. The first signal transmission path is between the at least one conductive via of the sub-computing section and the at least one conductive via of the core-computing section.
    Type: Grant
    Filed: January 25, 2022
    Date of Patent: October 24, 2023
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventors: Cheng-Yuan Kung, Hung-Yi Lin
  • Electronic device package and method of manufacturing the same
    Patent number: 11798859
    Abstract: An electronic device package includes an encapsulated electronic component, a substrate, a conductor and a buffer layer. The encapsulated electronic component includes a redistribution layer (RDL) and an encapsulation layer. The first surface is closer to the RDL than the second surface is. The encapsulation layer includes a first surface, and a second surface opposite to the first surface. The substrate is disposed on the second surface of the encapsulation layer. The conductor is disposed between the substrate and the encapsulated electronic component, and electrically connecting the substrate to the encapsulated electronic component. The buffer layer is disposed between the substrate and the encapsulated electronic component and around the conductor.
    Type: Grant
    Filed: May 11, 2021
    Date of Patent: October 24, 2023
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventors: Chia-Pin Chen, Chia-Sheng Tien, Wan-Ting Chiu, Chi Long Tsai
  • MANUFACTURING PROCESS STEPS OF A SEMICONDUCTOR DEVICE PACKAGE
    Publication number: 20230335505
    Abstract: The present disclosure provides a semiconductor device package including a substrate having a first surface and a second surface opposite to the first surface, a first package body disposed on the first surface, and a conductive layer covering the first package body and the substrate. The conductive layer includes a first portion on the top surface of the first package body and a second portion on the lateral surface of the first package body and a sidewall of the substrate. The second portion of the conductive layer has a tapered shape. A method for manufacturing a semiconductor device package is also provided.
    Type: Application
    Filed: June 20, 2023
    Publication date: October 19, 2023
    Applicant: Advanced Semiconductor Engineering, Inc.
    Inventors: Ming-Hung CHEN, Zheng Wei WU
  • SEMICONDUCTOR DEVICE PACKAGE AND METHOD OF MANUFACTURING THE SAME
    Publication number: 20230335454
    Abstract: The present disclosure provides a semiconductor device package including a first device, a second device, and a spacer. The first device includes a substrate having a first dielectric constant. The second device includes a dielectric element, an antenna, and a reinforcing element. The dielectric element has a second dielectric constant less than the first dielectric constant. The antenna is at least partially within the dielectric element. The reinforcing element is disposed on the dielectric element, and the reinforcing element has a third dielectric constant greater than the first dielectric constant.
    Type: Application
    Filed: June 20, 2023
    Publication date: October 19, 2023
    Applicant: Advanced Semiconductor Engineering, Inc.
    Inventor: Wei-Tung CHANG
  • SEMICONDUCTOR DEVICE PACKAGE AND METHOD FOR MANUFACTURING THE SAME
    Publication number: 20230335533
    Abstract: A semiconductor device includes: a substrate having a first surface and a second surface opposite to the first surface; an electronic component disposed on the first surface of the substrate; a sensor disposed adjacent to the second surface of the substrate; an electrical contact disposed on the first surface of the substrate; and a package body exposing a portion of the electrical contact.
    Type: Application
    Filed: June 20, 2023
    Publication date: October 19, 2023
    Applicant: Advanced Semiconductor Engineering, Inc.
    Inventors: Chih-Ming HUNG, Meng-Jen WANG, Tsung-Yueh TSAI, Jen-Kai OU
  • TESTING DEVICE AND METHOD FOR TESTING A DEVICE UNDER TEST
    Publication number: 20230333139
    Abstract: A testing device is disclosed. The testing device includes a socket configured to support a DUT and a first detection module disposed at a first side of the socket and configured to detect a location relationship between the DUT and the socket.
    Type: Application
    Filed: April 15, 2022
    Publication date: October 19, 2023
    Applicants: Advanced Semiconductor Engineering, Inc., ASE TEST, INC.
    Inventors: Jia Jin LIN, Chia Hsiang WANG, Shih Pin CHUNG, Wei Shuo CHU, You Lin LEE, Pin Heng KUO, Cheng Chia TU
  • Electronic package, optoelectronic package and method of manufacturing the same
    Patent number: 11791434
    Abstract: An electronic package is provided. The electronic package includes a carrier, a first electronic component, a bonding element, and a barrier. The carrier has a conductive layer. The first electronic component is disposed adjacent to the carrier and has a first terminal and a second terminal. The bonding element is configured to electrically connect the conductive layer to the first terminal. The barrier is configured to avoid electrically bypassing an electrical path in the first electronic component and between the first terminal and the second terminal.
    Type: Grant
    Filed: November 9, 2021
    Date of Patent: October 17, 2023
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventors: Jun-Wei Chen, Yu-Yuan Yeh, Hsu-Nan Fang
  • Semiconductor device and method of manufacturing the same
    Patent number: 11791293
    Abstract: A semiconductor device and a method of manufacturing the same are provided. The semiconductor device includes an antenna zone and a routing zone. The routing zone is disposed on the antenna zone, where the antenna zone includes a first insulation layer and two or more second insulation layer and a thickness of the first insulation layer is different from that of the second insulation layer.
    Type: Grant
    Filed: September 20, 2021
    Date of Patent: October 17, 2023
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventors: Wen Hung Huang, Yan Wen Chung, Wei Chu Sun