Abstract: A hybrid matching system is disclosed for use with a transmitter and receiver. The hybrid matching system includes a pair of transmitter output nodes, a pair of receiver input nodes, and a pair of terminals for interfacing to a transmission line. The system further includes a first impedance bridge portion including at least one inductor for coupling to the transmission line terminals via at least one transformer winding, and a second impedance bridge portion interposed between the pair of transmitter output nodes and the first impedance bridge portion, and interposed between the pair of receiver input nodes and the first impedance bridge portion.

Abstract: A micromachined device has a body suspended over a substrate and movable in a plane relative to the substrate. The body has a perimeter portion, a first cross-piece portion extending from one part of the perimeter portion to another part of the perimeter portion to define at least first and second apertures, a first plurality of fingers extending along parallel axes from the perimeter portion into the first aperture, and a second plurality of fingers extending along parallel axes from the perimeter portion into the second aperture.

Abstract: A variable modulus interpolator (1) for interpolating a fractional part F M of a rational number by which a reference frequency is to be divided in a multi-divisor divider in a variable frequency synthesizer comprises a third order sigma-delta modulator (3) of MASH cascade configuration having first, second and third sigma-delta stages (5,6,7). The numerator F of the fraction is selectable and is inputted to a first register (10) for inputting to the input of the first sigma-delta stage (5) of the sigma-delta modulator (3). The denominator M of the fraction is selectable and is inputted to a second register 11. A single bit output quantiser (16) in each sigma-delta stage (5,6,7) outputs a sign bit indicative of the sign of the output from an integrator (15) in the corresponding sigma-delta stage (5,6,7).

Abstract: Methods of making microelectromechanical combdrive devices are disclosed. The device may optionally be formed using three device layers. A moveable element and flexure may be formed from a first device layer. The second device layer may be attached to the first and a first set of comb teeth are formed from the second device layer. One or more comb teeth in the first set extend from a major surface of the moveable element. A third device layer is attached to the second device layer and a second set of comb teeth are formed from the third device layer. An alignment target is formed in the first device layer. Corresponding alignment holes are formed in the second or third device layers.

Abstract: A receiver circuit is disclosed for use in a communication system. The receiver circuit includes a forward path with a channel selection filter and a feedback path. The output of the channel selection filter is provided to an output device. The feedback path includes a feedback filter and a mixer. The input of the feedback filter is coupled to the output of the channel selection filter and the output of the feedback filter is coupled to a first input of the mixer. The second input of the mixer is coupled to a multi-frequency signal generator, and the output of the mixer is coupled to the forward path of the receiver circuit.

Abstract: A multi-channel analog to digital converter which facilitates calibration of the analog to digital converter and respective input channels to the analog to digital converter, and a method for calibrating the analog to digital converter. A multi-channel ADC (1) comprising an ADC circuit (2) for converting analog signals received on input channels CH1 to CHN to digital output signals comprises a primary offset storing register (24) and a primary gain storing register (25) for storing respective primary offset and gain correction codes which are applied to the digital output signals in a primary correcting circuit (14) for correcting for the offset and gain errors introduced by the ADC circuit (2).

Abstract: A sigma delta modulator includes a modulator module that includes a quantizer with variable hysteresis, which receives an input signal to perform necessary modulation operations. A non-linear mapping module receives a signal associated with said input signal and tabulates the necessary hysteresis control information so as to reduce the transition rate of the modulator module.

Abstract: A multi-channel circuit (1) comprising a plurality of on-chip channels (CH1 to CH4), each of which comprises a DAC (3) for converting digital data into analogue output signals independently of each other under the control of an interface and control logic circuit (11). The analogue output signals from the DACs (3) are outputted on output terminals (7) of the respective channels (CH1 to CH4). The digital input data and control and address signals for controlling the conversion of the digital data in the DACs (3) are inputted to the interface and control logic circuit (11) through an I/O port (10). DAC registers (9) are provided in the respective channels (CH1 to CH4) for storing the digital words to be converted in the corresponding DACs (3). Analogue input terminals (20) are provided for receiving analogue input signals (20), for example, analogue signals from external systems which may be controlled by the output signals from the DACs (3).

Abstract: A transceiver system is disclosed for use in a telecommunication system. The transceiver system includes a transmission circuit including a transmitter input coupled to an input of a transmission amplifier, a receiver circuit including a receiver output coupled to an output of a receiver amplifier, and a transmission line interface circuit that is coupled to an output of the transmission amplifier and to an input of the receiver amplifier. The transmission line interface circuit includes a matching impedance that is directly coupled to a feedback path of the transmission amplifier and that terminates the transmission line of the transceiver system.

Abstract: A logic isolation circuit has a transmitter circuit for receiving a logic input signal and providing a periodic signal to an isolation barrier, and a receiving circuit for receiving the periodic signal from the isolation barrier and for providing an output signal that indicates the transitions in the logical input signal.

Abstract: Driver circuitry is described. The circuitry is specifically adapted for use in transmission line environments and provides an offset and swing voltage at an output thereof. The voltages provided at the output are both provided by a current source provided within the driver circuit and coupled to a differential pair current switch.

Abstract: Register adjustment is performed based on adjustment values determined at multiple stages within a pipeline of a processor. In one embodiment, a programmable processor is adapted to include a speculative count register. The speculative count register may be loaded with data associated with an instruction before the instruction commits. However, if the instruction is terminated before it commits, the speculative count register may be adjusted. A set of counters may monitor the difference between the speculative count register and its architectural counterpart.

Abstract: A driver circuit for driving a line in a network comprises first driving means for driving the line, second driving means for driving the line, and switching means for switching between the first and second driving means. A method for providing multi-mode driver capability is also described. The method comprises the steps of providing a line driver circuit including both a current source and a voltage source, selecting a first or second mode of operation, operating the line driver circuit in a first configuration when the first mode of operation is selected, and operating the line driver circuit in a second configuration when the second mode of operation is selected.

Abstract: A programmable processor is adapted to detect exception conditions associated with one or more instructions before the instructions are executed. The detected exception conditions may be stored with the one or more instructions in a prefetch unit. Then, the exception conditions may be issued in parallel with the issuance of the instructions.

Abstract: The invention provides a bandgap voltage reference circuit that is adapted to provide a ?Vbe of sufficiently large value that no amplification is required, and therefore any offset contribution is not gained. Using a stacked arrangement of three pairs of transistors, the invention reduces the requirement for multiple resistors within a circuit and can therefore minimise errors due to resistor matching and value. Internally provided circuitry for reducing voltage curvature is provided with the result that a circuit having low offset sensitivity and curvature correction is provided.

Abstract: A programmable input voltage range analog-to-digital converter in which a split gate oxide process allows the use of high voltage (±15 volt) switches on the same silicon substrate as standard sub-micron 5 volt CMOS devices. With this process, the analog input voltage can be sampled directly onto one or more sampling capacitors without the need for prior attenuation circuits. By only sampling on a given ratio of the sampling capacitors, the analog input can be scaled or attenuated to suit the dynamic range of a subsequent ADC. In the system of the present invention, the sampling capacitor can be the actual capacitive redistribution digital-to-analog converter (CapDAC) used in a SAR ADC itself, or a separate capacitor array. By selecting which bits of the CapDAC or separate sampling array to sample on, one can program the input range.

Abstract: A real-valued FFT processor implements Bergland's real-valued FFT and uses unique interstage switching/delay modules to reduce pipeline latency. Modified hybrid floating point arithmetic is also employed to provide maximum SNR. The real-valued FFT processor is particularly suited for a DMT engine and, in a multichannel CO ADSL application, the DMT engine can be multiplexed between the channels to provide an economic, low cost CO solution.

Abstract: Systems and methods receive a digital signal and generate an analog signal indicative thereof. In one embodiment, a system includes a DAC that receives a multi-bit digital signal, generates at least two analog signals each indicative of the value of the multi-bit digital signal, and filters two or more of the at least two analog signals. In another embodiment, a system includes a DAC that receives digital input signals at an input data rate and outputs analog signals indicative of the digital signals to a signal conditioning stage at an output data rate different than the input data rate.

Abstract: A digital data processor having a main pipeline to which a side pipe is loosely coupled. In particular, the side pipe is coupled to the main pipeline at a point after which an instruction entering the side pipe cannot cause an exception. When such an instruction enters the first stage of the side pipe, a copy or “ghost” of this instruction is created. While the actual instruction flows down the side pipe, this ghost instruction is allowed to flow independently down the main pipeline as if it were a non-squashable no-op. When the ghost reaches the retirement stage of the main pipeline, it is retired in normal program order, regardless of the status of the actual instruction. However, in addition, each system resource that is still waiting for a result from the actual instruction is marked appropriately. When the actual instruction finally completes in the side pipe, the only consequence, other than those local to the side pipe itself, is that any results are forwarded to the awaiting resources.

Abstract: Methods and apparatus are provided for encoding data.