Abstract: A multimode voltage regulator includes a low current pass device and a high current pass device each adapted for connection between a power supply and a load; an error amplifier responsive to a difference between a reference voltage and a function of the voltage on the load to produce an error signal; and a low power driver responsive in a low load power mode to an error signal for operating the low current pass device to provide low power to the load and a high power driver responsive in a high load power mode to an error signal for operating the high current pass device to provide high power to the load for maintaining efficiency over high and low power load operation.

Abstract: In an embodiment, a pipelined processor includes a future file for storing updated data address values generated by a data address generator (DAG). These updated values may be provided to the DAG for subsequent address calculation operations.

Abstract: A charge pump system for a fast locking phase lock loop includes a set n of charge pump units; and a control logic circuit for enabling the set of n charge pump units to produce up and down charge pulses with a nominal charge pump mismatch in a wide bandwidth mode; and in a narrow bandwidth mode enabling at least a subset of the n charge pump units sequentially to produce an average charge pump mismatch in narrow bandwidth mode that matches the nominal charge pump mismatch in the wide bandwidth mode.

Abstract: A multiple bus architecture includes multiple processors, and one or more shared peripherals such as memory. The architecture includes plural bus masters, each connected to its own bus. There are also plural bus slaves, each connected to its own bus. A bus arbitration module selectively interconnects the buses, so that when the plural bus masters each access a different bus slave, no blocking occurs, and when the plural bus masers each access a same bus slave, bandwidth starvation is avoided. The architecture is supported by a bus arbitration method including hierarchical application of an interrupt-based method, an assigned slot rotation method and a round-robin method, which avoids both bandwidth starvation and lockout during extended periods of bus contention.

Abstract: Methods and apparatus are provided for supplying data to a processor in a digital processing system. The method includes holding data required by the processor in a cache memory, supplying data from the cache memory to the processor in response to processor requests, performing a cache line fill operation in response to a chache miss, supplying data from a prefetch buffer to the cache memory in response to the cache line fill operation, and speculatively loading data from a lower level memory to the prefetch buffer in response to the cache line fill operation.

Abstract: A brown-out detector that continuously monitors power supply voltage and provides an output signal that transitions to a logic HIGH state when the monitored power supply voltage exceeds a predetermined threshold value. One embodiment of the present invention comprises a first voltage reference with respect to ground that varies in direct proportion to absolute temperature, a second voltage reference with respect to the supply voltage that varies inversely with absolute temperature, and a comparator having the first voltage reference coupled to one input, and the second voltage reference coupled to the other input, such that the comparator output changes state when the power supply voltage exceeds a predetermined threshold voltage that is relatively independent of absolute temperature. The circuit may also be configured such that the first voltage reference varies inversely with absolute temperature, while the second voltage reference varies in direct proportion to absolute temperature.

Abstract: Accelerometer offset is reduced by forming mass support structures within an inner periphery of the mass, affixing the mass support structures to the substrate by at least one anchor positioned near the mass' center of mass, and affixing the sensing fingers proximate to the anchor. The mass support structures can be affixed to the substrate using a single anchor or multiple anchors that are positioned close together. The sensing fingers can be affixed to the substrate or to the mass support structures. The mass is typically suspended from within its periphery but toward its outer periphery.

Abstract: A translinear amplifier is disclosed. A loop amplifier drives the bases of the input and output transistor pairs from the differential collector voltage of the input pair. The loop amplifier contains a third differential pair (a gain pair). The tail current of the gain pair is inversely related to the tail current of the input pair, such that loop amplifier gain remains stable when the transconductance of the input pair changes (due, e.g., to input gain changes). In one embodiment, a linear-in-dB interface is provided that adjusts input pair tail current exponentially (and gain pair tail current exponentially and inversely) to linear voltage changes at a gain input.

Abstract: An pipeline analog-to-digital converter (ADC) is provided that is capable of applying calibration at a resolution greater than the resolution of a digital output signal provided by the ADC. The ADC includes a calibration component adapted to apply calibration bits to digital output bits generated by stages of the pipeline and corresponding to samples of an analog input signal. The ADC also includes a random number generator that provides at least one random bit having a sub-LSB bit weight. The calibration bits and the at least one random bit are applied as a dither to the digital output bits such that, on average, the digital output signal provided by the ADC is calibrated at a sub-LSB resolution.

Abstract: A method of producing a shadow mask having a set of apertures (the set of apertures including a given aperture with an aperture boundary) uses a wafer having at least a first silicon layer, a second silicon layer, and an insulator layer between the first and second silicon layers. A first portion of the first silicon layer within the aperture boundary is removed. This produces a second portion of the first silicon layer, which remains within the aperture boundary. The second silicon layer within the aperture boundary is removed, as well as the insulator layer within the aperture boundary. The second portion of the first silicon layer remaining within the aperture boundary then is removed.

Abstract: An apparatus having magnetic detection sensor deployed on a micro machined optical element is exposed to a magnetic field to sense change in property as the micro machined optical element is manipulated with respect to the magnetic field, and, conversely when the magnetic field is manipulated with respect to the micro machined optical element. The electrical, optical and/or mechanical change in sensor property varies according to said manipulation, and telemetry created by said property change tracks the manipulation of the moveable portion of the optical element. The system includes a configuration capable of compensating for temperature variation.

Abstract: A voltage reference circuit is provided which includes PTAT and CTAT generating components. The CTAT components are provided in a feedback configuration about an operational amplifier and are combined with PTAT generating components which are coupled to the inputs of the amplifier. The combination of the CTAT and PTAT components is effected in a manner which provides for a temperature curvature correction of the output voltage of the circuit.

Abstract: An RC equivalent filter is provided in which the resistor is replaced by a voltage source (40) and a capacative divider. With suitable control the voltage occurring across a capacitor (44) in the divider can reproduce that which would occur across at the output of the original RC filter, but with much lower noise.

Abstract: An input signal is a complex vector whose phase is a coherent measurement of the phase rotation occurring between two separated symbols of a received CDMA signal. A processing block (30) provides a first signal showing the magnitude and the sign of the imaginary part of the input signal, and a second signal showing the magnitude and sign of the real part of the input signal to an initialisation block (31). A quadrant determination block (32) examines the signs of the signals to determine the quadrant in which the phase of the input signal exists. A comparator block (33) determines if the magnitude of the first signal is greater than or equal to the magnitude of the second signal. If a negative determination is made, the magnitude of the first signal is doubled in a multiplication block (35) to form a multiplied signal, and a counter incremented, initially from zero. The comparator block (33) then determines if the multiplied signal is greater than or equal to the magnitude of the second signal.

Abstract: In an embodiment, a pipelined processor may be adapted to process multi-cycle instructions (MCIs). Results generated in response to non-terminal sub-instructions may be written to a speculative commit register. When the MCI commits, i.e., a terminal sub-instruction reaches the WB stage, the value in the speculative commit register may be written to the architectural register.

Abstract: MEMS structures may be formed on a substrate by forming a series trenches filled with etch-stop material in the device layer, followed by an isotropic etch of the device material stopping on the etch-stop material. This approach provides a controlled release method where the exact timing of the isotropic release etch becomes non-critical. Further, using this method, structures with significant topology may be fabricated while keeping the wafer topology to a minimum during processing until the very end of the process. Using the method of this invention, features with large topology may be formed while keeping the wafer topology to a minimum until the very end of the process.

Abstract: A dynamic power controller is provided that identifies a clock frequency requirement of a processor and determines a voltage requirement to support the clock frequency requirement. The dynamic power controller transitions the processor to a power state defined by the clock frequency requirement and the voltage requirement. In particular, a voltage level indicated by the voltage requirement is supplied to the processor and the frequency distribution indicated by the frequency requirement is provided to the clocks signals of the processor.

Abstract: A microelectromechanical (MEMS) apparatus has a base and a flap with a portion coupled to the base so that the flap may move out of the plane of the base between first and second position. The base may have a cavity with largely vertical sidewalls that contact a portion of the flap when the flap is in the second position Electrodes may be placed on the vertical sidewalls and electrically isolated from the base to provide electrostatic clamping of the flap to the sidewall. The base may be made from a substrate portion of a silicon-on-insulator (SOI) wafer and the flap defined from a device layer of the SOI wafer. The flap may be connected to the base by one or more flexures such as torsional beams. An array of one or more of such structures may be used to form an optical switch.

Abstract: A bond pad structure for an integrated circuit includes first and second active devices formed in a substrate, first and second buses above the first and second active devices, respectively, a bond pad above the first and second buses, first interconnections between the first and second active devices and the bond pad, and second interconnections between the first and second active devices and the first and second buses, respectively. The first active device may be at least one PMOS transistor, and the second active device may be at least one NMOS transistor. A guard band region may be formed in the substrate.

Abstract: A voltage bandgap reference voltage circuit is provided. The circuit includes an amplifier having a first and second transistor coupled to the inputs of the amplifier. The circuit is adapted to operate with lower headroom by effecting a subtraction of a voltage substantially equivalent to Delta Vbe of the first and second transistors from the voltage applied to the common input of the amplifier.