Abstract: A multiple-stage digitally-switched impedance has one “type B” stage and at least two “type A” stages. The type A stages are cascaded between high and low reference nodes and the type B stage. Each stage comprises a string of series-connected impedances and a switch network. A decoder responds to an digital input signal by controlling the switch networks to switch selectable portions of the strings in the type A stages into a series connection with the type B stage's string, and to control the type B stage's switch network to tap its string at a location to provide a impedance corresponding to the n-bit digital input signal between the final output node and at least one of the high and low reference nodes. Each stage provides a portion of the impedance's n-bit resolution, and the sum of the bits of resolution provided by each stage equals the total n-bit resolution.

Abstract: A signal generator (1) for generating a square waveform analog voltage output signal comprises an on-chip DAC (12) which outputs the analog voltage signal on an output terminal (5). On-chip first and second programmable registers (9,10) store first and second digital words which correspond to the maximum and minimum voltage values of the analog output signal. An on-chip switch circuit (15) selectively and alternately switches the first and second registers (9,10) to an on-chip DAC register (17) from which the respective first and second digital words are loaded into the DAC (12) in response to a load DAC signal generated by a control circuit (14). The load DAC signal is generated in response to an externally generated LDAC signal in the form of a clock signal which is applied to an LDAC terminal (22). A flip-flop (19) in response to the load DAC signal outputs a control signal on a control line (25) for alternately switching the first and second registers (9,10) to the DAC register (17).

Abstract: A retention device stabilizes the logic output levels of a dynamic logic stage. The dynamic logic stage contains an inverter, which generates an inverted logic signal that is used as a feedback signal into the retention device. The retention device contains a switching element consisting of two active elements connected in series. The retention device has two inputs, a control input for receiving a delayed clock signal, and a feedback input for receiving the inverted logic signal generated by the inverter. The feedback and delayed clock signals switch the switching element between two retention states, where each retention state stabilizes a respective logic output level.

Abstract: A pipelined analog to digital converter. Each stage in the pipeline has a flash converter and a multiplying digital to analog converter. Each stage provides a digital bits and an analog residue that is passed to the next stage in the pipeline. The digital bits from all stages are combined in digital logic to produce the digital output of the converter. The flash converter in each stage has a set of comparators, each coupled to a reference ladder. A random number generator in connection with a switch matrix “shuffles” the reference inputs to the comparators. The comparators are latched as soon as practical after they are stable and the reference inputs are shuffled as soon as practical after the comparators are latched. Also, a bandwidth trim circuit is provided to compensate for different cutoff frequencies of the input impedances of the flash and multiplying digital to analog converters.

Abstract: A direct conversion receiver apparatus includes a local oscillator to produce a first local oscillation signal and a second oscillation signal. A first modulation circuit modulates the first local oscillation signal, and a second modulation circuit modulates the second local oscillation signal. A RF mixer mixes a received radio frequency signal with the modulated first local oscillation signal, and another RF mixer mixes the received radio frequency signal with the modulated second local oscillation signal. Demodulating circuits translate desired signals of the mixed signal from the RF mixers into band and translate undesired signals of the mixed signal out of band. Filters remove the undesired signals from the demodulated signals.

Abstract: A selectable-gain amplifier selectively couples different capacitors and feedback networks to a gain stage to provide operating characteristics that may include constant bandwidth operation. An interpolated VGA includes pairs of gm cells with cross-connected outputs and may include output cascodes. A dual-rank interpolator utilizes a correction current with a second-order temperature characteristic which may compensate for temperature effects in the transistor ranks.

Abstract: A metallization stack is provided for use as a contact structure in an integrated MEMS device. The metallization stack includes a titanium-tungsten adhesion and barrier layer formed with a platinum layer formed on top. The platinum feature is formed by sputter etching the platinum in argon, followed by a wet etch in aqua regia using an oxide hardmask. Alternatively, the titanium-tungsten and platinum layers are deposited sequentially and patterned by a single plasma etch process with a photoresist mask.

Abstract: A micromachined gyroscope makes use of Coriolis acceleration to detect and measure rotation rate about a plane normal to the surface of a substrate. Specifically, various resonating structures are suspended within a frame. The resonating structures include phase and anti-phase masses that are mechanically coupled in order to produce a single resonance frequency for the entire resonating system. Rotation of the micromachined gyroscope about the plane produces a rotational force on the frame. The frame is suspended in such a way that its motion is severely restricted in all but the rotational direction. Sensors on all sides of the frame detect the rotational deflection of the frame for measuring the change in direction.

Abstract: An analog-to-digital metering circuit includes a first programmable gain amplifier to amplify a first voltage signal from a first channel before being received by a first analog-to-digital converter that converts the amplified first voltage signal to a first digital signal. A second programmable gain amplifier amplifies a second voltage signal from a second channel and feds the amplified signal to a second analog-to-digital converter that converts the amplified second voltage signal to a second digital signal. A first lowpass filter circuit receives the first and second digital signals, to generate therefrom, a multi-bit analog-to-digital value. A direct digital synthesizer generates a digital signal representing a predetermined waveform that is fed to a digital-to-analog converter. The second voltage signal and the digital signal representing the predetermined waveform are multiplied together to generate a digital value.

Abstract: An inductor current emulation circuit for a switched-mode power supply (SMPS) which is arranged such that its inductor current (IL) goes to zero at least once per switching cycle. The emulation circuit includes an RC integrator connected in parallel across the inductor, and a zero reset switch (ZRS) connected in parallel across the integrator's capacitor. A control circuit operates the ZRS such that it is opened when IL is non-zero, and is closed for a least a portion of the time during each switching cycle when IL is zero such that the capacitor is substantially discharged. In this way, the ZRS essentially recalibrates the emulation circuit when IL is zero. When so arranged, the voltage (VC) across the capacitor emulates IL. The invention may be implemented with either a discontinuous-inductor-current SMPS, or a continuous-bipolar-inductor-current SMPS.

Abstract: A repatterned integrated circuit chip package which balances and/or reduces the package capacitance associated with the gain resistor terminals to reduce the degradation of common mode rejection with frequency.

Abstract: Systems and methods receive a digital signal and generate an analog signal indicative thereof. In one embodiment, a system includes a DAC that receives a multi-bit digital signal, generates at least two analog signals each indicative of the value of the multi-bit digital signal, and filters two or more of the at least two analog signals. In another embodiment, a system includes a DAC that receives digital input signals at an input data rate and outputs analog signals Indicative of the digital signals to a signal conditioning stage at an output data rate different the input data mute.

Abstract: A non-optical isolator having a driver circuit for providing an input signal to one or more first passive components which are coupled across a galvanic isolation barrier to one or more corresponding second passive components, and an output circuit that converts the signal from the second passive components to an output signal corresponding to the input signal. The entire structure may be formed monolithically as an integrated circuit on one or two die substrates, for low cost, small size, and low power consumption. The passive components may be coils or capacitor plates, for example. When the first and second passive components are capacitor plates, a Faraday shield may be provided between them, with the first and second passive components being referenced to separate grounds and the Faraday shield referenced to the same ground as the second passive components.

Abstract: An optical microelectromechanical system (MEMS) device and a method for making it are disclosed. The device generally includes a substrate with two or more device dies attached to the substrate. Each device die includes one or more MEMS optical elements. A common clamping die is attached to the device dies such that each MEMS optical element aligns with a corresponding clamping surface on the common clamping die. The single larger clamping die, which covers all the elements on the smaller device dies, forces mirrors contained thereon to register accurately, in the “ON” state. Such a device may be made by attaching two or more device dies to a substrate, and attaching a common clamping die to the two or more device dies. The device dies may be attached to the substrate before attaching the common clamping die to the device dies. Alternatively, the common clamping die may be attached to the device dies before the device dies are attached to the substrate.

Abstract: A position-sense interface with improved transfer characteristics. Electrical position detection circuitry, which may be substantially time-multiplexed or frequency-multiplexed, comprises a differential charge integrator with input-sensed output-driven common mode feedback. By placing sense capacitors in the feedback loop of said differential charge integrator with input-sensed output-driven common mode feedback, improved position sensing linearity is attained. In some embodiments of the invention, a compensating charge is applied to the sense capacitors in a fashion that minimizes the output common mode shift of the opamp. The magnitude of the compensating charge may be preset at a substantially constant level, or derived by a feedback loop that measures the shift in output common mode voltage in response to an excitation signal and adjusts the magnitude of the compensating charge to drive said shift towards zero.

Abstract: A logic signal isolator comprising a transformer having a primary winding and a secondary winding; a transmitter circuit which drives said primary winding in response to a received logic signal, such that in response to a first type of edge in the logic signal, a signal of a first predetermined type is supplied to the primary winding and in response to a second type of edge in the logic signal, a signal of a second predetermined type is supplied to said primary winding, the primary winding and the transmitter being referenced to a first ground; and the secondary winding being referenced to a second ground which is galvanically isolated from the first ground and said secondary winding supplying to a receiver circuit signals received in correspondence to the signals provided to the primary winding, the receiver reconstructing the received logic signal from the received signals.

Abstract: A single chip integrated circuit measuring circuit (1) for determining a characteristic of the impedance of an external complex impedance circuit (2) for facilitating characterization of the impedance of the complex impedance circuit (2) comprises a signal generating circuit (7) for generating a variable frequency stimulus signal for applying to the complex impedance circuit (2). A first receiving circuit (10) receives a response signal from the complex impedance circuit (2) in response to the stimulus signal and conditions the response signal. A first analog-to-digital converter (68) converts the conditioned response signal to a first digital output signal, which is read from the first analog-to-digital converter (68) through a first digital output port (14). The response signal from the complex impedance circuit (2) is a current signal, and a current to voltage converter circuit (64) converts the response signal to a voltage signal.

Abstract: A reconfigurable single instruction multiple data array includes a plurality of processing cells; a serial data bus with at least one line dedicated to each cell; each cell including an identification number for uniquely identifying each cell and its dedicated line and a communication port including at least one parallel to serial transmitter circuit in each cell for broadcasting its cell's output data over its dedicated line; at least one serial to parallel receiver circuit in each cell; each cell responsive to the identification number and a common command word to generate a local configuration command designating a pre-selected broadcasting cell and a configuration register associated with each receiver circuit and responsive to the local configuration command to condition its receiver's circuit to receive serial input data broadcast from the pre-selected cell's dedicated line.

Abstract: A filter system with reduced switch thermal noise includes an input circuit for receiving an input signal and a feedback signal and providing a signal representative of the difference; a filter circuit including at least an input sampling capacitor and switch which introduce thermal noise error; a feedback circuit responsive to the filter circuit for delivering to the input circuit the feedback signal; the input circuit also amplifying the difference signal before it is submitted to the filter circuit to reduce the input-referred thermal noise by a factor of approximately the gain of the amplification; and a ?? modulator using such a filter.

Abstract: One embodiment of the invention is directed to a method of extending the input range of an analog-to-digital converter (ADC) having a nominal input voltage range. The method comprises an act of mapping an over-range input voltage that falls outside of the nominal input voltage range to an over-range digital output code. Another embodiment of the invention is directed to an apparatus comprising an ADC having a nominal input voltage range, wherein the ADC is adapted to map an over-range input voltage that falls outside of the nominal input voltage range to an over-range digital output code.