Abstract: The present disclosure provides a forming method of a memory and a memory. The method includes: providing a substrate, wherein the substrate includes at least word line structures and active areas, and a bottom dielectric layer and a bit line contact layer located on a top surface of the substrate, the bottom dielectric layer has bit line contact openings, the bit line contact openings expose the active areas in the substrate, and the bit line contact layer covers the bottom dielectric layer and fills the bit line contact openings; etching parts of the bit line contact layer, and forming first bit line contact layer with different heights; forming a conductive layer, a top surface of the conductive layer is located at different heights in a direction perpendicular to an extension direction of the word line structures.

Abstract: Embodiments of this application provide a semiconductor structure and a method for forming the same. The method for forming the semiconductor structure includes: a first substrate is provided; the back surface of the first substrate is etched to form a trench; a conductive layer is formed in the trench; a first conductive column that extends into the trench is formed at a back surface of the first substrate; a device layer is formed at a front surface of the first substrate, and the device layer includes a storage array and a contact structure; and a second conductive column that penetrates through the device layer and extends into the first substrate is formed; the first conductive column is electrically connected with the second conductive column through the conductive layer.

Abstract: Provided are a heat dissipation structure, a method for forming a heat dissipation structure, and a semiconductor structure. The heat dissipation structure includes a first heat dissipation ring and a second heat dissipation ring. The first heat dissipation ring is formed in a dielectric layer around a Through Silicon Via (TSV) and in contact with the TSV. The TSV passes through a silicon substrate and the dielectric layer. The second heat dissipation ring is formed around the first heat dissipation ring, and in contact with the first heat dissipation ring. The second heat dissipation ring has a heat dissipation gap within it. A dimension of the second heat dissipation ring in a first direction is less than that of the first heat dissipation ring in the first direction. The first direction is a thickness direction of the silicon substrate.

Abstract: A refresh control circuit includes the following: an address output circuit configured to output a to-be-refreshed address signal including a block address signal and a row address signal; a block decoding circuit configured to: receive the block address signal; decode the block address signal and output a first block selection signal for selecting multiple data blocks from the memory array, in response to that the memory array is subjected to no row hammer attack, or decode the block address signal and output a second block selection signal for selecting one data block from the memory array, in response to that the memory array is subjected to a row hammer attack; and a row decoding circuit, configured to receive the row address signal, decode the row address signal and output a row selection signal.

Abstract: The present disclosure provides a latch-up test structure, including: a substrate of a first conductive type; a first well region of the first conductive type, located in the substrate of the first conductive type; a first doped region of the first conductive type, located in the first well region of the first conductive type; a first doped region of a second conductive type, located in the first well region of the first conductive type; and a second doped region of the first conductive type, a second doped region of the second conductive type, a third doped region of the first conductive type, and a third doped region of the second conductive type that are arranged at intervals in the substrate of the first conductive type.

Abstract: A comparison circuit includes a comparison module, a state judgment module and a state storage module. The comparison module includes a first input end connected to a voltage to be measured and a second input end connected to a reference voltage. The state judgment module includes a first input end connected to a first output end of the comparison module and a second input end connected to a second output end of the comparison module. The state storage module includes an input end connected to the first output end of the comparison module and an enable end connected to an output end of the state judgment module. The embodiments of the disclosure may improve processing efficiency of the comparison circuit.

Abstract: The method includes: providing a substrate, the substrate including a first region and a second region; forming an insulating layer on the substrate; etching a portion of the insulating layer in the second region, the insulating layer in the first region being configured as a first insulating layer, a remaining portion of the insulating layer in the second region being configured as a second insulating layer; forming a first barrier layer covering the first insulating layer and a second barrier layer covering the second insulating layer; etching the first barrier layer, a portion of the second barrier layer and the first insulating layer to form a through hole in the first insulating layer, and to form a hole segment in the second barrier layer; and removing the first barrier layer and the second barrier layer.

Abstract: A chip bonding method includes the following operations. A first chip is provided, which includes a first contact pad including a first portion lower than a first surface of a first substrate and a second portion higher than the first surface of the first substrate to form the stepped first contact pad. A second chip is provided, which includes a second contact pad including a third portion lower than a third surface of a second substrate and a fourth portion higher than the third surface of the second substrate to form the stepped second contact pad. The first chip and the second chip are bonded. The first portion of the first chip contacts with the fourth portion of the second chip, and the second portion of the first chip contacts with the third portion of the second chip.

Abstract: A semiconductor structure includes: a base; a conductive column, which is at least located in the base; an electric connection layer, which is connected to an end part of the conductive column. The end part, towards the electric connection layer, of the conductive column has a first protruding part and at least one groove defined by the first protruding part, the electric connection layer has a second protruding part at a position corresponding to the groove, and the second protruding part is embedded in the groove.

Abstract: A memory includes: bit lines extending along a first direction and word lines extending along a second direction; a plurality of memory modules arranged along the first direction; a column selection circuit and a read-write control driver circuit, wherein the column selection circuit and the read-write control driver circuit are located on a same side of the plurality of memory modules perpendicular to the first direction; column-select lines extending along the first direction and column connection lines extending along a third direction, wherein each of the column-select lines is electrically connected to an amplification unit arranged along the first direction and is electrically connected to the column selection circuit through the column connection line, and the column selection circuit is configured to drive the amplification unit electrically connected to the column-select line.

Abstract: A data processing circuit includes a primary transmission path, multiple secondary transmission paths and multiple storage arrays which share the primary transmission path. Each storage array includes at least two sub-arrays, and the secondary transmission path is formed between each sub-array and the primary transmission path, and the sub-array transmits a signal through the secondary transmission path and the primary transmission path.

Abstract: The present disclosure provides a method for forming a semiconductor structure, which includes: forming first trench structures and second trench structures in a substrate, wherein each of the first trench structures is located between two active regions arranged along a first direction, each of the second trench structures is located between two adjacent active regions arranged along a second direction, and the first trench structures are in communication with the second trench structures; forming first isolation structures and second isolation structures; and forming word lines.

Abstract: A semiconductor structure includes a substrate, a storage capacitor unit, a transistor, and an electrical connection structure. The storage capacitor unit is located at an array area and includes: N insulation posts, distributed in a direction parallel to a surface of the substrate; a bottom electrode layer; a top electrode layer, directly facing the bottom electrode layer; and a capacitor dielectric layer, located between the top and bottom electrode layers. One of the bottom or top electrode layers corresponding to the N insulation posts is a continuous film layer, and the other is discrete film layers. The transistor is located at a circuit area and includes a capacitor control terminal located in the substrate of the circuit area. The electrical connection structure is electrically connected to the capacitor control terminal, and extends from the circuit area to the array area to come into contact with a corresponding discrete film layer.

Abstract: A semiconductor structure includes a base and conductive channel structure which includes first and second conductive channel layers and conductive buffer layer. The first conductive channel layer includes a first conductive channel, first and second doped regions on both sides of the first conductive channel; the second conductive channel layer includes a second conductive channel and third and fourth doped regions on both sides of the second conductive channel; the conductive buffer layer reduces electrical interference between the first and third doped regions. The semiconductor structure further includes a first wire layer disposed on the base extending in a direction and in contact with the second doped region; a second wire layer extending in another direction and in contact with the first and third doped regions; and a gate structure disposed around the first and second conductive channels.

Abstract: An embodiment of the present application relates to the technical field of semiconductors, and discloses a method for manufacturing a semiconductor structure. In this embodiment, the method comprises: providing an insulating substrate (101); depositing an isolation layer (103) on the insulating substrate (101) by a physical vapor deposition process, the isolation layer (103) comprising cobalt atoms and barrier atoms located at grain boundaries of the cobalt atoms; and depositing a copper-containing metal layer (104) on the isolation layer (103).

Abstract: A sub route flow is a route flow different from a main route flow in testing of a semiconductor product. A method for configuring a sub route flow includes: determining at least one test item of the semiconductor product; obtaining a first test template corresponding to the test item, wherein the first test template includes preset test parameters; displaying the preset test parameters; receiving test parameters adjusted according to the preset test parameters; configuring current test parameters of the test item according to the adjusted test parameters; and forming the sub route flow of the semiconductor product according to the current test parameters of the test item.

Abstract: A refresh circuit includes a refresh counter configured to output address signals through a plurality of address pins; an address mixer configured to output row address selection signals according to the address signals received by the row address pins, output first bank address signals according to the address signals received by bank address pins, receive a refresh signal and a power supply voltage signal, and output fixed second bank address signals according to the refresh signal and the power supply voltage signal; and an address pre-decoding circuit configured to output a preset number of bank address selection signals according to the first bank address signals and the second bank address signals.

Abstract: A semiconductor device with a buried bit line and a preparation method thereof are provided. The preparation method of a semiconductor device with a buried bit line includes: providing a substrate; forming bit line trenches; forming a bit line structure in the bit line trench; and forming word line structures in the substrate. The semiconductor device with a buried bit line includes a substrate, bit line trenches, a bit line structure, and word line structures.

Abstract: The present application provides a floating pin, a wafer carrying device and a depositing apparatus, which relates to the technical field of semiconductor apparatus, and is used for solving the technical problem of low yield of a workpiece to be processed. The floating pin includes a pin body and a pin head connected to one end of the pin body, wherein the pin head protrudes in relation to a side surface of the pin body, and a side surface of a protruding part of the pin head is a curved surface. By reducing the distance between the pin head and the workpiece to be processed, the impact force on the workpiece to be processed when the pin head collides with the workpiece to be processed can be reduced, damages to the workpiece to be processed can be reduced, and the yield of the workpiece to be processed can be improved.

Abstract: A method for preparing a semiconductor structure includes: providing a substrate which includes a device region and a shallow trench isolation region surrounding the device region, in which the device region is exposed from a surface of the substrate; depositing a barrier layer on the substrate, the barrier layer at least covering the device region; forming an initial oxide which is located in the device region and in contact with the barrier layer; and removing part of the initial oxide to form a device oxide.