Abstract: Embodiments of the present disclosure provide a circuit for receiving data, a system for receiving data, and a memory device. The circuit for receiving data includes: a first amplification module, including: an amplification unit, provided with a first node, a second node, a third node, and a fourth node; a first N-channel metal oxide semiconductor (NMOS) transistor and a second NMOS transistor, the first NMOS transistor being provided with one terminal connected to the first node and another terminal connected to one terminal of the second NMOS transistor, another terminal of the second NMOS transistor being connected to the second node, a gate of one of the first NMOS transistor and the second NMOS transistor being configured to receive a first complementary feedback signal, and a gate of the other one of the first NMOS transistor and the second NMOS transistor being configured to receive an enable signal.

Abstract: A drive circuit, a method for driving the drive circuit and a memory are provided. The drive circuit includes a word line drive circuit and a first control circuit. The word line drive circuit includes an input terminal, an output terminal and at least one N-type transistor. The word line drive circuit is configured to provide an output signal to the output terminal according to an input signal received by the input terminal. The first control circuit is configured to pull down, in response to the input signal being a first control signal, a voltage of a substrate terminal of the at least one N-type transistor in the word line drive circuit, to reduce a leakage current of the at least one N-type transistor.

Abstract: A method for manufacturing the mask structure includes: forming a first mask layer, a first buffer layer, a second mask layer, and a second buffer layer sequentially stacked from bottom to top; patterning the second buffer layer and the second mask layer, as to obtain a first pattern structure, the first pattern structure exposes a part of the first buffer layer; forming a first mask pattern on sidewalls of the first pattern structure; forming a carbon plasma layer as a protective layer on an exposed part of an upper surface of the first buffer layer; removing the first pattern structure; and removing a remaining protective layer.

Abstract: A die, a memory and a method of manufacturing the die are provided. The die includes a substrate and a conductive structure, where the substrate has an interconnection structure layer, the conductive structure includes a first conductive structure and a second conductive structure connected with the first conductive structure, the first conductive structure is connected with the interconnection structure layer, and a coefficient of thermal expansion of the first conductive structure is smaller than that of copper.

Abstract: A reticle detection apparatus includes a processing unit, an optical detection unit, and an auxiliary detection unit; the optical detection unit is configured to determine whether there is a reticle according to the intensity of the received light; the processing unit is configured to start the auxiliary detection unit when the optical detection unit does not detect the reticle; the auxiliary detection unit is configured to detect whether there is a reticle based on the piezoelectric effect or the acoustoelectric effect; wherein, after the auxiliary detection unit is started, the processing unit is configured to serve the detection result of the auxiliary detection unit as a basis for determining whether there is a reticle.

Abstract: The present application provides a manufacturing method of a semiconductor structure, and relates to the technical field of semiconductors. The manufacturing method includes: providing a substrate; and forming multiple spaced first isolation sidewall structures on the substrate, where first opening regions are formed between adjacent first isolation sidewall structures, and each of the first opening regions is used to expose at least two columns of active regions.

Abstract: Embodiments provide a system for monitoring an environment and a monitoring method based on a system for monitoring an environment. The system for monitoring the environment includes: a sampling device, configured to collect environmental samples from the process areas and including a system sampling pipeline, the environmental sample containing air; an analysis device, connected to an output end of the system sampling pipeline and configured to analyze the collected environmental samples; and an air supply device, connected to the system sampling pipeline and configured to provide a purge gas and purge the system sampling pipeline using the purge gas. In a period for a single sampling, a ratio between a time period for purging the system sampling pipeline using the air supply device and a time period for sampling by the sampling device is controlled to be 1:5.

Abstract: Provided are a sense amplifying circuit and method, and a semiconductor memory. The sense amplifying circuit includes: a transmission circuit, configured to receive a signal to be processed and perform transmission on the signal to be processed to obtain an initial transmission signal; and an amplifying circuit, configured to receive a first control signal and the signal to be processed, and perform amplification on the initial transmission signal according to the first control signal and the signal to be processed to obtain a target transmission signal.

Abstract: The present application provides a method for manufacturing a semiconductor device, and a semiconductor device. The method includes: providing a substrate; forming a first conductive material layer on the substrate; performing plasma treatment on the first conductive material layer to form a first conductive layer; successively forming a second conductive layer, a first block layer, a third conductive layer and a fourth conductive layer on the first conductive layer; forming a dielectric layer on the fourth conductive layer, and forming an ohmic contact layer at a junction of the first conductive layer and the second conductive layer; forming an initial bit line structure; performing NH3/N2 plasma treatment on the initial bit line structure to form a second block layer on a sidewall of the first conductive layer and a third block layer on a sidewall of the ohmic contact layer.

Abstract: A method for preparing a semiconductor structure includes: providing a semiconductor substrate; forming a groove in the semiconductor substrate; forming a first insulation layer, the first insulation layer at least covering an inner wall of the groove; forming a channel layer, the channel layer at least covering an inner wall of the first insulation layer; forming a second insulation layer, the second insulation layer at least covering an inner wall of the channel layer; filling the groove with a word line structure; removing part of the semiconductor substrate, part of the first insulation layer, and part of the channel layer, and forming a recess region in an outer side wall of the second insulation layer; and forming a source-drain in the recess region, the source-drain being electrically connected with the channel layer.

Abstract: The embodiment of the present invention provides a semiconductor structure and a manufacturing method thereof. The semiconductor structure comprises: a substrate having a trench therein; a first layer covering the bottom and the sidewall of the trench; and a second layer covering the surface of the first layer, wherein the step coverage of the second layer is different from the step coverage of the first layer. The embodiment of the invention is conducive to obtaining a multi-layer structure with preset step coverage.

Abstract: A layout structure and a method for fabricating the same. A frequency divider pattern layer includes a first frequency divider region, a second frequency divider region, a third frequency divider region and a fourth frequency divider region arranged centrosymmetrically. A conductor pattern layer includes a first sub-conductor pattern layer and a second sub-conductor pattern layer stacked. The first sub-conductor pattern layer is configured to communicate the first frequency divider region with the second frequency divider region, and communicate the third frequency divider region with the fourth frequency divider region. The second sub-conductor pattern layer is configured to communicate the first frequency divider region with the fourth frequency divider region, and communicate the second frequency divider region with the third frequency divider region. The embodiments reduce a channel transmission difference between different frequency dividers in a frequency divider structure.

Abstract: Embodiments provide a memory and a fabrication method thereof, and relates to the field of storage device technology to solve the technical problem of lower storage density of the memory. The fabrication method of the memory includes: providing a substrate including a central region and an edge region connected to each other, a first contact structure electrically connected to a wordline structure in the substrate being formed in the edge region; forming a second contact structure electrically connected to the first contact structure on the edge region; forming a capacitor structure electrically connected to the wordline structure on the central region; forming a third contact structure electrically connected to the second contact structure on the second contact structure; and forming a transistor structure electrically connected to the wordline structure on the capacitor structure and the third contact structure.

Abstract: A mask includes a first boundary area and a plurality of exposure pattern areas, the first boundary area including a region surrounding the plurality of exposure pattern areas; in the first boundary area is disposed a plurality of first overlay mark units, each of which includes a plurality of overlay marks; the plurality of overlay marks are sequentially arranged along extension directions of adjacent transversal or longitudinal first boundary lines; a plurality of first overlay mark units are symmetric in pairs with a central line of the mask as a symmetric axis, and two symmetric first overlay mark units form an overlay mark set; arrangement directions of two overlay marks in the first overlay mark units in the same overlay mark set are parallel to and displaced with respect to each other.

Abstract: The embodiments of the present disclosure belong to the field of semiconductor manufacturing technology and relates to a method for manufacturing a semiconductor structure and a semiconductor structure. The method for manufacturing the semiconductor structure includes: a bit line structure is formed on a substrate, a fill channel is formed between the insulating structures on two adjacent bit lines; a conductor is formed within the fill channel; at least one slit is formed on the conductor along a direction perpendicular to a longitudinal direction of each of the plurality of bit line to divide the conductor into a plurality of conductive blocks, each of the plurality of conductive blocks is connected to one of transistors on the substrate.

Abstract: The present application relates to a method and apparatus for batch testing device, related a computer device and a medium. The method includes: writing a corresponding test identification into each of the devices to be tested, wherein different devices to be tested have different test identifications; acquiring a device identification of each of the devices to be tested and generating a device identification sequence; sending corresponding test cases to the devices to be tested sequentially according to the device identification sequence, so that each of the devices to be tested executes the corresponding test case; and generating a test result for each of the devices to be tested, the test result corresponding to the corresponding test identification.

Abstract: Embodiments provide a ring oscillator and test method. The ring oscillator includes a first logic gate, a second logic gate, and a switch circuit. The first logic gate is configured to receive a test signal. The second logic gate includes a first NAND gate and a first NOR gate connected in sequence. An output terminal of the second logic gate is connected to an input terminal of the first logic gate, and the second logic gate is configured to receive output of the first logic gate to form a loop. The switch circuit includes a first switch circuit and a second switch circuit. The first switch circuit may be configured to control on/off of a power supply terminal of the first NAND gate and a ground terminal of the first NOR gate. The second switch circuit is configured to control on/off of a ground terminal of the first NAND gate.

Abstract: Embodiments relate to a sense amplifier circuit and a data read method. The sense amplifier circuit includes: a first P-type transistor connected to a first signal terminal; a second P-type transistor connected to a second signal terminal; a first N-type transistor connected to a third signal terminal; a second N-type transistor connected to a fourth signal terminal; a first offset cancellation subcircuit configured to connect a first read bit line to a second complementary read bit line in response to a first offset cancellation signal; a second offset cancellation subcircuit configured to connect a first complementary read bit line to a second read bit line in response to a second offset cancellation signal; a first write-back subcircuit configured to connect the first complementary read bit line to the second complementary read bit line in response to a first write-back signal; and a second write-back subcircuit.

Abstract: The present disclosure provides a method of manufacturing a buried bit line structure and a buried bit line structure. The method of manufacturing a buried bit line structure includes: providing an initial structure, the initial structure including active region structures; forming an initial bit line trench, the initial bit line trench exposing the active region structure; forming a conductive structure, the conductive structure being located at the bottom of the initial bit line trench; forming a bit line contact structure, the bit line contact structure covering the conductive structure, and a top surface of the bit line contact structure being lower than a top surface of the active region structure; and forming an insulation structure, the insulation structure covering the bit line contact structure.

Abstract: A cleaning process for cleaning a surface of a semiconductor structure is provided, in which residue layer is formed on the surface of the semiconductor structure. The cleaning process includes providing a first reaction gas and a second reaction gas to the surface of the semiconductor structure, in which the first reaction gas reacts with the second reaction gas to remove the residue layer while forming a protection layer on the surface of the semiconductor structure.