Abstract: Apparatuses and methods for detecting interaction of a user with a sensor array disposed on the wall of a protrusion from the surface of a control panel of a device that physically resembles a mechanical knob protruding from the surface of the control panel of the device. The method may include receiving a plurality of signals from the sensor array and detecting interaction of a user with the sensor array based on the plurality of signals.

Abstract: Apparatuses and methods of signal-flow aware supply routing are described. A programmable routing system is configured to route supply signals from a supply generator circuit to one or more functional blocks based on signal channels of the functional blocks.

Abstract: A charge pump, comprising a charge pump output may be operatively coupled to a filter input of a loop filter. A first amplifier input of an operational transconductance amplifier (OTA) may be operatively coupled to the filter input and the charge pump output, and the second amplifier input is operatively coupled to the amplifier output and filter output.

Abstract: A method in accordance with one embodiment of the invention may include receiving a first encryption key. A second encryption key may be generated, and a first data packet containing the second encryption key may be generated and at least part of the first data packet encrypted using the first encryption key. A second data packet may be generated and at least part of the second data packet encrypted using the second encryption key.

Abstract: Embodiments of a capacitive sensor array may comprise a large sensor electrode and a plurality of small sensor electrodes, including a first small sensor electrode, a second small sensor electrode, and a third small sensor electrode. The large sensor electrode and the plurality of small sensor electrodes may be formed from a single layer of conductive material. The first small sensor electrode may be located on the same lateral side of the large sensor electrode as the second small sensor electrode, may be consecutive with the second small sensor electrode in a spatial order of the small sensor electrodes along a longitudinal axis of the large sensor electrode, and may be located on an opposite lateral side of the large sensor electrode from the third small sensor electrode. For each small sensor electrode of the plurality of small sensor electrodes, at least a portion of the small sensor electrode may be located between two interior points of the large sensor electrode.

Abstract: A computing system includes a sensor configured to detect user inputs. The system further includes a processor configured to receive a detected first user input from the sensor. The processor further receives a detected second user input from the sensor. In response, the processor assigns a command to the first user input based on the second user input.

Abstract: A system interface of a processing system receives an indication to initiate configuration of a programmable system. A processing device coupled to the system interface and associated with an integrated development environment, responsive to the indication, translates a hardware description code into one or more configuration files specific to the programmable system, the hardware description code to describe circuitry in the programmable system. The processing device further generates program code for a microcontroller of the programmable system based, at least in part, on the hardware description code, and configures the programmable system to implement the circuitry according to the configuration files and the program code. In addition, the processing device debugs the programmable system as configured by the configuration files and the program code.

Abstract: A method and apparatus receive a plurality of signals that are used to calculate a position of a conductive object relative to a capacitive sensor element and determine an estimated position error through the plurality of signals, the estimated position error to offset a position error of the calculated position.

Abstract: Apparatus, systems, and methods for providing high voltage to memory devices are provided. One apparatus includes a low voltage input and a two-rail level shifting. The two-rail level shifting is configured to increase the low voltage or to decrease the low voltage to an amount that is less than or equal to a ground potential based on the amount of the low voltage. A system includes a low voltage input for receiving a voltage and a two-rail level shifting coupled to the low voltage input. The two-rail level shifting is configured to increase the voltage to a positive voltage if the voltage is equal to a ground potential and decrease the voltage to a negative voltage if the voltage is greater than the ground potential. One method includes receiving a voltage, modifying the voltage to generate one of a plurality of output voltages, and providing the output voltage to a memory device.

Abstract: Techniques for placement in highly constraint chip architectures are described herein. In an example embodiment, a computer system places a digital portion of an electronic design for a programmable chip. The programmable chip comprises multiple fixed-function blocks and a plurality of pins, where each one of the multiple fixed-function blocks can be coupled only to a respective subset of the plurality of pins. The electronic design comprises a particular fixed-function block (FFB) instance that is connected to a particular input-output (IO) instance. The computer system places (e.g., by using a backtracking search) the particular FFB instance on a particular fixed-function block and the particular IO instance on a particular pin from a particular subset of the plurality of pins, where in the programmable chip the particular fixed-function block can be coupled only to the particular subset of the plurality of pins.

Abstract: A circuit with a plurality of analog circuit blocks, each configured to provide at least one analog function and a programmable interconnect coupled of the analog circuit blocks and configurable to interconnect combinations of the analog circuit blocks to one another. The circuit is formed in an integrated circuit (chip) and the programmable interconnect comprises a plurality of switches coupled between the analog circuit blocks and ports that provide signal connections for the chip.

Abstract: A device for providing electrostatic discharge (ESD) protection is described which includes a silicon controlled rectifier (SCR), a mechanism for triggering the SCR, and a pair of contact regions of opposing conductivity type distinct from regions of the SCR that are interposed between the cathodic and anodic regions of the SCR. The contact regions are configured to collect charge generated by the SCR. In some embodiments, the device may include a transistor and the cathodic region of the SCR may dually serve as a source contact region of the transistor. A circuit is described which includes an ESD protection device coupled between high and low voltage power supply bus bars, wherein the ESD protection device includes an SCR as well as a pair of contact regions of opposing conductivity type distinct from the SCR and interposed between the cathodic and anodic regions of the SCR.

Abstract: Apparatuses and methods of driving different transmit (TX) phase sequences of a TX signal on TX electrodes in different sensing stages according to a weighting matrix as the excitation matrix. One method drives the TX signals according to the weighting matrix and measures receive (RX) signals on the RX electrodes to determine if an object is proximate to the electrodes.

Abstract: A method for fabricating a non-volatile, ferroelectric random access memory (F-RAM) device is described. In one embodiment, the method includes forming an opening in an insulating layer over a surface of a substrate, and forming bottom electrode spacers proximal to sidewalls of the opening. Next, a ferroelectric dielectric layer is formed in the opening over the surface of the substrate and between the bottom electrode spacers, and a pair of top electrodes is formed within the opening comprising first and second side portions displaced laterally from respective ones of the bottom electrode spacers by the ferroelectric dielectric layer.

Abstract: A capacitance sensing system may include a current conveyor circuit coupled to receive induced current from a capacitance sensing structure at a low impedance current input port; and a comparator having an input coupled to a high impedance output port of the current conveyor circuit, and an output coupled to the current conveyor circuit by a feedback path and coupled to drive the capacitance sensing structure to generate the induced current.

Abstract: A dynamic adjusting RFID demodulator circuit includes an envelope detector having an input for receiving a modulated RF signal, a fixed reference generator coupled to the input of an RC filter, an RF level dependent signal path adding to the fixed reference level at higher RF energy levels, a comparator having a first input coupled to an output of the envelope detector, a second input coupled to an output of the RC filter, and an output for providing a data output signal.

Abstract: An apparatus includes a memory and a processing device comprising touch sorting logic. The touch sorting logic sorts the raw touch position data in two stages. In each of the stages, the touch sorting logic predicts the centroid positions for each touch of the plurality of touches, compares the predicted centroid positions for each touch and indexes the centroid position for each touch based on the predicted centroid position that is closest to the raw touch position data. The sorted touch position data is sorted according to the touch index assigned to each of the centroid positions for each of the plurality of touches.

Abstract: A voltage regulator for low power operation of digital circuits includes an output node for providing a regulated output voltage, a diode-connected P-channel transistor in series with a second diode-connected N-channel transistor coupled between the output node and ground, and a bias current having a value for biasing the first and second diode-connected transistors in a sub-threshold mode of operation. The low power voltage regulator further includes a buffer amplifier or emitter or source follower stage to provide a low impedance regulated voltage. The bias current may be generated by a bandgap circuit.

Abstract: A method and device for supplementing current from the USB bus for enumerating USB devices that require additional current beyond that allowable by USB bus specification is disclosed. A chargeable power source, such as a capacitor or rechargeable battery, is supplied to the enumeration circuitry and is charged from the USB bus for an initial period of time. The charged power source is then discharged to supplement the allowable current available for enumeration during a second period of time. It is during this second period of time that the enumeration takes place. The circuitry may exist in the USB device or may be supplied separately as a power monitor or power maintenance chip or device.

Abstract: A system, comprising: a plurality of modules, each module comprising a plurality of integrated circuits devices coupled to a module bus and a channel interface that communicates with a memory controller, at least a first module having a portion of its total module address space composed of first type memory cells having a first maximum access speed, and at least a second module having a portion of its total module address space composed of second type memory cells having a second maximum access speed slower than the first access speed.