Abstract: A surface acoustic wave (SAW) expander based transmitter and correlator based receiver comprises SAW devices that perform expander or correlator functions based on the types of signals inputted to the SAW devices. The SAW devices incorporate chirp with adaptive interference and programmable coding capabilities. The SAW devices and method of operating the devices allow the implementation of very low power radios that overcome problems with temperature drift, lithography constraints and interference and jamming suffered by prior art implementations.

Abstract: An improved method and apparatus is described for using a direct sequence spread spectrum (DSSS) system that takes advantage of multiplicative pseudo-noise codes (PN-Codes) in order to wirelessly connect multiple peripherals in a computer system at different data rates. The use of multiplicative PN-Codes allows the system to use multiple-length PN-Codes within the same system while minimizing the hardware needed to implement such a system. The improved method and apparatus also uses an identifier in the transmitted packet header in order to communicate the choice of PN-Code to the receiver. By using multiple-length PN-Codes in conjunction with an identifier in the packet header the improved method and apparatus allows for remote peripherals to choose a suitable data rate on a packet-by-packet basis while minimizing the system complexity.

Abstract: A test system and method are provided for testing in parallel radiant output of multiple light emitting devices. Generally, the method involves: (i) providing a system having a master, calibrated power meter (CPM), a source transfer standard (STS), and multiple secondary, test site power meters (TSPMs); (ii) determining a relationship between electrical power supplied to the STS and a radiant output therefrom as measured by the CPM; (iii) calibrating the TSPMs using the STS and the relationship between the power supplied to the STS and the radiant output therefrom as determined by the CPM; and (iv) positioning the devices undergoing test on a fixture of the test system and positioning the fixture relative to the TSPMs to test radiant outputs of the devices.

Abstract: A timer circuit is disclosed. The timer, having a delay configured to track inversely with temperature of the memory device, includes a reference signal configured to increase in voltage, as the temperature of the memory device increases. The reference signal may be generated from a current that is derived from a bandgap reference circuit. The timer circuit includes a pull-down path made up of a plurality of selectable pull down transistors which are coupled to the reference signal at the gate. Resistance of the pull-down path is reduced as the reference signal is increased and the reduced resistance of the pull-down path decreases the delay of timer. A plurality of selectable delay elements may be preconfigured to adjust the delay and are coupled to the output path of the current starved inverter.

Abstract: Disclosed are a circuit and a method for an analog-to-digital conversion with programmable resolution. The circuit includes a resistor ladder comprising a plurality of resistors coupled to a plurality of comparators; wherein the resistor ladder is further coupled to a switch logic circuit and a plurality of current sources; and wherein the switch logic circuit is configured to control an operation of a plurality of switches to alter conversion resolution of the ADC, and an error correction circuit coupled to the outputs of the plurality of comparators, wherein the ADC is configured to perform a first conversion step and a second conversion step, and wherein the ADC is configured to perform only the first conversion step when programmed for lower conversion accuracy and higher conversion speed.

Abstract: Systems and method for tracking different types of transconductance cells is shown and described. In these multi-cell systems, the addition of one or more tracking control modules allows circuit designers to advantageously incorporate multiple transconductor topologies and their uniquely beneficial characteristics into their designs, without eradicating its centralized multi-cell tuning functionality.

Abstract: A phase lock loop pre-charging system and method are described. In one embodiment, a phase lock loop pre-charge system includes a bias component for generating a pre-charge voltage, and an activation component for activating the bias component. In one exemplary implementation the pre-charge voltage is utilized to facilitate pre-charging of a phase lock loop voltage controlled oscillator. In one embodiment, the bias component includes replica bias components that track the voltage controlled oscillation control voltage over varying process, voltage and temperature characteristics. The phase lock loop pre-charging systems and methods can be utilized to reduce lock time for a circuit.

Abstract: A technique for receiving an error state in a single chip sequence in a wireless communications network is disclosed. The error state may comprise a Viterbi error state. The error state may be identified as a target code encoded in the single chip sequence, the target code comprising either a code or the complement of the code. The code may comprise a PN-Code. The error state may be identified using a previous mapping of error states from a set of error states to a group of codes, the group of codes comprising a plurality of codes and their complements. The error states in the set of error states in the previous mapping may be uniquely mapped to plurality of codes and their complements in the group of codes.

Abstract: A non-keyboard computer peripheral device represents itself to a host computer as having a keyboard function in addition to representing its actual function. Keyboard status signals are generated by the host computer in response to a user pressing different keys on an actual keyboard. The peripheral device uses the keyboard status signals to identify different peripheral device operations selected by the user. In one example, a radio receiving device represents itself to the host computer as including the keyboard function. Pressing a button on the receiving device causes the receiving device to send a sequence of keystroke commands to the host computer that cause the host computer to initiate software applications and to display operating instructions to a user. A series of further binding operations are then executed in accordance with the displayed operating instructions.

Abstract: In one embodiment, an integrated circuit includes a PMOS transistor having a gate stack comprising a P+ doped gate polysilicon layer and a nitrided gate oxide (NGOX) layer. The NGOX layer may be over a silicon substrate. The integrated circuit further includes an interconnect line formed over the transistor. The interconnect line includes a hydrogen getter material and may comprise a single material or stack of materials. The interconnect line advantageously getters hydrogen (e.g., H2 or H2O) that would otherwise be trapped in the NGOX layer/silicon substrate interface, thereby improving the negative bias temperature instability (NBTI) lifetime of the transistor.

Abstract: Customization methodology for integrated circuit (e.g., clocks) design customization using a software tool that integrates multiple integrated circuit development operations.

Abstract: An improved method of framing data packets in a direct sequence spread spectrum (DSSS) system that uses one pseudo-noise code (PN-Code) to frame the packet with a start-of-packet (SOP) and end-of-packet (EOP) indicator, and a different PN-Code to encode the data payload. Furthermore, the SOP is represented by the framing PN-Code, and the EOP is represented by the inverse of the framing PN-Code. This method creates a robust framing system that enables a DSSS system to operate with a low threshold of detection, thus maximizing transmission range even in noisy environments. Additionally, the PN-Code used for the SOP and EOP indicators can be used to indicate an acknowledgement response.

Abstract: A transmission line equalizer, communication system, and method are provided for adaptively compensating for changes in transmission path length and transmission path medium. Within the equalizer is a filter that exhibits a high pass characteristic and, more specifically, has an inverse frequency response to that of the transmission path. The inverse filter can include a pair of amplifier stages coupled in parallel, with a mixer chosen to adaptively select portions of one stage over than of the other. The dual stage inverse filter can, therefore, adapt to greater transmission path lengths and/or attenuation. A feedback architecture is used to set the inverse filter response by measuring the amplitude of a communication signal output from the inverse filter during periods of low frequency. A peak detector will capture a peak-to-peak voltage value during those periods, and adjust the output of the slicer to match a launch amplitude of the communication signal.

Abstract: An oscillator circuit is provided having an oscillating amplifier circuit connected to a resonator. The oscillator/amplifier and resonator are preferably fabricated on a single die using semiconductor fabrication tools. Included with the circuitry is a temperature sensor or transducer, an execution unit, non-volatile memory, a modulator, and frequency synthesizer, all of which are integrated together on the substrate, along with the piezoelectric crystal resonator. The frequency synthesizer can preferably include a phase-locked loop with a divider that is in a feedback loop of the phase-locked loop, in which a divide-by value is received from a modulator that achieves finer and higher resolution frequency selectivity from the voltage-controlled oscillator, also within the phase-locked loop, as an output from the crystal oscillator.

Abstract: A memory device, current sense amplifier and method of operating the same are disclosed herein. In accordance with one embodiment, the current sense amplifier circuit may include a pair of cross-coupled transistors, a pair of output nodes and a first pair of load transistors. The pair of cross-coupled transistors may be coupled for receiving a pair of differential currents and for generating a pair of differential voltages, which may then be supplied to the pair of output nodes. The first pair of load transistors may have mutually-connected gate terminals, mutually-connected drain terminals, and a source terminal coupled to a different one of the output nodes. In a unique aspect of the invention, an equalization transistor may coupled between the pair of output nodes for equalizing the pair of differential voltages for a predetermined amount of time at the beginning of a sense cycle.

Abstract: An improved key matrix scanning technique conducts a first pre-scan on a first array of connections in a key matrix to identify any activated keys or buttons associated with the first array. A second sub-scan is conducted on a second array of connections in the key matrix but only for the connections in the first array that are detected as having activated keys.

Abstract: An input buffer has a high voltage leg in parallel with a low voltage leg. The low voltage leg pulls up the pad when the pad voltage is below the power supply voltage. The high voltage leg remains off when the pad voltage is below the power supply. The low voltage leg is turned off when the pad voltage is above the power supply voltage. The high voltage leg is on when the pad voltage is above power supply voltage. A low voltage bias circuit and a high voltage bias circuit protect the transistors in the low and voltage legs when the pad voltage is above the power supply voltage. As a result, the pull-up circuit is high voltage tolerant and does not sink the current from pad.

Abstract: A circuit in accordance with one embodiment of the invention can include a light emitting diode (LED) assembly comprising a plurality of LED channels that are controlled independently with a switch mode driver. The circuit also includes N+1 wires coupled to said LED assembly, where N is equal to the number of said plurality of LED channels of said LED assembly.

Abstract: A pixel structure is described, comprising at least two selection switches coupled in series to improve the yield of the pixel. Also an array comprising such pixel structures logically organized in rows and columns is described, as well as a method for selecting a row or column of pixel structures in such an array.

Abstract: A multiplexer circuit, system and method is provided herein for multiplexing signals with reduced jitter by eliminating all crosstalk and power supply noise injection within the multiplexer circuit. For example, crosstalk and supply noise injection may be eliminated by: (i) separating the multiplexing function into three separate logic gates and (ii) allowing only one switching input per logic gate. In some cases, jitter may be further reduced by distributing the logic gates across three distinct power domains. In other words, the logic gate inputs may be further isolated by gating each signal in its own power domain. In addition, the multiplexer circuit provides built in delay matching by utilizing three substantially identical logic gates.