Abstract: In one embodiment, an integrated circuit package includes a lead frame with a die paddle and several leads. Portions of the lead frame not having an external electrical connection may be thinned such that they may be encapsulated by an electrically insulating packaging material on the back of the lead frame. Portions of the lead frame having external electrical connections may have a thickness such that they are exposed through the packaging material. The lead frame may be covered by an electrically insulating cover to protect components on the lead frame from erroneous electrical contact or electrostatic discharge (ESD) damage.

Abstract: This invention is directed to a process for etching a semiconductor device using an etchant composition to form a predetermined etched pattern therein. The semiconductor device typically has a plurality of layers. At least one of the layers comprises a refractory metal, refractory metal alloy or refractory metal silicide. The etchant composition contains a high concentration of chlorine. The source (or TCP) power is decreased over that of conventional methods, and the bias (or RF) power is increased. Using such an etchant composition, along with the adjusted power levels, uniform etching and increased oxide selectivity is achieved.

Abstract: A method and an apparatus are described for shorted input detection for amplifier circuits. An embodiment of a circuit includes multiple amplifier circuits, with each amplifier circuit having an input and an output. The circuit also includes multiple short detection circuits, with one of the short detection circuits being coupled to the input of each amplifier circuit. Each short detection circuit has an active state for detection of short circuits and an inactive state for normal amplifier operation. The circuit also includes a register coupled with the output of each of the amplifier circuits to hold the output of one or more of the amplifier circuits.

Abstract: Disclosed is a high voltage switch circuit that can include a first well bias switch configured to track the greater of an input voltage and a supply voltage, a voltage comparator configurable to compare the input voltage to a predetermined reference voltage, and a second well bias switch having a control input coupled to an output of the comparator.

Abstract: A driver circuit, system, and method is provided. The driver circuit includes a plurality of delay cells or circuits, each comprising a set of flip-flop circuits coupled in series to produce a staged set of outputs onto an output port of the driver circuit. The staged outputs are sequentially applied to the output port at a time depending on the number of flip-flop circuits within each stage. The number of such circuits can be programmably modified so that the slew rate output of the driver circuit can be programmably changed. The driver circuit can be a low speed driver circuit clocked by a low speed clocking signal of, for example, 1.5 MHz, with the slew rate derived by a clocking signal of, for example, 480 MHz. The higher speed clocking signal clocks the flip-flop circuits, yet the output is staged so that the low speed driver circuit transitions between logic states using the higher speed clock, but at a must slower edge rate.

Abstract: A circuit having a high voltage, drain-extended (DE) metal-oxide-semiconductor (MOS) transistor and method for fabricating the same are provided. Generally, the circuit includes an n-channel (NMOS) transistor having: (i) a source and drain formed in a substrate, the source separated from the drain by a channel; and (ii) a diffused deep n-well (DNW) formed by a long, high temperature drive-in step. The DNW forms a drain-extension region for the NMOS transistor surrounding the drain and extending a predetermined distance into the channel. The drain extension region has a doping concentration lower than the source and drain to deplete during reverse biasing of the transistor, thereby raising a breakdown voltage of the transistor. Preferably, the circuit further includes a DE p-channel MOS (PMOS) transistor in which the DNW forms a well tub for the PMOS transistor, and a p-well in DNW forms a DE region therefore. Other embodiments are also disclosed.

Abstract: A pixel structure having a shielded storage node. A pixel comprises a sample transistor coupled to a light detecting stage. The sample transistor comprises an inner junction region surrounding and coupled to a storage node and a gate disposed around at least three sides of the inner junction region that operates as a charge barrier to shield the storage node. A memory capacitor is coupled to the storage node.

Abstract: Disclosed are a circuit and a method for a high speed, low supply voltage tolerant bootstrapped word line driver with high voltage isolation. The circuit includes a low voltage driver. A gate bootstrapped transistor is coupled to the low voltage driver. A first transistor is coupled to an output terminal of the gate bootstrapped transistor. A substrate of the first transistor is coupled to a negative bias signal. A second transistor is coupled to a gate terminal of the gate bootstrapped transistor. A substrate of the first transistor is coupled to a negative bias signal.

Abstract: A variable reference voltage circuit for performing memory operation on non-volatile memory includes a multi-level voltage source and a selector circuit. The multi-level voltage source generates multiple voltages. The selector circuit includes a selector input and a selector output. The selector input is coupled to the multi-level voltage source to selectively couple any of the multiple voltages to the selector output. The selector output of the selector circuit is coupled to a non-volatile memory array to provide the NV memory array with a selectable program voltage for programming the NV memory array and a selectable erase voltage for erasing the NV memory array.

Abstract: A voltage-controlled oscillator is provided that avoids use of any crystal resonator, or any resonator that is external to and not integrated upon the voltage-controlled oscillator monolithic substrate. The present oscillator can receive two or more parameters that would likely have an affect on the oscillator frequency, yet the oscillator includes compensating transfer functions that will remove, or correct for, that effect. Transfer functions involve electronic subsystems implemented in hardware or software that receive the input parameter that has changed from a nominal value, and will note the drift in output frequency, yet will compensate for that drift so that the output frequency remains near the nominal value. The voltage-controlled oscillator preferably is an LCVCO, and the transfer function outputs can be summed to take into account multiple parameter changes.

Abstract: Methods of fabricating negative-channel metal-oxide semiconductor (NMOS) devices and positive-channel metal-oxide semiconductor (PMOS) devices having complementary threshold voltages are described. Elements of lower-threshold voltage NMOS devices are formed at first locations on a substrate. Elements of higher-threshold voltage PMOS devices are formed at second locations on the substrate. Elements of higher-threshold voltage NMOS devices and elements of lower-threshold PMOS devices are formed by adding a same amount of p-type dopant at selected locations chosen from the first and second locations.

Abstract: One embodiment relates to an optical navigation device. The device includes a lead frame having reference features, a laser, a detector array, and an optical component having alignment features. The laser is attached to the lead frame and positioned in reference to the reference features of the lead frame. The detector array is attached to the lead frame and positioned in reference to the reference features of the lead frame. The optical component is coupled to the lead frame so that its alignment features register to the reference features of the lead frame. In this way, the molded optical component is passively aligned to the laser and the detector array. Other embodiments are also disclosed.

Abstract: A driver circuit is provided herein. In general, the driver circuit includes a driver portion, a common mode feedback portion and a current replication portion. The feedback portion receives a common mode voltage (vcm) from the driver portion and an alternative common mode voltage (vcm_alt) from the current replication portion. The feedback portion selects one of the common mode voltages for comparison with a reference voltage and generates a feedback bias signal (vcmfb) based on a voltage difference there between. When the driver circuit is enabled, the actual common mode voltage (vcm) is used to maintain the output common mode voltage around the reference voltage. When the driver circuit is disabled, the alternative common mode voltage (vcm_alt) is used to keep the bias signal (vcmfb) from drifting away.

Abstract: A transmitter digital signal processor (DSP) circuit has a transmit frequency represented by n-bit data output from a look up table (LUT). The n-bit data is outputted to an n-bit accumulator structured to overflow at a rate based on the output n-bit data to output a phase. The circuit further has device structured to add an n-bit signed constant to the accumulator to offset the frequency represented by the n-bit data output from the LUT. A transceiver on a semiconductor chip may include as part of a transmitter circuit, a transmit DSP circuit that has the LUT, accumulator and device providing an n-bit signed constant to the accumulator to offset a transmit frequency in order to allow a receiver circuit on the transceiver to communicate directly with the transmitter circuit, and thus allowing testing of the transceiver.

Abstract: An improved amplifier circuit is provided herein with a gain stage and a bias stage, which may be switchably connected to the gain stage during power-up operations. The bias stage reduces a power-up time associated with the gain stage, while minimizing current consumption in the next amplifier stage and improving battery life. For example, during power-up, the bias stage may enable the output voltage of the gain stage to gradually rise from a ground potential to a desired common mode level in a highly controlled and predictable manner. By preventing “glitches” in the output voltage, the bias stage eliminates the need for inserting switches in the signal path between the output nodes of the gain stage and input nodes of the next amplifier stage.

Abstract: A device includes a first wireless transceiver adapted to communicate over a cellular network, a second wireless transceiver adapted to communicate over a local network separate from the cellular network, and a mechanism adapted to report movement information to a computer via the second wireless transceiver. The mechanism is optionally an optical sensor reporting relative position information. The device is operable as both a cellular communication device and a computer pointing device. A button of the device is adapted to operate as a mouse button, and optionally, in some modes, controls operation of the cellular communication device. The second wireless transceiver optionally uses Universal Serial Bus protocol. The device optionally transfers files via the second wireless transceiver. In some usage scenarios, the device and a separate wireless pointing device communicate with a same computer and are used to operate an application, such as a gaming application.

Abstract: Power management commands are provided to a power management unit of a processing device, wherein the power management unit coupled to a core system block of the processing device. Sampling of the core system block is performed in response to the power management commands by the power management unit, wherein sampling includes periodically powering the core system block.

Abstract: We disclose an apparatus capable of receiving control command data for one or more electrical fixtures and modulating an alternating current by modifying firing phase angles to transmit the data corresponding to the control commands via a power line transmitting the alternating current.

Abstract: A driver circuit, and light emitting system and method are provided. The driver circuit includes possibly a controller and a phase detector coupled to produce an intermittent output proportional to a value of an input relative to upper and lower threshold values, and a difference between the input signal, which is the intermittent output signal, and a reference value. The light emitting system can include a switch and at least one light emitting device coupled to the switch. The driver circuit can be coupled to forward the intermittent output signal to the switch that is active in proportion to current level through the light emitting device, rising and falling between the modifiable upper and lower threshold values.

Abstract: One embodiment in accordance with the invention can include a circuit for controlling a light emitting diode (LED) lighting fixture via a power line. The circuit can include a power switch coupled to the power line and is for outputting a firing angle. Additionally, the circuit can include a control circuit coupled to the power switch and is for implementing firing angle control of the power switch. Furthermore, the circuit can include a translator coupled to receive the firing angle and for mapping the firing angle to a function of the LED lighting fixture.