Abstract: A memory circuit includes volatile memory cells coupled to bit lines, and nonvolatile memory cells coupled to the volatile memory cells via the bit lines but not via complement bit lines.

Abstract: A time delayed integration image sensor provides over-sampled image data on a time-shared column bus to maintain data synchronization.

Abstract: A circuit and method are provided that eliminate race conditions in data storage devices. Generally, the circuit includes: (i) an input latch to which an address signal (ADD) is applied; (ii) a multiplexer (MUX) to which the ADD is coupled from the input latch and through which an output is supplied to an output latch; (iii) an address valid signal (ADV) input coupled to the output latch and to which an ADV is applied to close the output latch supplying the output to a circuit output; and (iv) a middle latch coupled between the input latch and the MUX to hold the ADD applied to the MUX until the output latch closes, independent of a change in the ADD applied to the input latch. Preferably, the circuit includes control logic configured to close the middle latch on a rising edge of ADV and reopen it when the output latch closes.

Abstract: A method for fabricating a nonvolatile charge trap memory device is described. The method includes first forming a tunnel dielectric layer on a substrate in a first process chamber of a single-wafer cluster tool. A charge-trapping layer is then formed on the tunnel dielectric layer in a second process chamber of the single-wafer cluster tool. A top dielectric layer is then formed on the charge-trapping layer in the second or in a third process chamber of the single-wafer cluster tool.

Abstract: A charge pump control circuit that four main parts: a clock control circuit; a clock switch and driver circuit; a pump stage; and a dynamic load control circuit. The clock control circuit has a dynamic load that is controlled by the dynamic load control circuit. When the charge pump control circuit is enabled, the dynamic capacitive load is applied which incorporates a delay allowing the high frequency clock to control the pump stage and quickly charge the output to the desired boosted voltage. This provides a very fast boosted output voltage during a startup condition. Once the desired output voltage is realized, the dynamic capacitive load is disabled and the low frequency clock takes over the operation. During each low frequency clock cycle, the high frequency clock is enabled for several cycles per cycle of the low frequency clock.

Abstract: An electrostatic discharge protection device for protecting a node includes a transistor, a silicon controlled rectifier, a second contact region laterally displaced from the first contact region, and a collection region adjacent the source region. The transistor includes a semiconductor substrate, a source region, a channel region adjacent the source region, a gate over the channel region, and a drain region laterally displaced from the channel. The silicon controlled rectifier includes the source region, a portion of the substrate, a doped well, and a first contact region in the well, laterally displaced from the drain region. The collection region, the source region and the gate, are metallically connected. The node, the first contact region, and the second contact region, are metallically connected, and the drain region is not metallically connected to the node.

Abstract: A capacitive sensor with ratiometric voltage references includes a voltage source, a charge transfer switch, an integrating capacitor, and a comparator. The voltage source is configured to generate a first voltage reference and a second voltage reference in response to a supply voltage, where the first voltage reference changes proportionally to the second voltage reference in response to a change in the supply voltage. The charge transfer switch is coupled to the integrating capacitor to distribute charge between a sensing capacitor and the integrating capacitor, where the charge is accumulated in response to the first voltage reference. The comparator is coupled to the second voltage reference and the integrating capacitor to compare a voltage on the integrating capacitor against the second voltage reference.

Abstract: An apparatus for triggering image acquisition in radiography includes an interconnect, a detector to detect radiation and a switch coupled between the interconnect and the detector to charge the interconnect in response to the radiation while the switch is in an open-circuit state. The apparatus also includes control circuitry coupled to the interconnect to detect the charge on the interconnect and to generate a signal indicating presence of the radiation in response to the charge. A method for triggering image acquisition in radiography includes coupling a switch between an interconnect and a detector, then charging an interconnect with that switch in response to radiation incident upon the switch while the switch is in an open-circuit state. Next, the charge on the interconnect is monitored and a signal is generated indicating the presence of the radiation in response to that charge.

Abstract: An improved Received Signal Strength Indicator (RSSI) circuit and method is provided herein for quickly and accurately detecting the strength of a received signal. The circuit described herein provides a more accurate RSSI signal, while consuming less power and die area, by utilizing digital rather than analog summing.

Abstract: A method, system, and computer-readable storage medium are provided for compressing a packet of data sent across a wireless transmission path to reduce power consumption in a wireless input device. The wireless input device preferably includes a human interface device that sends a report that is of variable length and compressed by refraining from transmitting unused bytes of a packet containing the report. Certain byte fields can be swapped, such as a first scan code byte field with a modifier key byte. Also, any reserved bytes that are not used can be removed in order to convert a standard HID report format into the present compressed report format. By removing unused bytes and optimally swapping the more prevalently used byte into the first field while removing any reserved bytes, the compressed report reduces the amount of power consumed to transmit the compressed report, relative to a non-compressed and fixed-length report of conventional HID input devices.

Abstract: A memory device can provide burst access to row boundary crossing addresses without introducing inter-burst latency. Address locations for a first row of the burst can be accessed at speed, while a prefetch latch can be accessed in lieu of a next row.

Abstract: A method and an apparatus are described for an offset correction in a high gain amplifier. An embodiment of an amplifier circuit includes an amplifier to convert a current signal into a voltage signal, where the amplifier generates an offset voltage in the voltage signal. The amplifier circuit also includes a sampling component coupled with the amplifier, with the sampling component subtracting a first sample of the voltage signal from a second sample of the voltage signal to produce a difference value. The amplifier circuit further includes a gain component coupled with the sampling component to amplify the difference between the first sample and the second sample.

Abstract: A circuit including a subcircuit having differential signals, and a feedback circuit coupled to the subcircuit. The feedback circuit is configured to measure an offset between the differential signals, to generate a calibration signal in response to the measurement, and to reduce the offset in response to the calibration signal.

Abstract: Devices for protecting drain extended metal oxide semiconductor (DEMOS) output transistors from damage caused by electrostatic discharge (ESD) events are provided. In general, the devices include a silicon controlled rectifier (SCR) and a DEMOS transistor configured to breakdown at a lower voltage than a breakdown voltage of the output driver transistor it is configured to protect. The devices further include a pair of ohmic regions configured to trigger the SCR upon breakdown of the drain contact region of the DEMOS transistor and a collection region configured to collect charge generated by the SCR. The transistor, the pair of ohmic regions, and the SCR are respectively configured and arranged to independently set the breakdown voltage of the drain contact region, the trigger voltage of the SCR, and the holding voltage of the SCR. One of the ohmic regions may be coupled to the drain contact region of the transistor.

Abstract: Embodiments of the invention include a bus bridge that is capable of communicating with more than one MSC device coupled to it. In some embodiments, the bridge includes a LUN processor that translates different LUN numbers received from the bus into different addresses and LUNs for devices connected to the bridge. The bridge masks the fact that multiple MSC devices are coupled to it by reporting to the host that only a single device having multiple LUNs are coupled to the bridge.

Abstract: In one embodiment, a method of fabricating one or more transistors in an integrated circuit includes an annealing step prior to a gate oxidation step. The annealing step may comprise a rapid thermal annealing (RTA) step performed prior to a gate oxidation pre-clean step. Among other advantages, the annealing step reduces a step height difference between P-doped and N-doped regions of a field oxide of a shallow trench isolation structure. The shallow trench isolation structure may be separating a PMOS transistor and an NMOS transistor in the integrated circuit.

Abstract: An improved ESD protection device, integrated circuit and method for programmably altering a sensitivity of the ESD protection device is provided herein. More specifically, an active shunt ESD protection device is provided with an improved trigger circuit design. The improved trigger circuit design enables the sensitivity of the ESD protection device to be altered by providing a variety of programmable elements for adjusting an RC time constant of a slew rate detector contained therein. The programmable elements allow the RC time constant to be altered at the wafer or package level, and avoid the significant time and cost typically associated with conventional trial-and-error adjustment procedures.

Abstract: An apparatus having a plurality of power supply domains and a plurality of logic components. Each of the plurality of logic components residing within a different one of the plurality of power supply domains. Each of the plurality of logic components is configured to operate with a corresponding clock signal within a respective one of the plurality of power supply domains.

Abstract: A Universal Serial Bus (USB) device uses a same elasticity buffer for buffering packets for multiple different ports and only necessary packet detection circuitry is associated with the individual ports. A collision detection circuit is further included corresponding with information received from the packet detection circuitry. This simplified universal elasticity buffer architecture reduces the complexity and cost of the USB device.

Abstract: A device using a single external resistor for battery charging applications and a software current feedback control loop for use with the external resistor is described. For instance, a single resistor can be used to determine the charge electrical current level being used to charge a battery. The determined level from the single resistor can be used in a feedback loop to set the charge electrical current level and to determine if there is an over current condition requiring the charge current be shut down.