Patents Assigned to Cypress Semiconductor
  • Publication number: 20090153152
    Abstract: A capacitive sensor may include a transmit electrode and a receive electrode capacitively coupled with the transmit electrode. A capacitance sensing circuit senses a capacitance between the transmit and receive electrodes by applying a signal to the transmit electrode and rectifying a current waveform induced at the receive electrode. A compensation circuit reduces the effect of a mutual and parasitic capacitances of the transmit and receive electrode pair by adding a compensation current to the rectified current.
    Type: Application
    Filed: December 11, 2008
    Publication date: June 18, 2009
    Applicant: CYPRESS SEMICONDUCTOR CORPORATION
    Inventors: Andriy Maharyta, Viktor Kremin
  • Publication number: 20090150688
    Abstract: A method and a system for supplying power to a microcontroller with a single cell. One embodiment of the present invention discloses incorporation of a power supply pump circuit with the microcontroller and their dynamic interaction. The microcontroller sends its power requirements to the power supply pump circuit and in response, the power supply pump circuit controls the operating voltage with optimal efficiency. The dynamic update of power supply pump circuit results in an efficient use of the power supply pump circuit and thus results in a reduction of the number of dry cell batteries to only a single cell. Incorporation of the microcontroller and power supply pump circuit onto a single chip reduces the pin number requirements as well as the space required on the printed circuit board.
    Type: Application
    Filed: June 10, 2008
    Publication date: June 11, 2009
    Applicant: CYPRESS SEMICONDUCTOR CORP.
    Inventors: Harold Kutz, Warren Snyder
  • Patent number: 7545694
    Abstract: Disclosed is a high speed and power efficient dual mode sense amplifier circuit, which comprises a configuration selector further comprising a read amplifier, a debug circuit and a backup read circuit. The dual mode sense amplifier circuit also comprises a controllable input node further comprising an enabling circuit, the controllable input node being coupled to the configuration selector and the dual mode sense amplifier circuit comprises a differential signal generator further comprising a reference signal source, the differential signal generator is coupled to the controllable input node. A method of dual mode sensing and other embodiments are also disclosed.
    Type: Grant
    Filed: August 16, 2007
    Date of Patent: June 9, 2009
    Assignee: Cypress Semiconductor Corporation
    Inventors: Vijay Kumar Srinivasa Raghavan, Ryan Tasuo Hirose
  • Patent number: 7545764
    Abstract: A system includes a central controller to transmit a plurality of synchronization codes through a transmission medium and a plurality of satellite controllers, each satellite controller configured to recognize one or more synchronization codes of the plurality of synchronization codes, each satellite controller comprising a synchronous clock signal generator to generate a synchronous clock signal each time the satellite controller recognizes the one or more synchronization codes of the plurality of synchronization codes.
    Type: Grant
    Filed: November 19, 2004
    Date of Patent: June 9, 2009
    Assignee: Cypress Semiconductor Corporation
    Inventor: Mark Francis
  • Patent number: 7539054
    Abstract: A system and method for programming and erasing a semiconductor memory is disclosed. More particularly, the present invention uses the bit lines of a volatile memory portion of semiconductor memory so as to program and erase the non-volatile portion of the semiconductor memory.
    Type: Grant
    Filed: December 22, 2006
    Date of Patent: May 26, 2009
    Assignee: Cypress Semiconductor Corp.
    Inventors: Jayant Ashokkumar, David W. Still, James D. Allan
  • Patent number: 7535772
    Abstract: Data paths (100 and 900) can be configured to accommodate two or four burst data sequences, with a data value being input/output each half clock cycle. A data sequence can be a fixed order or user-defined order depending upon a selected option. A data input path (100) can reduce power consumption with an enable signal (dinen) timed to activate after data input lines have settled values. A data output path (900) can access output data in a parallel fashion for subsequent output according to a burst sequence. Cycle latencies for such output data can include one clock cycle latency or one and a half-clock cycles. A data output path (900) can also accommodate various clocking modes, including: single clocking with a delay locked loop (DLL) type circuit enabled, single clocking with a delay locked loop (DLL) type circuit disabled, and double clocking, with a phase difference between an input clock and output clock of up to 180°.
    Type: Grant
    Filed: June 25, 2004
    Date of Patent: May 19, 2009
    Assignee: Cypress Semiconductor Corporation
    Inventors: Suresh Parameswaran, Thinh Tran
  • Patent number: 7528648
    Abstract: An apparatus, method and system are described for providing a low power replica biased regulated supply voltage without the size requirements of using a large resistor coupled between the source of a master transistor and ground. Instead, a source of a replica transistor diode may be biased with a bias voltage, and the gate and drain of the diode may be biased with a current bias. Additional descriptions provide the supply voltage without the size requirements of a resistor coupled between a source of one or more pass transistors and ground. Instead, the source of the pass transistor(s) may be biased with a “leaker” current.
    Type: Grant
    Filed: February 22, 2007
    Date of Patent: May 5, 2009
    Assignee: Cypress Semiconductor Corporation
    Inventor: Nandakishore Raimar
  • Patent number: 7526422
    Abstract: A system and a method for checking consistency of a lock-step process while debugging a microcontroller code. A host device copies a partially copies a production microcontroller in an ICE (in-circuit emulation) to form a virtual microcontroller. The virtual microcontroller and the microcontroller simultaneously and independently run a microcontroller code for debugging purposes. The microcontroller residing on a test circuit includes a first memory and the virtual microcontroller residing in the ICE includes a second memory. A host computer copies a content of the first memory and a content of the second memory in the host computer memory when the execution of the code is halted. Software in the host device compares the content of the first memory and the content of the second memory for consistency.
    Type: Grant
    Filed: November 13, 2001
    Date of Patent: April 28, 2009
    Assignee: Cypress Semiconductor Corporation
    Inventor: Craig Nemecek
  • Patent number: 7518420
    Abstract: A delay limit detect circuit can determine the delay of a current steering delay cell, like those utilized in a voltage controlled oscillator (VCO), by monitoring a current (ISENSE) that tracks a delay cell current (I2). When the monitored current (ISENSE) outside of a limit, a signal LIMIT can be activated. A monitored current (ISENSE) can be generated by a control replica circuit having the same circuit component types as a control circuit within a delay cell. Such limit detection can provide a way to prevent a ring VCO from entering a runaway state, particularly in cases where a maximum frequency can be reached before a maximum control voltage is reached.
    Type: Grant
    Filed: January 30, 2007
    Date of Patent: April 14, 2009
    Assignee: Cypress Semiconductor Corporation
    Inventor: Jonathon C. Stiff
  • Patent number: 7518916
    Abstract: A system and method for programming both sides of the non-volatile portion in a semiconductor memory is disclosed. The present invention erases and then programs the memory stacks in the non-volatile portion of an nvSRAM.
    Type: Grant
    Filed: December 22, 2006
    Date of Patent: April 14, 2009
    Assignee: Cypress Semiconductor Corporation
    Inventors: Jayant Ashokkumar, David W. Still, James D. Allan, John Roger Gill
  • Patent number: 7518434
    Abstract: A method and apparatus for power supply rejection in a reference voltage circuit using a variable resistance circuit.
    Type: Grant
    Filed: September 18, 2006
    Date of Patent: April 14, 2009
    Assignee: Cypress Semiconductor Corporation
    Inventors: Ryan Jurasek, Adam B. Wilson
  • Patent number: 7518534
    Abstract: Methods and systems for generating 10-bit control codes for use in 8-bit to 10-bit encoding are disclosed. Such control codes can have low subblock disparity (where subblocks include 6-bit and 4-bit blocks), limited run lengths when concatenated, limited run lengths within sub-blocks, meet minimal allowable cumulative disparity values at predetermined bit locations (not violate a transition matrix), and not form an aliased comma character sequence within a code, or when codes are concatenated with other codes or encoded data values. Preferably, new codes are added to existing 8B10B schemes with less than sixteen control codes to arrive at a control code set of at least sixteen.
    Type: Grant
    Filed: July 20, 2007
    Date of Patent: April 14, 2009
    Assignee: Cypress Semiconductor Corporation
    Inventor: Edward L. Grivna
  • Patent number: 7519101
    Abstract: Communication circuitry uses a combination of Pseudo-Noise (PN) coded and non-PN coded transmission periods to represent different data values. In one embodiment, a number of data values are encoded into a smaller second number of encoded ternary values. The Pseudo-Noise (PN) codes are transmitted representing some of the encoded ternary values and no transmitted PN codes represent other encoded ternary values. The throughput of spread spectrum radio systems is increased by representing data values in fewer spread spectrum time slots.
    Type: Grant
    Filed: December 7, 2004
    Date of Patent: April 14, 2009
    Assignee: Cypress Semiconductor Corporation
    Inventor: David G. Wright
  • Patent number: 7516280
    Abstract: A pulsed arbitration system has a partial-address coincidence detector with a partial-address collision flag as an output. An active global word line detector and disable pulse generator receives the partial-address collision flag as well as a decoded row address and an internal write pulse as an input, and generates a disable pulse for the interfering global word line of the colliding reading port.
    Type: Grant
    Filed: March 15, 2005
    Date of Patent: April 7, 2009
    Assignee: Cypress Semiconductor Corporation
    Inventor: Stefan-Cristian Rezeanu
  • Patent number: 7512075
    Abstract: A system (100) can update a network performance counter and include link layer (MAC blocks) devices (102-0 to 102-N) coupled in a daisy chain manner. A single performance counter (104) can serve all of the link layer devices (102-0 to 102-N), receiving statistics vectors from all link layer devices (102-0 to 102-N) and a vector enable signal from a last link layer device 102-N in the chain. A method (1200) for updating a performance counter according to such a daisy chain configuration is also disclosed.
    Type: Grant
    Filed: September 10, 2004
    Date of Patent: March 31, 2009
    Assignee: Cypress Semiconductor Corporation
    Inventors: Somnath Paul, Hamid Khodabandehlou
  • Patent number: 7511590
    Abstract: A differential crystal oscillator electronic circuit. Embodiments of the present invention include circuits comprising two substantially similar oscillator circuits. The oscillator circuits may be coupled to a common crystal or ceramic resonator. Embodiments of the present invention are especially well suited to implementation within integrated circuits where their superior common mode and supply rejection function beneficially in opposition to the naturally high coupling characteristics of integrated circuits. Further, by naturally furnishing differential signals, these low noise signals may be used directly by other differential circuits on an integrated circuit, without requiring additional single ended to differential conversion circuitry.
    Type: Grant
    Filed: August 21, 2002
    Date of Patent: March 31, 2009
    Assignee: Cypress Semiconductor Corporation
    Inventor: Mark Richard Gehring
  • Patent number: 7507944
    Abstract: A non-planar frame base for an image sensor.
    Type: Grant
    Filed: June 27, 2006
    Date of Patent: March 24, 2009
    Assignee: Cypress Semiconductor Corporation
    Inventors: Daniel Arnzen, Thurman John Rodgers
  • Patent number: 7504876
    Abstract: Disclosed is an improved substrate bias feedback circuit, and a method for operating the same.
    Type: Grant
    Filed: June 28, 2006
    Date of Patent: March 17, 2009
    Assignee: Cypress Semiconductor Corporation
    Inventors: Vijay Kumar Srinivasa Raghavan, Iulian Gradinariu
  • Patent number: 7504833
    Abstract: Disclosed is method for compensating for variation in the capacitance between multiple capacitive sensors. Prior to sensing operations, baseline capacitance values can be acquired for all sensors. A correction factor can be calculated based on such baseline values. During sensing operations (run-time), variations in capacitance from baseline values can be modified by appropriate correction factors. Sensitivity between sensors can thus be made more uniform.
    Type: Grant
    Filed: March 31, 2006
    Date of Patent: March 17, 2009
    Assignee: Cypress Semiconductor Corporation
    Inventor: Dennis Seguine
  • Patent number: 7505303
    Abstract: A system and method for disturbing an erased memory location structure in a non-volatile portion of a semiconductor memory is disclosed. The present invention applies a voltage to a first memory location of a non-volatile portion of the semiconductor memory that is in a programmed state and a second memory location of a non-volatile portion of the semiconductor memory that is in an erased state so as to keep the first memory location programmed and to transition the second memory location from a programmed state to an erased state.
    Type: Grant
    Filed: December 22, 2006
    Date of Patent: March 17, 2009
    Assignee: Cypress Semiconductor Corporation
    Inventors: Jayant Ashokkumar, David W. Still, James D. Allan