Abstract: A hub switch allows a high-speed USB peripheral or set of peripherals to be shared between multiple USB hosts. Multiple USB ports are configured to connect to different USB peripheral devices and USB hosts. Switching logic is located between at least some of the USB ports and USB logic. The switching logic selectively connects the USB peripheral devices to different selectable ones of the USB hosts.

Abstract: A method and apparatus to synchronize a boost signal. The apparatus includes a boost circuit and a synchronization circuit. The synchronization circuit is coupled to the boost circuit. The boost circuit generates an unsynchronized boost signal to boost a voltage signal from a first voltage to a second voltage. The synchronization circuit synchronizes the unsynchronized boost signal with a reference signal to generate a synchronized boost signal.

Abstract: In one embodiment, a method for constructing an application includes presenting to a user a list of possible elements for a logic expression. The possible elements may include one or more names of variables. The method further includes receiving a user selection of one or more elements from the list of possible elements, presenting the selected elements as part of the logic expression, and allowing the user to complete the logic expression using the selected elements and at least one logical operator.

Abstract: A system includes a control store memory populated with data path instructions indexable by control store addresses and jump addresses. The system further includes a control state machine to provide at least one control store address and at least one jump address to the control store memory, wherein the control store memory is configured to identify one or more data path instructions for both the control store address and the jump address.

Abstract: A high-speed redundancy circuit having redundant rows/blocks for replacing defective rows, columns and blocks. For row redundancy, an off-pitch encoder in conjunction with row control circuitry is used to disable defective rows while enabling non-defective rows. An off-pitch fuse is blown to enable redundant rows for a particular sub-array. Therefore, the enabled redundant row replaces the disabled defective row. For column/block redundancy, an encoder is used where appropriate off-pitch fuses are blown to enable the appropriate redundant blocks. Unlike row redundancy, the defective columns/blocks are not disabled. Instead when redundant blocks are enabled, the column/block control unit detects whether to transfer data to/from the redundant block/columns or block/columns corresponding to the defective columns. As a result of using off-pitch fuses the die size is reduced.

Abstract: A packet processing system including an encapsulator engine, and a packet pre-processor coupled to the encapsulator engine. The packet pre-processor calculates a variation between an input data rate and a pre-determined output data rate. The input data rate is based on a number of data read requests. The packet pre-processor compensates for the variation by modifying the number of data read requests.

Abstract: In one embodiment, the invention is an apparatus for assembling data for virtual concatenation. The apparatus includes an auxiliary memory having a set of storage locations for data. The apparatus also includes an external memory having a set of storage locations for data. The apparatus further includes a data assembler coupled to the auxiliary memory and the external memory. The data assembler is to read data of a virtual container from the external memory. The data assembler is also to store data of the virtual container in the auxiliary memory. The data assembler is further to determine if all data of the virtual container is present in the auxiliary memory. The data assembler is also to generate a set of addresses of the data of the virtual container in the auxiliary memory. The data assembler is further to read the data of the virtual container from the auxiliary memory. The data assembler is also to interleave the data of the virtual container.

Abstract: A phase locked loop circuit, system, and method of operation are provided. The phase-locked loop (PLL) includes a first PLL and a second PLL. The first PLL is nested inside the second PLL. According to one embodiment, the first PLL is coupled to the output of a surface acoustic wave (SAW) resonator, and includes first divider coupled within a feedback loop of the first PLL. The second PLL is coupled between an input of the overall PLL circuit, and output from the first PLL and the first divider. According to a second embodiment, the second PLL includes a SAW voltage-controlled oscillator (VCSO) and a second divider coupled to an output of the first PLL. Regardless of whether the first or second embodiments are contemplated, the nested first and second PLL circuits provide an agile, low phase noise, clock synthesizer and jitter attenuator hereof.

Abstract: One embodiment relates to a method of velocity prediction using a sensor array. Differential signals are obtained from the sensor array at multiple frame rates. A first velocity prediction is determined from the differential signals at a first frame rate, and a second velocity prediction is determined from the differential signals at a second frame rate. Another embodiment relates to an optical navigation apparatus which includes a sensor array, differential circuitry, driver circuitry, and a signal processing device. The driver circuitry is configured to drive the sensor array and differential circuitry so as to operate at multiple frame rates in an interleaved manner. The signal processing device is configured to compute a first velocity prediction from the differential signals at a first frame rate and to compute a second velocity prediction from the differential signals at a second frame rate. Other embodiments and features are also disclosed.

Abstract: A circuit for a pixel site in an imaging array includes a light-detecting element to convert incident light to a photocurrent and a reset transistor, operatively connected to the light-detecting element, to reset a voltage associated with the light-detecting element. The reset transistor hard resets the voltage associated with the light-detecting element and soft resets the voltage associated with the light-detecting element after the generation of the hard reset of the voltage associated with the light-detecting element. A pixel voltage of a column or row line is also measured by hard resetting the column or row line voltage to a first predetermined voltage; soft resetting the column or row line voltage to a first pixel voltage; hard resetting the column or row line voltage to a second predetermined voltage; soft resetting the column or row line voltage to a second pixel voltage; and determining a difference between the first and second pixel voltages, the difference being the measured pixel voltage.

Abstract: A circuit for a pixel site in an imaging array includes a light-detecting element to convert incident light to a photocurrent and a reset transistor, operatively connected to the light-detecting element, to reset a voltage associated with the light-detecting element. The reset transistor hard resets the voltage associated with the light-detecting element and soft resets the voltage associated with the light-detecting element after the generation of the hard reset of the voltage associated with the light-detecting element. A pixel voltage of a column or row line is also measured by hard resetting the column or row line voltage to a first predetermined voltage; soft resetting the column or row line voltage to a first pixel voltage; hard resetting the column or row line voltage to a second predetermined voltage; soft resetting the column or row line voltage to a second pixel voltage; and determining a difference between the first and second pixel voltages, the difference being the measured pixel voltage.

Abstract: A system, fan controller and method for enhanced alert notification. Embodiments provide an effective mechanism for utilizing system fans to create alert tones or messages, where fan speed differentials may be adjusted to alter the frequency of the fan interference sounds. As such, existing hardware can be used to reduce cost by producing audible alerts which may be heard above ambient noise in a room with one or more electronic systems. Further, the frequency of the interference sounds may be altered to more clearly identify one or more systems to which a fault pertains.

Abstract: A method and apparatus for a configurable device contacts. A logic value on an external contact of a device is read. The external contact is selectively coupled to one of two voltage rails dependent upon the logic value. The logic value on the external contact is sensed to determine whether the logic value changed after selectively coupling the external contact to one of the two voltage rails. Based on the whether the external contact changed logic values, it is determined whether the external contact is coupled to receive a last address bit of an address.

Abstract: A system comprises a system interface to receive one or more instruction sets from a microcontroller and to receive digital data to be processed. The system further comprises a controller that is reconfigurable according to the one or more instruction sets received by the system interface. The system further comprises a data path device to perform digital filtering operations on the digital data as directed by the controller according to the reconfiguration of the controller by the one or more instruction sets.

Abstract: A configurable analog to digital converter (ADC) includes a plurality of analog units to integrate an input signal. The analog units are coupled together to generate a plurality of discrete-time signals responsive to the input signal and are further coupled to a plurality of bus segments via a plurality of interconnect circuits. Each interconnect circuit is configured to selectively couple the analog units to any of the bus segments.

Abstract: A variable impedance sense (VIS) circuit (600) can detect and store an input offset value inherent in a sensing loop (620 and/or 622). According to a detected input offset polarity, a resulting impedance matching binary code can be adjusted to compensate for error that can be introduced by the input offset. The binary code can also be adjusted to compensate for additional error that can be introduced by dropping a least significant bit (LSB) of the code to reduce noise effects caused by the switching of the LSB.

Abstract: An embodiment of the present invention is directed to a method for processing a position signal. The method includes receiving a first position signal from a capacitive sensor and determining a proximity of the capacitive sensor to a connection of an array of capacitive sensors. The sensitivity of the capacitive sensor is then adjusted and a second position signal is received from the capacitive sensor. The second position signal may then be reported. The present invention facilitates more accurate readings from an array of capacitive sensors.

Abstract: System and method for optimizing the consumption of power while maintaining performance in capacitive sensor arrays. A limited sensing area is used to improve the update rate and sensitivity of a row/column array of capacitive sensors. According to one embodiment, a method is provided for scanning a plurality of capacitive sensors by: detecting a stimulus in the field of capacitive sensors, scanning the field of capacitive sensors to determine the position of the stimulus. Once the position of the stimulus is determined, a subsection of the field comprising window corresponding to the position of the stimulus remains activated while the remaining sensors in the field are deactivated.

Abstract: A method for integrated device testing can include the steps of: receiving wafer test data that identifies wafer test failures with the dice tested while part of a shared common substrate; receiving package test data that identifies test failures for at least a subset of the dice after the dice have been separated and assembled into different packages; identifying non-unique coverage test sets that include at least one wafer test or package test that generates failures that correlates with failures generated by another wafer test or package test for the same dice; and identifying unique coverage tests that include failures generated by wafer tests or package tests that do not correlate with failures generated by any other another wafer test or package test for the same dice.

Abstract: A correlator has a feedback circuit having a first input coupled to an incoming data stream, a second input and an output. A data register is to store an incoming data stream having a number of candidate bits, the data register having an output coupled to the second input of the feedback circuit. A code register is to store a known code having a predetermined number of code bits and a comparator is to compare a portion of the incoming data stream to a portion of the known code.