Abstract: A multiplexer circuit provided herein includes a plurality of pass devices coupled in parallel between a power supply and a ground supply. According to one embodiment, each pass device may include a first pair of transistors, which is coupled in series between the power supply and the ground supply, and a second pair of transistors, which is coupled to the first pair of transistors for controlling a current passed there through. In general, the second pair of transistors may be configured for increasing the amount of current passed through the first pair of transistors. For example, the second pair of transistors may utilize a bootstrapping effect to increase a pair of control voltages supplied to the gate terminals of the first pair of transistors. The increased control voltages function to over-drive the gate terminals of the first pair of transistors, thereby increasing the amount of current passed there through.

Abstract: A system includes a controllable voltage generator to generate a power supply voltage. The system also includes a system controller to determine a voltage level associated with the power supply voltage, and prompt the controllable voltage generator to generate the power supply voltage. The system includes a floating gate reference device to generate an absolute voltage reference based, at least in part, on the voltage level associated with the power supply voltage. The system can also include analog circuitry to perform one or more electrical operations responsive to the absolute voltage reference from the floating gate reference device.

Abstract: A system includes an analog-to-digital modulator to convert at least one analog input signal into at least one digital output signal. The system also includes a processing device to set an operational order and a quantization level of the analog-to-digital modulator. The analog-to-digital modulator converts the analog input signal into the digital output signal according to the operational order and the quantization level.

Abstract: A system and method for graphically displaying modules and resources within a chip design software application. The system and method provide a data driven model for matching the hardware resource requirements for an associated user module and the available hardware resources on an underlying chip. Databases are utilized to describe the hardware resource requirements which are dictated by the particular user module and the available hardware resources of a particular chip. The user module descriptive database can be updated in response to additional user modules being added or changes to the hardware resource requirements of existing user modules. The hardware description database can be updated in response to additional chips being added. Further, the graphical interface relates both a user module and the possible hardware resource.

Abstract: An optical sensor and method of using the same is provided for sensing relative movement between the sensor and a surface by detecting changes in optical features of light reflected from the surface. In one embodiment, the sensor includes a two dimensional array of photosensitive elements, the array including at least a first plurality of photosensitive elements arranged and coupled to sense a first combined movement along a first set of at least two non-parallel axes, and a second plurality of photosensitive elements arranged and coupled to sense a second combined movement along a second set of a least two non-parallel axes.

Abstract: A Programmable System on a Chip Hub (PHUB) is configured to enable master processing elements within the PHUB to simultaneously access peripherals on different busses. The master processing elements include a Central Processing Unit (CPU) interface configured to decode addresses received from a CPU and configure the PHUB to connect signaling from the CPU to one of the multiple busses associated with the address. A second one of the master processing elements is a Direct Memory Access Controller (DMAC) source engine configured to conduct Direct Memory Access (DMA) reads. A third one of the master processing elements is a DMAC destination engine configured to conduct DMA writes independently of the CPU interface.

Abstract: A system includes a plurality of datapaths, each having structural arithmetic elements to perform various arithmetic operations based, at least in part, on configuration data. The system also includes a configuration memory coupled to the datapaths, the configuration memory to provide the configuration data to the datapaths, which causes the datapaths to collaborate when performing the arithmetic operations.

Abstract: The circuit comprises a pulse width modulated (PWM) input signal, a resistor, an instrumentation amplifier, a filter and an analog to digital converter. The method of performing synchronization comprises sampling an analog signal and forming a digital data stream representing the signal, filtering the data stream to remove harmonics, measuring an approximate level of ripple in the data stream, detecting a change in the level of ripple, and based upon change in the level of ripple, determining if a stall has occurred.

Abstract: A circuit and method are provided herein for monitoring the status of a clock signal. In general, the method may include supplying a pair of clock signals to a clock monitor circuit, which is configured for monitoring a status of one clock signal relative to the other. The status indicates whether the frequency of the one clock signal is faster, slower or substantially equal to the frequency of the other clock signal. Once determined, the status may be stored as a bit pattern within a status register, which is operatively coupled to the clock monitor circuit. This enables the status to be read by detecting a logic state of one or more bits within the status register.

Abstract: A method of transmitting communications codes is used in spread spectrum communications systems. The method includes transmitting a first pseudo-noise code, and transmitting a second pseudo-noise code, wherein the second pseudo-noise code is a time-reversed version of the first pseudo-noise code. A device includes a first shift register to store a first code and a second register to store a second code in a time-reversed version. A comparison circuit then compares the two codes and a result is output.

Abstract: A method and system is provided for supplying power to a host via a USB port. The power is transmitted to the host using the standard VBUS and GND lines that are part of standard USB cables and connectors. The peripheral device includes a special USB descriptor block. During the standard enumeration process, the host reads this USB descriptor block and recognizes that the device can provide power to the host. A set feature command is used to start the power transmission to the host.

Abstract: A circuit for a pixel site in an imaging array includes a light-detecting element to convert incident light to a photocurrent and a reset transistor, operatively connected to the light-detecting element, to reset a voltage associated with the light-detecting element. The reset transistor hard resets the voltage associated with the light-detecting element and soft resets the voltage associated with the light-detecting element after the generation of the hard reset of the voltage associated with the light-detecting element. A pixel voltage of a column or row line is also measured by hard resetting the column or row line voltage to a first predetermined voltage; soft resetting the column or row line voltage to a first pixel voltage; hard resetting the column or row line voltage to a second predetermined voltage; soft resetting the column or row line voltage to a second pixel voltage; and determining a difference between the first and second pixel voltages, the difference being the measured pixel voltage.

Abstract: A parallel data transmission test system can include a receiver section (100) having input selector circuits (104-O to 104-N) that provide a received test data to logic adjust circuits (106-O to 106-N) that “logically align” multiple incoming test values to remove intentionally introduced logic difference (e.g., inversion) with respect to one another. Result combining circuit (108) can logically combine output data values and provide a resulting sequence to a pattern sequence test circuit (110).

Abstract: A method of forming structures comprises depositing silicon nitride films simultaneously on a plurality of substrates at a first temperature, and heating the silicon nitride films at a temperature greater than the first temperature.

Abstract: A self-calibration system includes a variable current source to generate a default source current for charging a capacitive load, and a load charge calibrator to detect a voltage associated with the capacitive load when charged by the default source current, and to generate a current control feedback according to the detected voltage and a desired charged voltage of the capacitive load, the current control feedback to indicate to the variable current source a charge current capable of charging the capacitive load to the desired charged voltage.

Abstract: A system includes a bandgap temperature sensor to generate multiple base-emitter voltages. The system also include a controller to detect the base-emitter voltages generated by the bandgap temperature sensor and to generate a bandgap reference voltage according to the multiple base-emitter voltage signals, the bandgap reference voltage having a voltage level that remains substantially constant relative to environmental temperature variations.

Abstract: Embodiments of the invention relate to a configurable LCD driver system having a plurality of configurable LCD drivers. Each LCD driver may be configured as a common or segment driver by selecting a drive voltage from an appropriate set of drive voltages associated with a common or segment driver in accordance with certain parameters, such as whether a user may configure the LCD driver as a common driver or segment driver, a multiplex ratio, and/or bias ratio of an LCD panel. The drive time and drive strength associated with the LCD driver may also be configurable. The selected drive voltage may be provided to a drive buffer to output an LCD drive voltage waveform for driving one or more segments or pixels in an LCD panel. A memory may store appropriate display data for both the segment and common drivers to control the output drive capability of the LCD driver.

Abstract: A liquid crystal display (LCD) driving system includes a reference voltage generator to generate a plurality of reference voltages. The LCD driving system also includes a plurality of drive buffers to generate drive voltages according to at least one of the reference voltages, and to drive at least a portion of a liquid crystal display to present data according to the drive voltages.

Abstract: An array of universal digital blocks include programmable logic device sections that have uncommitted user programmable logic functions and structural datapath sections that include dedicated and highly configurable arithmetic operators. A routing channel matrix programmably connects to different programmable logic device sections and datapath sections in the different universal digital blocks.

Abstract: Different functional elements are all located on a same integrated circuit wherein at least one of the functional elements comprises a micro-controller. Configuration registers or configuration memory in the integrated circuit store configuration values loaded by the micro-controller. Connectors are configured to connect the integrated circuit to external signals. A system level interconnect also located in the integrated circuit programmably connects together the different functional elements and different connectors according to the configuration values loaded into the configuration registers.