Abstract: A liquid crystal display (LCD) driving system includes a reference voltage generator to generate a plurality of reference voltages. The LCD driving system also includes a plurality of drive buffers to generate drive voltages according to at least one of the reference voltages, and to drive at least a portion of a liquid crystal display to present data according to the drive voltages.

Abstract: An array of universal digital blocks include programmable logic device sections that have uncommitted user programmable logic functions and structural datapath sections that include dedicated and highly configurable arithmetic operators. A routing channel matrix programmably connects to different programmable logic device sections and datapath sections in the different universal digital blocks.

Abstract: A display interface buffer includes a general purpose memory to store data capable of being displayed on a panel, a plurality of display drivers to receive data from the general purpose memory, each of the display drivers to drive a different portion of the panel with the data, and processor or a direct memory access controller to access data in the general purpose memory and to provide the data to the display drivers for presentation on the panel.

Abstract: An apparatus includes a configuration memory coupled to one or more structural arithmetic elements, the configuration memory to store values that cause the structural arithmetic elements to perform various functions. The apparatus also includes a system controller to dynamically load the configuration memory with values, and to prompt the structural arithmetic elements to perform functions according to the values stored by the configuration memory.

Abstract: Embodiments of the invention relate to a method and system for accessing a set of parallel registers orthogonally. A decoder may be used to select a particular row or column of the set of parallel registers to perform register operations in a parallel fashion corresponding to the selected row or in an orthogonal fashion corresponding to the selected column. Thus, when a particular row is selected, a register operation may be carried out for each bit of the selected row to produce a parallel register output, such as by reading/writing each bit of the selected row to a parallel register. On the other hand, when a particular column is selected, a register operation may be carried out for each bit of the selected column, such as by reading/writing each bit of the selected column to an orthogonal register. The orthogonal register access allows for fast and efficient access to a particular bit in the set of parallel registers.

Abstract: Embodiments of the invention relate to a method and apparatus to drive non-resistive loads. The non-resistive load driver may include two or more drivers, such as a high-drive circuit and a low-drive circuit, to drive rail-to-rail output voltages and to stabilize the output voltages at a substantially constant level. The high-drive circuit may drive the output voltage of the non-resistive load driver to a threshold level, whereas the low-drive circuit may modify the output voltage of the non-resistive load driver to approximate an input voltage of the non-resistive load driver, and compensate any leakage associated with the non-resistive loads to provide a substantially constant output voltage. The low-drive circuit consumes less current than the high-drive circuit. The non-resistive load driver consumes less power and use less chip space.

Abstract: Embodiments of the invention relate to a method and apparatus to reduce power consumption in a passive matrix LCD driver circuit by using a plurality of drive buffers and active power management of sub-blocks in the passive matrix LCD drive circuit. Each drive buffer may operate in a first phase, which may include a high-drive mode to drive an LCD voltage to a threshold voltage level and a low-drive mode to modify the LCD voltage to approximate an input voltage of the drive buffer, and to maintain a constant LCD voltage level. The low-drive buffer consumes less current than the high-drive buffer, thus reducing power consumption. The drive buffer may also operate in a second phase, also a no-drive mode, in which the drive buffer and the bias voltage generator may be completely turned off, to further reduce power consumption. The drive buffer may be used to drive capacitive loads, as well as partially-resistive loads and inductive loads.

Abstract: A memory device includes a memory array having a plurality of memory cells arranged in a row-column format, where the memory array is configured to designate at least one of the memory cells as a test memory cell. The memory system also includes a sense amplifier to read the test memory cell and to evaluate a validity of the memory array responsive to reading the test memory cell.

Abstract: A system comprises a temperature sensor generate multiple base-emitter voltage signals by sequentially providing various currents to a transistor, and a system controller to determine a differential voltage signal according to the multiple base-emitter voltage signals, the differential voltage signal proportional to an environmental temperature associated with the transistor.

Abstract: A system includes at least one word line decoder to select word lines to activate, and a memory cell array having a plurality of memory cell devices to store data received through one or more write bit lines. At least one of the memory cell devices including a memory cell to store data received over one or more write bit lines, and a sensing inversion device coupled to the memory cell and word lines. The sensing inversion device can read data stored by the memory cell and provide the read data to one or more read bit lines when at least one of the word lines is activated for read operations.

Abstract: A universal serial bus controller pre-generates and stores a subset of USB commands in a memory, the pre-generated commands available for transmission to at least one USB peripheral device over universal serial bus, and transfers at least one command from the subset of pre-generated commands stored in the memory to the USB peripheral device over the universal serial bus. The universal serial bus controller may receive a response to the transferred command from the USB peripheral device over the universal serial bus, and send an acknowledgment packet to the USB peripheral device over the universal serial bus responsive to receiving the response from the USB peripheral device.

Abstract: A phase locked loop circuit includes an oscillator, a dividing circuit coupled to the oscillator having a controllable dividing factor, and a rangefinder circuit coupled to the dividing circuit. The rangefinder circuit is configured to control the dividing factor in response to an operating characteristic of the phase-locked loop circuit.

Abstract: A method and system for initiating the oscillation of a crystal that controls a crystal oscillator by applying an initiating pulse to said crystal. The initiating pulse having a pulse width less than one half the periodicity of said crystal.

Abstract: Phase-locked loop fast lock circuit and method are described. The apparatus including a voltage controlled oscillator, a control loop filter having a capacitor and at least one resistor, and first and second control elements coupled with the control loop filter. The first control element may include a charge pump coupled to a node between the resistor and the capacitor of the control loop filter, and a frequency detector coupled to the charge pump.

Abstract: A signal processing method is provided for sensing movement of an optical sensor relative to a surface. Generally, the method includes steps of: (i) generating sets of signals responsive to motion along each of a first, second, and third direction, the directions not necessarily all different, (ii) combining the sets of signals to generate a first complex signal for each direction at a first time; (iii) combining the sets of signals to generate a second complex signal for each direction at a second time subsequent to the first time; (iv) computing a third complex signal for each direction wherein each of the third complex signals is a predicted value for each of the second complex signals, the predicted signal depending on a number of values representing distance moved; and (v) determining optimum values of the values representing distance moved by minimizing differences between the second and third complex signals.

Abstract: A multi-node time division multiplexing (TDM) system is disclosed. The improved method and apparatus utilizes an asynchronous synchronization packet (ASP) to synchronize the timing in all the nodes of the system. In some embodiments, the ASP also maps the time slots in a data frame to particular nodes. The ASP is sent at the start of each data frame to all the nodes in the system and each node synchronizes itself to the time of receipt of the ASP, thus establishing frame-based timing for all the nodes. Additionally, the ASP can contain a table that maps the data frame time slots to the nodes in the system.

Abstract: A phase shift apparatus, system and method are described herein for synchronizing output signals upon one or more components of a synchronous system. In one embodiment, the phase shift apparatus may be implemented as a clock generation circuit, which is configured to provide synchronous clocking signals to one or more components of the synchronous system. In another embodiment, the phase shift apparatus may be implemented as a data interface circuit, which is configured to provide error-free data transmission within a synchronous system. In either embodiment, the phase shift apparatus is configured to shift the plurality of signals by programmable first phase shift amounts prior to shifting the plurality of signals by programmable second phase shift amounts. As such, the phase shift apparatus is adapted to substantially eliminate clock skew, data skew and/or jitter, which may otherwise adversely affect the synchronous system.

Abstract: A circuit and method for providing a periodic clock signal, such as a high frequency clock signal. In one example, the circuit may include a phase locked loop circuit having a voltage controlled oscillator, the voltage controlled oscillator having a voltage input, a calibration input, and a clock signal output; and a logic circuit for dynamically calibrating an operating frequency of the phase locked loop during operation of the phase locked loop. In one embodiment, the logic circuit may compare an input voltage into the voltage controlled oscillator against a reference voltage, and if the input voltage is lower than the reference voltage, the logic circuit decreases the operating frequency of the phase locked loop circuit. The logic circuit may compare an input voltage into the voltage controlled oscillator against a reference voltage, and if the input voltage is higher than the reference voltage, the logic circuit increases the operating frequency of the phase locked loop circuit.

Abstract: A system and a method for checking consistency of a lock-step process while debugging a microcontroller code. The virtual microcontroller and the microcontroller simultaneously and independently run a microcontroller code. The microcontroller includes a first memory and the virtual microcontroller residing in the ICE includes a second memory. A host computer copies a content of the first memory and a content of the second memory in the host computer memory when the execution of the code is halted. The host device compares the content of the first memory and the content of the second memory for consistency. In case of a disparity between the content of the first memory and the content of the second memory, a user traces the execution of the code in a trace buffer residing in the ICE and debugs the faulty code accordingly.

Abstract: A memory architecture and a method of operating the same can provide a substantially constant data valid window (DVW) irrespective of a temperature for the memory device. Generally, a memory device can receive an access request, determine a temperature of the memory device, and switch a number of delay elements in an output buffer in response to the temperature of the memory device. In one embodiment, a memory device can have a multi-stage input-output (I/O) buffer and an automatic temperature compensated circuit that samples a temperature of the memory and then switches a number of delay elements in the I/O buffer into a data path between the memory and the output to provide a substantially constant DVW over changes in temperature.