Abstract: In an embodiment, a signature area and virtual keypad, among other display elements, are displayed in more than one location on a touch screen display. As a result, wear and tear may be strategically distributed evenly across the touch screen, instead of isolated to fixed locations, thus increasing the touch screen's useful lifetime. Display degradation is detected in a novel embodiment from physical parameters that are conventionally used for the touch screen's touch sensitivity. By detecting the display degradation according to display location, display elements can be strategically located to enhance the life of the touch screen.

Abstract: An imager includes a two-dimensional array of photosensors, each photosensor having a center point. A non-telecentric lens is positioned over the two-dimensional array of photosensors, and a two-dimensional array of microlenses is positioned over the two-dimensional array of photosensors. Each microlens is associated with a corresponding photosensor, and each microlens has a center point. A color filter array is positioned over the two-dimensional array of photosensors. The color filter array includes a plurality of color filter areas. Each color filter area is associated with a corresponding photosensor and has a center point. A layer of transmissive apertures is further positioned over the two-dimensional array of photosensors. Each aperture is associated with a corresponding photosensor and having a center point. The microlens is positioned over the corresponding photosensor such that the center point of the microlens is offset from the center point of the corresponding photosensor.

Abstract: In one embodiment, an integrated circuit includes a serial link interface configured to send and receive data over a serial bus both during normal operation and during scan tests. The integrated circuit may include data routing circuitry for transferring data between the serial link interface and a scan chain during a scan test, and for transferring data between the serial link interface and a core logic circuit of the integrated circuit, without going through the scan chain, during normal operation. Scan data may be generated and analyzed by a tester integrated circuit coupled to the integrated circuit over the serial bus.

Abstract: A test circuit can test a status of a group of non-volatile elements. A current flowing to the group of non-volatile elements can be compared against a reference value. If the current is determined to be outside of a predetermined range, the non-volatile elements can be determined to be programmed. In particular embodiments, non-volatile elements can be sections of differential one-time programmable anti-fuse latch memory elements.

Abstract: A method of making a semiconductor structure includes etching an isolation oxide. The isolation oxide is in a substrate, a gate layer is on the substrate, a patterned metallic layer is on the gate layer, and a first patterned etch-stop layer is on the metallic layer.

Abstract: A method for emulating and debugging a microcontroller. In one embodiment, an event thread is executed on an emulator that operates in lock-step with the microcontroller. Event information is sampled at selected points. Trace information is also recorded at the selected points. As such, the event information and trace information are effectively pre-filtered. Accordingly, it is not incumbent on a designer to read and understand the event and trace information and sort out the information that is of interest. Instead, this task is essentially done automatically, helping the designer and reducing the probability of error. Furthermore, because only selected event and trace information is recorded, the resources of the in-circuit emulator system are not taxed.

Abstract: A method and test circuits for measuring skew between two circuit blocks of an integrated circuit. A first data signal is propagated through a first circuit block and a first clock signal is propagated through a second circuit block. The first data signal is latched synchronized to the first clock signal after propagating the first data and clock signals. The first data signal is time shifted relative to the first clock signal until the first data signal is no longer validly latching. A second data signal is propagated through the second circuit block and a second clock signal is propagated through the first circuit block. An inversion of the second data signal synchronized to an inversion of the second clock signal is latched. Then, the second data signal is time shifted relative to the second clock signal until the inversion of the second data signal is no longer validly latching.

Abstract: A synchronous multi-port memory including a plurality of ports coupled with a memory array, each of the plurality of ports including a delay stage to delay a memory access while a memory access arbitration is performed. The synchronous multi-port memory may also include selection logic coupled with the plurality of ports and the memory array to arbitrate among a plurality of contending memory access requests, to select a prevailing memory access request and to implement memory access controls.

Abstract: In one embodiment, the invention is an apparatus. The apparatus includes a network processor interface suitable for coupling to a network processor. The apparatus further includes a central processor interface suitable for coupling to a central processor. The apparatus also includes a protocol determination logic block to determine a protocol type of data in a packet and steer the packet to either the central processor interface or the network processor interface based on the protocol type of data.

Abstract: An electronic containment battery includes a battery section and an electronic section that together form a standard battery form factor that allows insertion into conventional electronic devices. The electronic section can include Radio Frequency (RE) circuitry that enables electronic operations in the electronic containment battery to be communicated or controlled wirelessly.

Abstract: We describe an apparatus including a plurality of sensing elements, a conductive layer, and a compressive layer interposed between the plurality of sensing elements and the conductive layer. The conductive layer can include a plurality of segments. A user applies a force to an actuator positioned over the conductive layer. The actuator changes a capacitance of at least one capacitor formed by at least one of the plurality of sensing elements, the conductive layer (at least one segment), and the compressive layer by reducing the distance between the at least one of the plurality of sensing elements and the conductive layer responsive to the applied force. The device measures and calculates a magnitude and direction of the force by measuring the change in the capacitance.

Abstract: Embodiments of the invention are generally directed to a high-speed differential energy difference integrator (EDI) for adaptive equalizers. In an embodiment, the EDI includes two differential full-wave rectifiers providing differential outputs that are cross-coupled to the inputs of an integration capacitor. In one embodiment, the active areas of the transistors of the differential full-wave rectifiers are substantially the same.

Abstract: A method and system for cycle slip framing is disclosed. The method includes receiving an asynchronous signal and generating a synchronous pulse after receiving the asynchronous signal. The method further provides that the synchronous pulse be used to affect a bit slip that results in the moving of a character frame in the recovered data of a deserializer. According to one embodiment of the invention, the moving of the character frame is prompted by a single control signal of a clock divider circuit which causes the removal of a single clock cycle of a clock signal supplied to said deserializer.

Abstract: Disclosed herein is a current sense amplifier (ISA) circuit with increased speed, less insensitivities to process variation, better stability and improved output signal swing. According to one embodiment, the ISA circuit described herein may include a pair of output nodes and a first pair of load transistors, each coupled between a different one of the output nodes and ground for pulling the output nodes down to a first voltage value at the beginning of a sense cycle. In addition, a pulse generation circuit is included for activating the first pair of load transistors at the beginning of the sense cycle and deactivating the first pair of load transistors once the first voltage is reached. When activated, the first pair of load transistors provide a relatively low resistance current path between the output nodes and ground. This decreases the output node discharge time and increases the overall speed of the sense amp without compromising circuit stability and output swing.

Abstract: A system and method are provided for built-in-self test of any bits that have slipped from their appropriate positions within a frame character clock cycle. If a bit has slipped, then the built-in-self test mechanism can also implement either a clock generation stretch operation or a barrel shift operation to readjust the frame boundary output from a receiver with a 1-to-N deserializer. A pseudo-random bit sequence can be generated having the same logic value in both the receiver and transmitter, where the output of the deserializer which receives the transmitted bits is compared bit-by-bit with the receiver-generated bits as part of the built-in-self test mechanism. If a bit is determined to have been slipped, then error correction occurs with aliasing and phase jitter in mind.

Abstract: A pixel structure is described, comprising at least two selection switches coupled in series to improve the yield of the pixel. Also an array comprising such pixel structures logically organized in rows and columns is described, as well as a method for selecting a row or column of pixel structures in such an array.

Abstract: An improved clock recovery system, phase-locked loop, and phase detector are provided as well as a method for generating charge pump signals. The clock recovery system includes a phase-locked loop. The phase-locked loop includes a phase detector and a voltage-controlled oscillator. The phase detector generates pump signals that change linearly with respect to differences between phases of an incoming signal and a clocking signal. The oscillator is coupled to receive the pump signals and produce a clocking signal at a frequency not exceeding the frequency of the incoming signal. For example, the oscillator can produce clocking signals at one-half the frequency of the incoming signal, where the incoming signal is preferably a maximum bit rate of a data signal from which the clock signal is recovered. The phase detector can include a first flip-flop and second flip-flop.

Abstract: An apparatus for measuring energy usage. The apparatus can include an amplifier having a plurality of gain stages and the amplifier can be for receiving an input signal. The apparatus can also include an analog-to-digital converter that is coupled to the amplifier. Furthermore, the apparatus can include a scaling adjustment module that is coupled to the analog-to-digital converter. Additionally, the apparatus can include a gain control module coupled to the analog-to-digital converter.

Abstract: A frequency synthesizer is provided having a fractional-N control circuit and method. The control circuit can operate as having a modulator that selectively applies any fractional ratio to a frequency divider within, for example, a feedback loop of a PLL. The modulator can be a delta-sigma modulator or any sequential state machine that can be implemented as the control circuit, and can select amongst a plurality of vector values. The vector values can be spaced relatively close to each other, and the incoming present vector values can each be added to a value chosen from the immediately preceding set of potential values. The selector circuit chooses from among the present set of vector values depending on whether the sum is nearest a target value. The sum nearest the target value is, therefore, selected as the present vector value, and the process is repeated in time for each vector value having a corresponding P value to form a pattern of P values sent to the divider of the PLL.

Abstract: An architecture for an improved non-volatile memory device supporting multiple memory interface options is disclosed herein. In one embodiment, the improved memory device includes a magnetic random access memory (MRAM) array and at least one memory interface block, which is configured for accessing a different type of memory array other than the MRAM array. A smart MRAM interface block is also included and coupled between the plurality of memory interface blocks and the MRAM array. The smart MRAM array is configured for accessing the MRAM array using commands intended for the MRAM array, as well as commands intended for the different type of memory array. A method for operating the improved non-volatile memory device is also disclosed herein.