Abstract: In one embodiment, a first transistor is configured to switch ON to discharge accumulated charges on an interconnect line during a metallization process. This advantageously protects a second transistor, which is coupled to the interconnect line, from charge buildup. The gate of the first transistor may be coupled to the interconnect line by way of a coupling capacitor. The gate of the first transistor may remain floating during the metallization process, and subsequently coupled to ground at a topmost metal level. The metallization process may be physical vapor deposition, for example.

Abstract: A method for multi-bit de-skewing of parallel bus signals is disclosed. The method includes receiving data comprising a multi-bit word and a training pattern. After a first control word of the training pattern is detected, the number of bits needed to de-skew each data bit of a multi-bit data word in each bit-line of a parallel bus is calculated. The number of bits needed to de-skew each data bit of a multi-bit data word in each bit-line of the parallel bus is transmitted to a bit delay line. The system then outputs a de-skewed data word.

Abstract: A voltage-to-current converter circuit is disclosed. In one embodiment, the present invention includes a first metal oxide semiconductor field effect transistor (MOSFET) stage operable in a low to medium power range. The present invention also includes a second MOSFET stage operable in a medium to high power range. An additive circuit is utilized to add the contributions of both the first MOSFET stage and the second MOSFET stage. A subtractive circuit is further used to subtract either the first MOSFET stage or the second MOSFET stage when both the first MOSFET stage and the second MOSFET stage are operating in the medium power range and outputting current in a voltage-to-current converting circuit.

Abstract: A method and system for a reject management protocol within a back-end IC manufacturing process. In one method embodiment, the present invention implements a tracking process for a die-strip. The present invention also maintains an electronic die-strip map database, and utilizes the tracking process to update the electronic die-strip map database as the die-strip moves in an in-line fashion from one sub-station to another within the manufacturing process. Information used to update the database can originate from one or more automated visual camera systems used for quality assurance. In so doing, the present invention categorizes the die on the die-strip based on information maintained by the electronic die-strip map database. This information can be used for die sorting and for die rejection. In one embodiment, an identifying code is placed on each die strip that can automatically identify the die-strip using the automated camera systems.

Abstract: In one embodiment, an interconnect line on one level of an integrated circuit is electrically coupled to another interconnect line on another level. The two layers of interconnects may be coupled together using a via. To reduce capacitance between the interconnect lines, an air core is formed between them. The air core may be formed by using a chemistry that includes a noble gas fluoride to etch a sacrificial layer between the interconnect layers.

Abstract: A replica biased voltage regulator circuit (100) is disclosed that provides high frequency response via local positive feedback and low frequency response via a negative feedback loop. A voltage regulator circuit (100) can include current conveyor (106) that essentially forces an output voltage (Vload) to follow a replica voltage (Vrep). An operational amplifier (102) can provide negative feedback by controlling current supplied to the current conveyor (104) based on a comparison between a reference voltage (Vref) and the replica voltage (Vrep).

Abstract: An apparatus is provided that includes a wafer examination stand configured to securely receive a wafer carrier. In addition, the apparatus may include a measurement device suspended above stand. In some cases, the stand may include a means for positioning the wafer carrier relative to the measurement device such that a portion of the measurement device is directly above the wafer carrier in a first predetermined position and directly above the microelectronic wafer in a second predetermined position. In any case, the stand may be used for the examination of a microelectronic wafer for any circumstance in which the wafer is placed within a wafer carrier ring. For example, the stand may be used for, but not limited to, measuring the protrusion of a microelectronic wafer relative to a carrier ring. Consequently, a method for measuring a protrusion of a microelectronic wafer relative to a carrier ring is also provided.

Abstract: The present invention discloses a method and system of generating and delivering a high voltage signal without latch-up hazards and without incurring a voltage drop due to the threshold of the switching element. The utilization of NMOS elements when switching a high voltage signal may remove latch-up hazards. Switching of the high voltage signal may be accomplished without incurring a voltage drop in the signal. With multiple transistors, switching of a high voltage signal in accordance with the present invention may provide an output driven to a destination circuit on each phase wherein clock cycles may be overlapping and non-overlapping.

Abstract: A circuit for establishing frequency and phase alignment of clock signals across a domain of analog blocks coupled in a single integrated circuit. Different analog functions are implemented by selectively and electrically coupling different combinations of analog blocks. The analog blocks may be arrayed in a number of columns. The circuit is coupled to the analog blocks to supply a synchronized clock signal to all of the analog blocks in a combination of blocks, even when the blocks are in different columns. The circuit allows the frequency of the clock signal to be changed dynamically depending on the analog function to be achieved. The circuit also establishes phase alignment when a frequency change occurs.

Abstract: A plurality of arbitration devices is hierarchically coupled and has a plurality of child devices and at least one parent device. Each of the plurality of arbitration devices is operable to store a previous arbitration winner. In addition, the plurality of arbitration devices is operable to generate a request-out signal based on a plurality of request-in signals, and is operable to generate a select-out signal from a select-in signal, a plurality of request-in signals and from the previous arbitration winner. The request-out signals of the plurality of child devices are coupled to request-in signals of their respective parent devices and select-in signals of the child devices are received from select-out signals of the respective parent devices. Access is granted by a select-out signal from a device of the plurality of arbitration devices that resides at the lowest level of the system.

Abstract: According to one embodiment, an integrated circuit (100) includes a programmable portion (102) and a communication portion (104). A programmable portion (102) may include logic circuits that are configurable by a user. A communication portion (104) may include one or more circuit blocks designed to perform predetermined serial data communication functions. According to one embodiment, a communication portion (104) may include a block converter (218) that can encode/decode input data words into output data words, and a scrambler circuit (220) for scrambling/de-scrambling data according to a predetermined scrambling polynomial value. Different scrambling polynomial values may be selected from an operation control store (206) to provide a variety of different scrambling/de-scrambling functions.

Abstract: A wireless peripheral controller connects multiple wireless game controllers to a game console across a communication port. A connector simulates the appearance of connecting a device to another communication port. Upon detecting the connection event, the game console queries the communication port associated with the connection event. A bus reset detector alerts the wireless peripheral controller. The alerted wireless peripheral controller signals the game console through the original communication port with the appropriate configuration instructions to obtain a unique device address for an additional wireless game controller. Using the unique device addresses, the wireless peripheral controller receives and responds to traffic intended for other communication ports through the original communication port.

Abstract: A method and apparatus for supplying auxiliary power to a peripheral is disclosed. The method includes supplying power from a first USB port of a host device to an input USB port of a USB hub device, supplying power through a downstream USB port of the USB hub device for use by a downstream USB device, supplying auxiliary power through a power output port of the USB hub device for use by a peripheral device that is coupled to an upstream port and supplying power from a second USB port of the host device to the peripheral device. The power received by the peripheral device is sufficient for its operation.

Abstract: A programmable serial interface device. The device generally comprises a programmable logic device and another die mounted to an assembly apparatus. The programmable logic device may comprise (i) a plurality of logic block clusters and (ii) a plurality of routing channels configured to interconnect said logic block clusters. The die may comprise a first communication channel (i) configured to convert between a first serial data signal and a first parallel data signal and (ii) coupled to a first of the routing channels to exchange the first parallel data signal with at least one of the logic block clusters.

Abstract: A circuit having a process, voltage, and temperature (PVT) invariant delay element is disclosed. In one embodiment, the present invention includes a first and second operational transconductance amplifier (OTA), a first and second switched capacitor driven by a clock, and a first and second clock-controlled switch. In addition, the present invention includes a trip inverter, a delay inverter, and a plurality of transistors. In so coupling the first and second OTA, the first and second switched capacitor, the first and second clock-controlled switch, the trip inverter, the delay inverter, and the plurality of transistors, a circuit having a PVT invariant delay element is provided.

Abstract: In one embodiment, a passivation level includes a low-k dielectric. The low-k dielectric helps lower the capacitance of a metal line in a last metal level, which may be just below the passivation level. In another embodiment, the metal line is relatively thick. This helps lower the metal line's resistance and resulting RC delay.

Abstract: A voltage trim circuit, in accordance with one embodiment of the invention, includes an operational amplifier, a transistor, a voltage divider and a bias current circuit. The operational amplifier is coupled to an input. The transistor is coupled to the operational amplifier and a first potential. The voltage divider circuit is coupled to the operational amplifier, the transistor and an output. The bias current circuit is coupled to the voltage divider circuit and a second potential. The voltage divider generates an output voltage as a function of a selectable divider ratio and provides a substantially constant feedback path to the operational amplifier. The bias current circuit provides for selectively adjusting a load resistance of the transistor to maintain a substantially constant load current through the transistor.

Abstract: An apparatus comprising a first circuit configured to generate (i) a pump up signal in response to a reference signal and a reset signal and (ii) a pump down signal in response to an input signal and said reset signal and a second circuit configured to (i) generate said reset signal in response to said pump up signal and said pump down signal.

Abstract: The invention provides a method and system for lookup of message header information that has the advantages of low-power, speed, and flexibility. The invention uses a sequence of pipelined on-chip memories, each having only a portion of the header information intended for lookup. Each one of the on-chip memories simultaneously performs a lookup on a portion of the header information, allowing embodiments of the invention to operate on multiple messages worth of header information substantially simultaneously. The invention uses a novel data structure for recording destination addresses in the sequence of on-chip memories, having the property that moving information about destination addresses, or otherwise responding to changes in network topology is flexible, while at the same time maintaining relatively dense usage of the on-chip memories.

Abstract: An apparatus configured to extract in-band information or skip extraction of the in-band information and perform a look ahead operation. The apparatus may be configured to switch between the extraction and the skipping of the extraction.