Abstract: The invention provides a method and system for lookup of message header information that has the advantages of low-power, speed, and flexibility. The invention uses a sequence of pipelined on-chip memories, each having only a portion of the header information intended for lookup. Each one of the on-chip memories simultaneously performs a lookup on a portion of the header information, allowing embodiments of the invention to operate on multiple messages worth of header information substantially simultaneously. The invention uses a novel data structure for recording destination addresses in the sequence of on-chip memories, having the property that moving information about destination addresses, or otherwise responding to changes in network topology is flexible, while at the same time maintaining relatively dense usage of the on-chip memories.

Abstract: A method and a system are provided for removing matter adhered to such a polishing pad. In particular, a polishing system is provided which is adapted to remove matter adhered to a polishing pad during a polishing process of a semiconductor topography. The polishing system may include a polishing pad and a spray element, which is preferably adapted to spray a pressurized fluid upon the polishing pad to remove matter adhered to the pad. In addition, a spray element is provided which may be adapted to be positioned within a polishing system. Such a spray element may be adapted to remove matter adhered to a polishing pad within the system by spraying a pressurized fluid upon the polishing pad. In addition, methods for cleaning a polishing pad during a polishing process and polishing multiple semiconductor topographies using the systems described herein are provided.

Abstract: A circuit for discharging a high voltage signal to a supply voltage line. In one embodiment, the circuit includes a first switch receiving the high voltage signal; a second switch having an input coupled with the output of the first switch; and a third switch having an input coupled with the output of the second switch and having an output coupled with the supply voltage line. In this embodiment, the high voltage signal discharges to the supply voltage line when the first, second, and third switches are on. The circuit may include a fourth switch for clamping the high voltage signal to ground. The fourth switch may have a control coupled with the output of the first switch along a discharge path such that when the high voltage signal is discharging and approaches a voltage level of approximately ground, the fourth switch automatically turns on and clamps the high voltage signal to ground level.

Abstract: The present invention is a high speed serial memory interface system and method that facilitates efficient communication of information between a system controller operating at a relatively high speed serial communication rate and a memory array operating at a relatively slow speed serial communication rate. In one embodiment the present invention is a high speed serial memory interface system with an information configuration core for coordinating proper alignment of information communication signals, a system interface for communicating with a system controller, and a memory array interface for communicating with a memory array. A memory module array for storing information and a high speed serial memory interface system for providing interface configuration management are integrated on a single substrate.

Abstract: The present invention is an efficient system and method for cascading optical switches. A plurality of cascaded optical switches form a cascaded optical switch fabric and direct an optical signal beam from one of the plurality of optical switches to another of the plurality of optical switches. In one embodiment of the present invention, a fixed incidence corrective device is included in a cascaded optical switch fabric. The incidence corrective device directs an optical signal beam in a shallow angle so that it strikes the next optical switch at a corrected incidence angle. A corrected incidence angle permits an optical signal beam to be forwarded at a relatively shallow angle to an optical switch located in a relatively close proximity on the optical switch fabric. The present invention also provides for refocusing of spreading optical signal beams and mitigation of signal loss.

Abstract: A method to program a microcontroller using a software program. First a user selects a module from a catalog of available modules. The module may be for implementing an amplifier, timer, pulse width modulator, etc. This causes information related to the selected module to be displayed. For example, a schematic and data sheet for the selected module may be displayed. Next, the user requests a position and places the selected module in a graphical user interface, which represents the resources available to implement the available modules. For example, the resources may be programmable system blocks. Additional user modules may then be selected and placed. The user then configures the circuit by selecting circuit parameters for the user modules (e.g., amplifier gain), pin configurations, and interconnections between programmable system blocks. The user may then edit source code used to cause the user modules to perform their functions.

Abstract: A method for generating a superset pinout for a family of devices. First, a pinlist is defined for each device within the family of devices. Second, a superset listing of pins is generated from the pinlist. Third, the superset pinout for the family of devices is created from said superset listing of pins to eliminate potential footprint variations within the family of devices. Fourth, each pin of the superset pinout associated with each member of the family of devices is marked.

Abstract: A fast pipelined adder/subtractor using increment/decrement functions with reduced register utilization. Embodiments of the present invention replace double width registers with incrementor elements, pipelined single width registers, and pipelined carry bits. This is made possible by positioning the adder elements at the first pipestage in each of the pipelines. Single width registers are used to hold the results of the initial add/subtract operation. Single bit registers pipeline the carry bits from the adders and incrementors to the next stage. The incrementor collects the sum from one of the adder elements, the pipelined carry bit from that adder element, and the carry bit from a previous stage adder and combines them to produce a new result and carry. This new result is passed along the pipeline to the output bus of the circuit. In this fashion, no double width busses or registers are required in between individual pipestages of the pipelines.

Abstract: A memory device (200) can include memory cell arrays (202-a and 202-b) accessed according to phase shifted clock signals. Memory cell array (202-a) can be accessed at double data rates essentially synchronous with clock signal CLK. Memory cell array (202-b) can be accessed at double data rates essentially synchronous with a phase delayed clock signal DCLK. Such an arrangement can provide eight data accesses (four reads and four writes) in a single clock cycle.

Abstract: A serializer within, for example, a transceiver is provided having multiple stages of pipelined multiplexing cells. Each multiplexing cell may be substantially the same and each comprises no more than one latch. In some embodiments, each multiplexing cell includes a multiplexer comprising a pair of inputs and a single latch, which is coupled to one input of the multiplexer. No latches are coupled to the other input of the multiplexer. The serializer generally includes a plurality of stages. Each successive stage includes one-half the number of multiplexing cells included in the previous stage, and each successive stage is clocked by a clocking signal that transitions at twice the frequency of the previous stage clock signal.

Abstract: A microcontroller having a dual mode relax oscillator that is trimmable. In one embodiment, the present invention provides a relaxation oscillator circuit comprising two current sources for establishing a reference voltage for use in causing the relaxation oscillator circuit to operate in two power modes, and a control coupled to both current sources for switching between power modes. In one embodiment, one power mode is a low power mode for standard operation of the microcontroller and one power mode is a very low power mode for use in a sleep mode. In one embodiment, the relaxation oscillator circuit further comprises digitally trimmable components operable to control a current charging a capacitor of the relaxation oscillator circuit to account for process variation in the capacitor, wherein the current is for controlling a frequency of the microcontroller.

Abstract: A frame configured to (i) be transmitted on a network and (ii) store data packets in a plurality of channels. One or more of the plurality of channels may be configured to store one or more fragments of the data packets.

Abstract: A system and method that converts a series of input data words at a first data width to a series of output data words at a smaller data width. In order to achieve 10-Gigabit Ethernet over an optical network, data must be converted from 66-bit words to 64-bit words (the smaller data width) at a faster clock rate, such that the concatenation of the series of input data is equivalent to the concatenation of the series of output data. This is accomplished by shifting the input data such that it is either prefixed by zeros, suffixed by zeros, or both, depending on the stage of the progression of the series. The shifted data is then split up, with a portion of the data going into a delay register and another portion of the data either being output directly or combined with data previously stored in the delay register.

Abstract: A method for computing a sum or difference and a carry-out of numbers in product-term based programmable logic comprising the steps of: (A) generating (i) a portion of the sum or difference and (ii) a lookahead carry output in each of a plurality of logic blocks; (B) communicating the lookahead carry output of each of the logic blocks to a carry input of a next logic block; (C) presenting the lookahead carry output of a last logic block as the carry-out.

Abstract: A method for providing orderly service delivery to clients over a network, comprising the steps of (A) requesting data from a location and (B) if a denial is received, notifying a particular client of availability.

Abstract: A method and system of automatically generating information in a grid structure on a display screen. In one embodiment, the present invention is directed to displaying and editing microcontroller chip configuration information. The method involves reading a data file describing a configurable sub-system of the microcontroller, identifying the configurable parameters of the sub-system and constructing a two dimensional display for displaying the values of variables associated with those parameters. The two dimensional display (“display grid”) may contain a row for each parameter, a column for the name of the parameter, and a cell in each row for each variable associated with that parameter. The cells associated with variables can be restricted to accept values chosen from a set enumerated in the data file describing the configurable sub-system.

Abstract: An apparatus comprising one or more nodes. The apparatus may be configured to transport one or more packets within a frame. The one or more nodes may be configured to add and/or drop at least one of the one or more packet from the frame.

Abstract: A method for reading a position of a wiper on a potentiometer, comprising the steps of (A) charging a capacitor connected to a wiper terminal of the potentiometer, (B) discharging the capacitor through a particular terminal of the potentiometer, (C) measuring a first time taken to discharge the capacitor from a first voltage to a second voltage, (D) recharging the capacitor, (E) discharging the capacitor through another particular terminal of the potentiometer, (F) measuring a second time taken to discharge the capacitor from the first voltage to the second voltage, (G) reading the position of the wiper by calculating a ratio of the times measured in steps (C) and (F).

Abstract: A priority encoder circuit (300) for a content addressable memory (CAM) device is disclosed that may include a priority selection circuit (310) that receives match results (M0 to Mz) and provides prioritized match results (P0 to Pz), and a logic section (350) that logically combines prioritized match results (P0 to Pz) to generate a smaller number of encoder inputs (RWL0 to RWLr). A logic section (350) can also generate a first portion (ID0) of an encoded value (ID0 to IDX). Encoder entries (314-0 to 314-r) may each generate a second portion (ID1 to IDX) of an encoded value (ID0 to IDX).

Abstract: An apparatus comprising a first circuit, a second circuit and a third circuit. The first circuit may be configured to communicate as a host through a first interface. The second circuit may be configured to communicate through a second interface as a host when in a first mode and as a peripheral when in a second mode. The third circuit may be configured to (i) control the first and the second circuits and (ii) transfer information between the first and the second circuits.