Abstract: Peer-to-peer Direct Memory Access (DMA) permits the efficient transfer of data from one DMA capable Application Specific Integrated Circuit (ASIC) block to another without accessing memory. The peer-to-peer transfer can be done over a standard AMBA AHB bus architecture without side band signals and without violating the AHB specification.

Abstract: An apparatus comprising a power supply device configured to generate a voltage. The voltage may comprise either (i) a standard voltage level or (ii) a power down voltage level. The power down voltage level may be configured to reduce current consumption.

Abstract: A method of synchronizing a clock signal to a data signal, comprising the steps of (A) detecting a first edge of the data signal and a position of the first edge, (B) determining if the position is within a zone, (C) if the edge is not within the zone, adjusting the clock signal towards the position of the edge, (D) detecting a second edge of the data signal and a position of the second edge, (E) determining a in value indicating a position of the second edge, (F) adding the first value to a second value, wherein the second value indicates a position of a third edge of the data signal and (G) adjusting the clock signal based on the result of step (F).

Abstract: An integrated circuit including a first cell configured to perform boundary scan testing, and an I/O node coupled to the first cell, wherein the I/O node is configured to carry a first differential signal. A level translator may be coupled between the I/O node and the first cell, wherein the level translator is configured to translate the first differential signal into a single ended signal. A level translator may be coupled between the I/O node and the first cell, wherein the level translator is configured to translate a single ended signal into the first differential signal. Core logic may be coupled to the first cell, wherein the core logic is configured to process a second differential signal, and a level translator may be coupled between the core logic and the first cell, wherein the level translator is configured to translate the second differential signal into a single ended signal.

Abstract: A programmable logic block in an integrated circuit comprising a plurality of macrocells, an AND-array, an OR-array, and a logic circuit. The plurality of macrocells may comprise logic that may be configured to (i) generate and propagate an inverted carry-input signal and (ii) generate a sum bit. The AND-array may comprise at least two product terms per macrocell. The OR-array may be configured to generate a sum-of-products term for each macrocell in response to the two product terms. The logic circuit may be configured to (a) receive (i) the product terms and (ii) the carry-input signal generated by a first macrocell of the plurality of macrocells and (b) generate (i) a block carry-propagate signal, (ii) a block carry-generate signal, and (iii) a block carry-output signal.

Abstract: A content addressable memory (CAM) device (100) may include a number of sub-blocks (102-8 to 102-15) that can generate CAM search results. In a “search beyond” operation, sub-blocks (102-8 to 102-15) may be excluded from a search operation according to criteria, including a sub-block address and a soft-priority value. A CAM device may include a compare circuit (400) that may compare sub-block address values in a time division multiplexed fashion to establish priority from among multiple CAM sub-blocks.

Abstract: The present invention is an efficient system and method for cascading optical switches in architectures that enable three dimensional multi-plane optical signal beam steering to be performed with two dimensional steering devices. A plurality of cascaded optical switches form a cascaded multi-plane optical switch fabric and direct an optical signal beam from one of the plurality of optical switches to another of the plurality of optical switches in a different plane. In addition, a multi-plane directional device directs an optical signal beam from a first optical switch stage to a second optical switch stage oriented in a different plane. Furthermore, a fixed incidence corrective device directs an optical signal beam in a shallow angle to an optical switch located in a relatively close proximity on the optical switch fabric and a optical signal beam spread correction device provides for refocusing of spreading optical signal beams and mitigation of signal loss.

Abstract: The present invention provides a circuit capable of driving a diode with multiple amounts of current with a low supply voltage without the requirement of alternating current coupling. The circuit provides for headroom voltage for the current sources allowing them to operate correctly without the requirement of external components such as inductors to provide coupling. The circuit may provide one of at least two different amounts of current depending upon the voltage of at least two inputs suitable for driving a vertical cavity surface emitting laser diode.

Abstract: An apparatus comprising a circuit configured to generate a spread spectrum clock signal. The circuit may comprise a voltage controlled oscillator with a gain that may be automatically controlled.

Abstract: A method of making a semiconductor structure comprises forming a hole through a first dielectric layer; followed by forming a hole through an etch-stop layer, to expose a first conducting layer. The thickness of the etch-stop layer is at least one-half the smallest line width of the first conducting layer.

Abstract: A circuit arrangement permits a microcontroller wirebond pad to be configured to be an analog or digital input or output. The circuit arrangement uses any of a plurality of switching configurations to selectively determine the use of the wirebond pad under control of the microcontroller's processor. The microcontroller can be configured using configurable analog and configurable digital blocks to perform any of a plurality of functions with certain of the pinouts determined under program control.

Abstract: In one embodiment, a schematic for a net includes a load and a load schematic. The load schematic may include a parasitic on the net, and an equivalent of the load. A buffer may be employed to couple the load schematic to the schematic. Among other advantages, this simplifies comparison of parasitics between the schematic and a corresponding layout.

Abstract: In one embodiment, a via structure includes a liner, a barrier layer over the liner, and an aluminum layer over the barrier layer. The barrier layer helps minimize reaction between the aluminum layer and the liner, thus helping minimize void formation in the via. The liner and the barrier layer may be deposited in-situ by ionized metal plasma (IMP) physical vapor deposition (PVD). In one embodiment, the liner comprises titanium, while the barrier layer comprises titanium nitride.

Abstract: A variable-mode digital logic circuit is provided for accepting and serializing a parallel data word, so that the parallel data word may be transmitted from the digital logic circuit over a single one-bit wide trace. In some embodiments, the variable-mode digital logic circuit may include a plurality of parallel data traces for receiving the parallel dataword, a plurality of select-capable multiplexor circuits for sequentially activating certain ones of the parallel data traces and for multiplexing the received data into a serial data stream, a ring counter for controlling a frequency of specific operations performed within the circuit, and at least one additional multiplexor circuit array for receiving data output from the plurality of select-capable multiplexor circuits and for further serializing the received data for output on the single one-bit wide trace. The digital logic circuit may be adapted to operate according to one of a plurality of variable modes.

Abstract: A concentrator connects multiple downstream devices to an upstream host using the same device address. The concentrator combines together configuration information obtained from the multiple downstream devices. The combined information appears to the host as coming from the same device. Multiple peripheral controllers may be configured to respond to different endpoints or alternate interfaces associated with the same device address. In one implementation, the downstream devices, the concentrator, and the upstream host all communicate using Universal Serial Bus (USB) connections.

Abstract: An apparatus comprising a first circuit and a second circuit. The first circuit may be configured to (i) select one of a plurality of input signals and (ii) generate (a) an output signal having a frequency and (b) one or more control signals in response to a skew signal. The second circuit may be configured to generate the skew signal in response to the one or more control signals. The first circuit may be configured to minimize skew between the selected input signal and a feedback of the output signal, in response to the skew signal.

Abstract: An adaptive driver and method is presented for communicating between an operating system of a computer and various peripheral devices connected to the computer via a peripheral bus. Operating characteristics and input/output characteristics of the peripheral device and all intervening hardware devices placed between the operating system and the peripheral device are noted in a linked set of data fields, i.e., a driver stack. Serialized data transfers are coordinated using the driver stack, and each request for a data transfer is submitted to the stack in the form of an input/output request packet (IRP). Unlike conventional practice, in which IRPs must be pre-defined and hard-coded to conform to the characteristics of a particular peripheral device, the adaptive driver derives the device characteristics from data structures maintained by the operating system and constructs IRPs accordingly.

Abstract: A frame configured to transmit information via a network, comprising one or more packets each comprising a header error check portion and a payload error check portion.

Abstract: An apparatus comprising a memory, an encoder and one or more registers. The memory may be configured to (i) read and/or write a plurality of state vectors and (ii) read and/or write data. The encoder may be configured to present state vectors to be written in response to (i) data read from the memory (ii) a first address and (iii) a serial data stream. The registers may be configured to present the first address in response to an input address.

Abstract: An apparatus that may be configured to generate a wireless radio signal in response to one or more first data signals. The wireless radio signal may comprise a single frequency hopping sequence configured to support one or more peripheral wireless network devices. The apparatus may also be configured to generate the one or more first data signals in response to the wireless radio signal.