Abstract: The present invention provides a method for automatically determining, and accordingly prompting an email user as to whether an attachment is to accompany an email message prior to transmission of the message. In one embodiment, the present invention provides a method, which can prompt an email user as to whether an attachment is to accompany an email addressed to certain individuals, groups, or organizations, prior to transmission of the message. In one embodiment, a database of certain addressees to whom attachments are frequently transmitted is consulted. In one embodiment, the present invention provides a method, which automatically prompts users based on the content of an email message as to whether an attachment is desired prior to transmission. In one embodiment, a database of certain keywords appearing in message text frequently correlated with attachment inclusion is consulted. In one embodiment, the databases are automatically updated by a self-learning modality.

Abstract: A power supply detecting input receiver circuit (300) can include a multiplexing capability that can select one of at least two power supplies during a non-critical timing period. Such selection of a power supply can reduce both the standby and the active current of input receiver circuit (300). In one arrangement, an input receiver circuit (300) can include a comparator (310), a latch (316), and a select circuit (304). A latch (316) can be enabled to indicate a selection of a supply upon a circuit power-up, as but one example. A method is disclosed that includes comparing at least two supply voltages, setting a latch to indicate a selected supply, and providing the selected supply to an input receiver. The receiver output signal may be voltage-translated to a suitable internal supply level.

Abstract: A method for fabricating a metallization structure is presented. The method preferably includes ion metal plasma depositing a wetting layer within a cavity defined in a dielectric layer. The wetting layer preferably includes titanium. The method preferably further includes sputter depositing a bulk metal layer within the cavity and upon the wetting layer. Sputter depositing of the bulk metal layer is preferably performed in a single deposition chamber at least until the cavity is substantially filled.

Abstract: A state machine comprising a first input receiving a first read clock, a second input receiving a first write clock, a third input receiving a first programmable Almost Full look-ahead signal, a fourth input receiving a second read clock, a fifth input receiving a second write clock, and a sixth input receiving a second programmable Almost Full look-ahead signal is disclosed. The state machine manipulates the inputs to produce an output signal representing an Almost Full output flag that is at a first logic state when a FIFO is Almost Full and is at a second logic state when the FIFO is Not Almost Full.

Abstract: The present invention system and method enables dynamic reconfiguration of an electronic device in a convenient and efficient manner. In one embodiment, the electronic device includes a microprocessor, a plurality of internal peripherals, an interconnecting component, an external coupling port, and a memory for storing instructions. The plurality of internal peripherals, the interconnecting component and the external coupling port are programmably configurable to perform a variety of functions. The memory stores a plurality of configuration images that define the configuration and functionality of the plurality of internal peripherals, the interconnecting component and the external coupling port. The instructions stored by the memory facilitate dynamic reconfiguration of the electronic device. Based upon the existence of a predetermined condition, the electronic device is automatically reconfigured by activating different configuration images.

Abstract: A system and method are provided for synchronizing a frame of related bits output from a deserializer to the related bits serially fed to the deserializer. Synchronization is achieved by overcoming a slip bit problem by selectively increasing the frame clock cycle during times in which the slip bit occurs. The deserializer is controlled by a clock generator that can include a counter which generates the frame clock. The counter can be asynchronously or synchronously reset, without any glitches occurring within the deserializer and, thus, avoiding any invalid bits output from the deserializer. The asynchronous reset forces the counter to a deterministic state, and the synchronous reset sets the counter to a valid state. In each instance, however, resets do not impart glitches to the deserializer and the deserializer output frame is maintained synchronous to related bits serially fed to the deserializer.

Abstract: A method is provided for eliminating a polish stop layer from a polishing process. In particular, a method is provided which may include polishing an upper layer of a semiconductor topography to form an upper surface at an elevation above an underlying layer, wherein the upper surface does not include a polish stop material. Preferably, the upper surface of the topography formed by polishing is spaced sufficiently above the underlying layer to avoid polishing the underlying layer. The entirety of the upper surface may be simultaneously etched to expose the underlying layer. In an embodiment, the underlying layer may comprise a lateral variation in polish characteristics. The method may include using fixed abrasive polishing of a dielectric layer for reducing a required thickness of an additional layer underlying the dielectric layer. Such a method may be useful when exposing an underlying layer is desirable by techniques other than polishing.

Abstract: A circuit and a method of operating the circuit is provided. The method generally comprises the steps of (A) receiving an explicit error checking instruction generated outside the circuit, (B) performing an error checking operation for at least one of a plurality of memory locations within the circuit, and (C) generating a result signal from the error checking operation.

Abstract: A method for establishing frequency and phase alignment of clock signals across a domain of analog blocks coupled in a single integrated circuit. Different analog functions are implemented by selectively and electrically coupling different combinations of analog blocks. The analog blocks may be arrayed in a number of columns. A synchronized clock signal is supplied to all of the analog blocks in a combination of blocks, even when the blocks are in different columns. The frequency of the clock signal can be changed dynamically depending on the analog function to be achieved.

Abstract: A controller continuously or periodically interrogates the FAT table to determine which blocks are not storing data relative to any files stored in the memory at that time. If a block is located that is not allocated to a file, this block is erased and marked as being ready to receive data. In this way, a large file can be stored in the memory without having to wait for an erase operation to take place while the file is being written to the memory.

Abstract: A method of making a semiconductor structure includes trimming a patterned hard mask with a wet etch, wherein the hard mask is on a gate layer; and etching the gate layer. In making multiple structures on a semiconductor wafer, an average width of lines in the patterned hard mask is trimmed by at least 100 ?.

Abstract: A method to facilitate circuit design. First, a schematic and data sheet for a selected module may be displayed. Next, in response to a request for a position for the module among available resources (e.g., programmable system blocks), a potential position for the module is computed. The position is displayed on a graphical user interface by mapping the module to one or more programmable system blocks. Additional user modules may then be selected and placed. After allowing the user to configure the circuit by selecting circuit parameters and pin-outs, various items are automatically generated to facilitate programming the target device. For example, application programming interfaces (APIs) for programming an operation of the modules, source code for realizing the modules in the resources, an interrupt vector table, and a data sheet for the circuit may be automatically generated.

Abstract: A method of enumerating a peripheral device preferably includes initiating operation of the device in a low-power mode. Power can be conserved, for instance, by slowing processor speed or by shutting off clocks to one or more unneeded blocks of the peripheral device during enumeration. During enumeration, a host computer preferably obtains enumeration information from the peripheral device and then uses that information to select a configuration state for operating the device following enumeration.

Abstract: An apparatus comprising a circuit that may be configured to (i) change a frequency of one or more first signals in response to a second signal and (ii) generate a third signal in response to either the second signal or a predetermined time period expiring.

Abstract: An integrated circuit device, and associated system and method, including a microprocessor, a multipurpose memory coupled with the microprocessor, a cache controller, and a first and second memory port. In one example, the first memory port is provided for coupling a first external memory device with the cache controller, and the second memory port is provided for coupling a second external memory device with the multipurpose memory. In one example, the first memory port may be adapted to be coupled with a Flash ROM, and the second memory port may be adapted to be coupled with an EEPROM. In this manner, the integrated circuit device may be utilized in different systems that have differing memory requirements.

Abstract: An interface controller includes configuration circuitry generated based on a configuration package associated with endpoint configuration parameters. The configuration circuitry is used for configuring logic circuitry in the interface controller for different endpoint configurations.

Abstract: An apparatus coupled to a low speed tester and a device is disclosed. The device may have a first speed faster than a second speed of the low speed tester. The apparatus may be configured to allow the low speed tester to perform high speed tests of the device at the first speed.

Abstract: A content addressable memory (CAM) device (300) can receive a compare data value having a native word size. The compare data value can be split into smaller portions, with one portion can be applied to a first CAM block (302-0) and another being applied to a second CAM block (302-1) on a subsequent clock (CAMCLK) cycle. Activation of circuit elements in the second CAM block (302-1) can be conditioned on first match results (CMATCHA0 to CMATCHAn) generated by first CAM block (302-0).

Abstract: A method and system for helping a user perform tasks in software. Graphic elements (e.g., icons) are rendered and displayed regardless of which task is being performed. An element can be either active or inactive; user selection of an element with the element active initiates an action in response to the selection while user selection of the element with the element inactive will not initiate the action. Some elements are activated and other elements are deactivated according to which task is to be performed. The elements are selectively activated and deactivated to guide the user through the tasks according to the order in which the tasks are logically performed. The elements thus suggest an order for performing the tasks, guiding the user through the tasks without the need for a help utility such as a wizard.

Abstract: An apparatus comprising a first circuit and a second circuit. The first circuit may comprise a control circuit and an oscillator. The control circuit may be configured to generate a control signal in response to a first reference signal and a second reference signal. The oscillator may be configured to generate the second reference signal in response to the control signal and a timing signal. The control signal is generally held when the first reference signal is lost. The second circuit may be configured to generate one or more output signals in response to the second reference signal and one of the one or more output signals. The one or more output signals may have a controlled delay with respect to the first reference signal.