Abstract: A system where a production microcontroller is partially copied in a FPGA of an ICE to form a virtual microcontroller. The virtual microcontroller and the production microcontroller simultaneously and independently run a microcontroller code to be debugged at a high frequency. The debugging logic can substantially reside in the ICE and the ICE can perform all debugging functions. The debug interface, residing in the production microcontroller, can enable the production microcontroller to communicate with the ICE in low frequencies. The production microcontroller may request the ICE to lower its frequency when the production microcontroller encounters a halt due to outside events. A user may command resumption of the operation of both the production microcontroller and the virtual microcontroller when debugging of the codes is completed.

Abstract: A noninterfering multiply-MAC (multiply accumulate) circuit is described. The circuit is operational to perform a MAC (multiply accumulate) operation and to perform a multiply operation without interfering with the accumulate value of the MAC operation. The circuit includes a first register, a second register, a multiplier circuit, and an accumulate circuit. The first register is addressable using either a primary first address or an alias first address. Moreover, the second register is addressable using either a primary second address or an alias second address. The multiplier circuit performs a multiply operation to generate a product value based on the data in the first and second registers after a write operation to either the first register or the second register. The accumulate circuit performs an accumulate operation to generate an accumulate value if either the alias first address or the alias second address is used in the write operation.

Abstract: The present invention concerns an apparatus comprising a first circuit and a second circuit. The first circuit may be configured to generate a reference output voltage in response to a plurality of reference voltages. The second circuit may be configured to generate an output voltage in response to the reference output voltage and an unknown voltage. The output voltage may comprise accurately controlled hysteresis.

Abstract: In one embodiment, the invention is an apparatus. The apparatus includes a FIFO array having a first plurality of memory elements, each memory element having a predetermined number of bits, the FIFO array having a read pointer. The apparatus also includes a FIFO control register array having a second plurality of memory elements, each memory element of the second plurality corresponding to a memory element of the first plurality of memory elements, the read pointer suitable for accessing the FIFO control register array. The apparatus further includes a control logic block coupled to the FIFO control register array and the FIFO array. The control logic block is to receive a data value of the memory element of the FIFO control register array pointed to by the read pointer. The control logic block is also to signal the read pointer to stall responsive to the data value having a first value.

Abstract: According to one embodiment, a search engine device (100) may include an input (102), search portion (106), and a vote portion (108). A vote portion (108) may receive responses to a search request at inputs. According to precedence information in received responses, a vote portion (108) may generate an output response having its own precedence information.

Abstract: A method for delineating a frame. The method generally comprises the steps of (A) receiving the frame comprising (i) a length value incorporating a payload error detection length, (ii) a length error detection value, (iii) a payload data, and (iv) a payload error detection value having the payload error detection length, wherein the payload error detection value and the payload data occupy separate fields of the frame, (B) performing an error detection on the length value based upon the length error detection value, and (C) retrieving the payload data and the payload error detection value based upon the length value in response to passing the error detection on the length value.

Abstract: A microcontroller provides protection to memory blocks in an embedded memory. A set of rules such as security levels mapped to memory blocks are stored in a nonvolatile supervisory memory. An algorithm for application of the rules is stored in a supervisory ROM. When a read or write operation is to be carried out, the rules are applied according to the algorithm in order to authorize or reject the read or write operation. Security levels can be modified, but only according to defined rules. In one embodiment, the security levels can only be increased.

Abstract: One embodiment of the present invention includes a microcontroller that enables its on-chip microprocessor to write data into a register of an on-chip programmable analog circuit even though the two circuits may be operating at different frequencies. Specifically, the microcontroller includes a write synchronization circuit that helps facilitate the write operation between these two circuits. For example, the write synchronization circuit is coupled to receive write cycle signals from the microprocessor and is also coupled to receive trigger signals based on a clocking signal received by the programmable analog circuit. Therefore, upon receiving a write cycle signal, the write synchronization circuit has the ability (if needed) to stall the microprocessor's operations until the optimum time for writing data into the register for controlling the programmable analog circuit.

Abstract: A method for synchronizing a clock signal to a data signal, comprising the steps of (A) detecting an edge of the data signal, (B) determining whether a position of the edge is within a zone and (B) if the edge is not within the zone, adjusting the clock signal towards the position of the edge.

Abstract: A system and method of testing switch functionality of a tunable capacitor array is disclosed. A built in test (BIT) circuit provides digital device for testing the functionality of a programmable switch capacitor array circuit. The method and system provides for switching a capacitor switch of a switch capacitor array between on and off, switching a test enable switch of a BIT circuit between on and off, pulling an internal node of the BIT circuit either high or low using a current source, and determining whether the internal node has been pulled either high or low. In addition, the method and system provides for making a pass or fail determination based on a determined state of the internal node.

Abstract: An apparatus comprising a control circuit and a first circuit. The first circuit may be configured to generate a calibration signal in response to an adjustment signal and a first control signal. The control circuit may be configured to generate (i) the first control signal, (ii) a second control signal and (iii) the adjustment signal in response to a rate of an input signal.

Abstract: A method and logic for providing an asynchronous interface to a synchronous memory is disclosed. One embodiment of the present invention provides for a memory having a first logical unit which is operable to generate a synchronized clock signal in response to a chip select signal to the memory. The memory comprises synchronous memory arrays. The synchronized clock signal is input to the selected synchronous memory array. This allows an access to the synchronous memory to complete within a timing budget of the asynchronous interface. Furthermore, the memory has a second logical unit which is operable, in response to the chip select signal and a second signal input to the memory, to put an input/output bus coupled to the synchronous memory into a high impedance state by the end of the memory access. The second input signal may be a read enable or a write enable signal.

Abstract: A FIFO memory system for multiple input channels, has a channel control logic coupled to a channel input signal. A pointer and flag logic block is coupled to an output of the channel control logic. A memory has an address bus coupled to the channel control logic and the pointer and flag logic.

Abstract: A method of forming a semiconductor structure comprises forming an etch-stop layer comprising nitride, on a stack. The stack is on a semiconductor substrate, and the stack comprises (i) a gate layer. The forming is by CVD with a gas comprising a first compound which is SixL2x, and a second compound comprising nitrogen and deuterium, L is an amino group, and X is 1 or 2.

Abstract: An architecture comprising a first circuit, a second circuit, and one or more pairs of communication channels. The first circuit may be configured to transmit one or more first serial streams in response to a plurality of first source data streams and recover a plurality of second source data streams from one or more second serial streams. The second circuit may be configured to transmit the one or more second serial streams in response to the plurality of second source data streams and recover the plurality of first source data streams in response to the one or more first serial streams. The first circuit and the second circuit may be coupled by the one or more pairs of communication channels. The first and second circuits may be configured to transmit simultaneously.

Abstract: A method of testing a circuit having a plurality of one-time programmable cells. The method generally comprises the steps of (A) transmitting a plurality of addresses to the circuit and (B) receiving a plurality of values from the circuit each representing at least one of the one-time programmable cells in response to one of the addresses.

Abstract: A programmable analog system architecture and method thereof are described. The analog system architecture and method introduce a single chip solution that contains a set of tailored analog blocks and elements that can be configured and reconfigured in different ways to implement a variety of different analog functions. The architecture includes an array of analog blocks, including continuous time blocks and different types of switched capacitor blocks. The analog blocks can be electrically coupled to each other in different combinations to perform different analog functions. Each analog block includes analog elements that have changeable characteristics that can be specified according to the function to be performed. The architecture thereby facilitates the design of customized chips at less time and expense.

Abstract: In one embodiment, a method of fabricating an integrated circuit includes forming a low-k dielectric layer over metal lines, forming an adhesion layer over the low-k dielectric layer, and forming a capping layer over the adhesion layer. The low-k dielectric may comprise SiLK™ dielectric material, while the capping layer may comprise TEOS. The resulting stack of dielectric materials may be employed in a passivation level to protect the metal lines. For example, a topside layer may be formed over the capping layer.

Abstract: According to one embodiment, a timing circuit (300) can include a first control circuit (302), a first clocked circuit (304), a second clocked circuit (306), and a second control circuit (314). A first control circuit (302) may compensate for a first timing signal FCLK making a transition earlier in time than a second timing signal RCLK. A second control circuit (314) may compensate for a second timing signal RCLK making a transition earlier in time than a first timing signal FCLK. A first timing signal FCLK can be a periodic signal generated by a first PLL type circuit (310) in response to a falling edge of an external clock signal EXT CLK. A second timing signal RCLK can be a periodic signal generated by a second PLL type circuit (312) in response to a rising edge of an external clock signal EXT CLK.

Abstract: An amplifier system has a control circuit. An amplifier is coupled to the control circuit and has a controllable gain. A controllable input impedance circuit is coupled to the control circuit. When the gain of the amplifier is changed the controllable input impedance circuit's impedance is adjusted, so that the input impedance to the system remains essentially constant.