Abstract: An integrated back-end integrated circuit (IC) manufacturing assembly is disclosed. In one embodiment, the present invention has a front-of-line portion comprising a plurality of integrated sub-stations for operating on a first plurality of die-strips on an in-line basis to produce a second plurality of die-strips. The present embodiment further comprises an end-of-line portion coupled to the front-of-line portion and comprising a plurality of integrated sub-stations for operating on the second plurality of die-strips on an in-line basis to produce die-strip components. The present embodiment also comprises an in-line test portion coupled to the end-of-line portion for testing the die-strip components. The present embodiment further comprises a finish portion coupled to the in-line test portion and comprising a plurality of integrated sub-stations operating on tested die-strip components.

Abstract: An apparatus for coupling a peripheral device to a host comprising an interface circuit and a logic circuit. The interface circuit may be configured to (i) receive a request from the host and (ii) present a response to the host. The logic circuit may be configured to (i) generate the response when the request is serviceable by the apparatus or (ii) pass the request to an external circuit when the request is not serviceable by the apparatus.

Abstract: An apparatus comprising a first device and a bus interface. The first device may be configured to present one or more control signals in response to one or more input instructions. The bus interface may be configured to (i) receive the one or more control signals and (ii) provide power to the device.

Abstract: An apparatus comprising a microcontroller configured to (i) send or receive data over one or more data lines when in a first mode and (ii) be programmed through said data lines when in a second mode.

Abstract: A circuit configured to provide a storage device comprising one or more virtual multiqueue FIFOs. The circuit is generally configured to operate at a preferred clock speed of a plurality of clock speeds.

Abstract: A method is provided for processing a semiconductor topography. In particular, a method is provided for decreasing the threshold voltage magnitude of a first transistor being formed within the substrate while simultaneously increasing the threshold voltage magnitude of a second transistor being formed within the substrate. In some embodiments, a width of the first transistor may be larger than a width of the second transistor. In addition or alternatively, the method may include performing a first implantation corresponding to a threshold voltage magnitude above a desired value for the first transistor. The method may further include performing a second implantation to simultaneously lower the threshold voltage magnitude of the first transistor and raise a threshold voltage magnitude of the second transistor. In some embodiments, the method may include introducing dopants of a first conductivity type into a first transistor channel dopant region and a second transistor channel dopant region simultaneously.

Abstract: An apparatus comprising a circuit configured to select one of a number of identification (ID) codes in response to a voltage level at one or more pins.

Abstract: Checking the consistency of a lock step process while debugging a microcontroller code is in progress. A method provides a production microcontroller to execute an instruction code and provides the result of the instruction code to an ICE. The ICE, independent from the production microcontroller and simultaneously, executes the same instruction code and produces a result. The ICE compares the result of its computation and the result received from the production microcontroller. The ICE issues a “lock step error” when the result of the comparison is a mismatch. A trace buffer residing in the host device provides the location of the line of code causing the mismatch. After identifying the line of code causing the mismatch the user debugs the erroneous line of code. The debugging process resumes on the next line of code in the microcontroller code under test.

Abstract: An apparatus comprising a first circuit and a second circuit. The first circuit may be configured to present a parallel output data signal in response to (i) a first clock signal and (ii) one or more serial data signals. The second circuit may be configured to present the one or more serial data signals and the first clock signal in response to (i) a second clock signal and (ii) a parallel input data signal.

Abstract: An antenna for a wireless communications device may be configured in a variety of shapes. The antenna is not limited to a two dimensional space, but may incorporate conductive antenna elements from an integrated circuit package, a circuit board to which the integrated circuit package mounts, and signal conducting connecting means between the integrated circuit package and the circuit board.

Abstract: An apparatus comprising a wireless transceiver and a programmable logic circuit. The wireless transceiver may be coupled to the programmable logic circuit. The programmable logic circuit may comprise a programmable logic device, a processor, and a memory circuit, implemented in a single integrated circuit package.

Abstract: According to one embodiment (100), a method of forming borderless contacts may include forming a composite layer over a first insulating layer (102). A contact hole may be formed through a composite layer and a first insulating layer (104). A conducting layer may then be formed (106), including within a contact hole. Portions of a conducting layer may then be removed with a composite layer as a polish stop (108), and a contact structure may be formed. A first interconnect structure and a second insulating layer may then be formed over a first insulating layer (110 and 112). A borderless contact pattern may then be etched with a composite layer as an etch stop (114).

Abstract: A current controlled delay circuit is disclosed. Two currents of constant sum are generated to control the delay of the circuit. The circuit includes a differential pair to switch one of the two currents from one leg of the circuit to another leg of the circuit. The circuit includes a cross-coupled pair to switch the other of the two currents from one leg of the circuit to another leg of the circuit. The circuit may include a fixed or variable load.

Abstract: A method for altering timing between transmissions of an input device comprising the steps of (A) receiving a plurality of inputs from the input device, (B) altering the timing between the inputs and (C) presenting the altered inputs in a potentially insecure environment.

Abstract: A method for testing a semiconductor memory device includes forcing the device into a logic state configuration that does not occur during normal operation of the device. The method may also include holding the logic state configuration for a user-variable length of time. In an embodiment, the device testing method includes flowing a direct current through a first input node of a bi-stable latch. This node may be electrically arranged between a node coupled to a voltage source and a node coupled to a circuit ground potential. An embodiment of a memory device may include testmode circuitry adapted to maintain a pair of bitlines at logic states that are not maintained during ordinary operation of the device. A system for testing a semiconductor memory device may include testmode circuitry adapted to force a pair of bitlines to the same logic state for a user-determined length of time.

Abstract: An apparatus comprising a first delay circuit. The first delay circuit may be configured to present a data delayed signal having one of a plurality of delay times. The plurality of delay times may provide a user configurable setup/hold time.

Abstract: A content addressable memory (CAM) device (100) may include a CAM array (102), a CAM array access circuit (104), and a preclassifier circuit (106). A preclassifier circuit (106) may selectively modify portions of an input data value before such an input data value is applied to a CAM array (102). In particular embodiments, a preclassifier circuit (106) may compare a compare portion of an input data value to one or more ranges. If such a portion falls within a range, a preclassifier may substitute a compare portion with a range code value to form a modified input data value.

Abstract: A method is provided for determining a concentration profile of an impurity within a layer of a semiconductor topography. The method may include exposing the layer and an underlying layer to oxidizing conditions. In addition, the method may include comparing thickness measurements of total dielectric above the underlying layer taken before and after exposing the topography to oxidizing conditions . In some cases, the comparison may include plotting pre-oxidation thickness measurements versus post-oxidation measurements. In other embodiments, the comparison may include determining differences between the pre-oxidation and post-oxidation thickness measurements and correlating the differences to concentrations of the impurity. In some cases, such a correlation may include subtracting a concentration of the impurity at a first location along the semiconductor topography from a concentration of the impurity at a second location along the semiconductor topography.

Abstract: This invention relates to a method of forming a local interconnect and a semiconductor device comprising a local interconnect. The semiconductor device comprises: a) a dielectric outside layer; and b) a conductivity structure comprising: i) at least one barrier layer having a thickness of 10-200 ? on a surface of said oxide layer; and ii) a conductive layer comprising titanium, on said at least one barrier layer, said at least one barrier layer preventing diffusion of oxygen from said dielectric oxide layer into said conductive layer and having a corresponding oxide that is not soluble in said conductive layer.

Abstract: In one embodiment, a metal level includes a plurality of metal lines. A low-k dielectric is deposited over the metal level such that an air gap forms at least between two metal lines. The relatively low dielectric constant of the low-k dielectric reduces capacitance on metal lines regardless of whether an air gap forms or not. The air gap in the low-k dielectric further reduces capacitance on metal lines. The reduced capacitance translates to lower RC delay and faster signal propagation speeds.